Initial creation of sourceware repository
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Stan Shebs
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388
sim/w65/interp.c
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388
sim/w65/interp.c
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/* Simulator for the WDC 65816 architecture.
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Written by Steve Chamberlain of Cygnus Support.
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sac@cygnus.com
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This file is part of W65 sim
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THIS SOFTWARE IS NOT COPYRIGHTED
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Cygnus offers the following for use in the public domain. Cygnus
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makes no warranty with regard to the software or it's performance
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and the user accepts the software "AS IS" with all faults.
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CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
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THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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*/
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#include "config.h"
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#include <stdio.h>
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#include <signal.h>
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#ifdef HAVE_STDLIB_H
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#include <stdlib.h>
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#endif
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#ifdef HAVE_TIME_H
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#include <time.h>
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#endif
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#ifdef HAVE_UNISTD_H
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#include <unistd.h>
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#endif
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#include <sys/param.h>
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#include "bfd.h"
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#include "callback.h"
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#include "remote-sim.h"
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#include "../../newlib/libc/sys/w65/sys/syscall.h"
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#include "interp.h"
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saved_state_type saved_state;
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int
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get_now ()
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{
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return time ((long *) 0);
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}
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void
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control_c (sig, code, scp, addr)
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int sig;
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int code;
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char *scp;
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char *addr;
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{
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saved_state.exception = SIGINT;
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}
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wai ()
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{
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saved_state.exception = SIGTRAP;
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}
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wdm (acc, x)
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int acc;
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int x;
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{
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int cycles;
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/* The x points to where the registers live, acc has code */
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#define R(arg) (x + arg * 2)
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unsigned R0 = R(0);
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unsigned R4 = R(4);
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unsigned R5 = R(5);
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unsigned R6 = R(6);
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unsigned R7 = R(7);
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unsigned R8 = R(8);
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unsigned char *memory = saved_state.memory;
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int a1 = fetch16 (R (4));
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switch (a1)
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{
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case SYS_write:
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{
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int file = fetch16 (R5);
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unsigned char *buf = fetch24 (R6) + memory;
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int len = fetch16 (R8);
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int res = write (file, buf, len);
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store16 (R0, res);
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break;
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}
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case 0:
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printf ("%c", acc);
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fflush (stdout);
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break;
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case 1:
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saved_state.exception = SIGTRAP;
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break;
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default:
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saved_state.exception = SIGILL;
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break;
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}
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}
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void
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sim_resume (step, insignal)
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int step;
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int insignal;
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{
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void (*prev) ();
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register unsigned char *memory;
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if (step)
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{
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saved_state.exception = SIGTRAP;
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}
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else
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{
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saved_state.exception = 0;
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}
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prev = signal (SIGINT, control_c);
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do
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{
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int x = (saved_state.p >> 4) & 1;
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int m = (saved_state.p >> 5) & 1;
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if (x == 0 && m == 0)
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{
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ifunc_X0_M0 ();
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}
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else if (x == 0 && m == 1)
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{
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ifunc_X0_M1 ();
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}
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else if (x == 1 && m == 0)
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{
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ifunc_X1_M0 ();
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}
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else if (x == 1 && m == 1)
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{
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ifunc_X1_M1 ();
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}
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}
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while (saved_state.exception == 0);
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signal (SIGINT, prev);
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}
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init_pointers ()
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{
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if (!saved_state.memory)
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{
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saved_state.memory = calloc (64 * 1024, NUMSEGS);
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}
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}
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int
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sim_write (addr, buffer, size)
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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{
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int i;
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init_pointers ();
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for (i = 0; i < size; i++)
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{
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saved_state.memory[(addr + i) & MMASK] = buffer[i];
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}
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return size;
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}
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int
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sim_read (addr, buffer, size)
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SIM_ADDR addr;
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unsigned char *buffer;
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int size;
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{
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int i;
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init_pointers ();
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for (i = 0; i < size; i++)
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{
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buffer[i] = saved_state.memory[(addr + i) & MMASK];
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}
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return size;
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}
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struct
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{
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unsigned int *ptr;
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int size;
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}
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rinfo[] =
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{
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&saved_state.r[0], 2,
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&saved_state.r[1], 2,
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&saved_state.r[2], 2,
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&saved_state.r[3], 2,
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&saved_state.r[4], 2,
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&saved_state.r[5], 2,
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&saved_state.r[6], 2,
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&saved_state.r[7], 2,
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&saved_state.r[8], 2,
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&saved_state.r[9], 2,
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&saved_state.r[10], 2,
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&saved_state.r[11], 2,
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&saved_state.r[12], 2,
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&saved_state.r[13], 2,
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&saved_state.r[14], 2,
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&saved_state.r[15], 4,
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&saved_state.pc, 4,
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&saved_state.a, 4,
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&saved_state.x, 4,
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&saved_state.y, 4,
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&saved_state.dbr, 4,
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&saved_state.d, 4,
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&saved_state.s, 4,
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&saved_state.p, 4,
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&saved_state.ticks, 4,
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&saved_state.cycles, 4,
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&saved_state.insts, 4,
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0
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};
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int
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sim_store_register (rn, value, length)
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int rn;
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unsigned char *value;
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int length;
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{
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unsigned int val;
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int i;
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val = 0;
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for (i = 0; i < rinfo[rn].size; i++)
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{
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val |= (*value++) << (i * 8);
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}
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*(rinfo[rn].ptr) = val;
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return -1;
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}
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int
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sim_fetch_register (rn, buf, length)
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int rn;
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unsigned char *buf;
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int length;
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{
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unsigned int val = *(rinfo[rn].ptr);
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int i;
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for (i = 0; i < rinfo[rn].size; i++)
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{
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*buf++ = val;
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val = val >> 8;
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}
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return -1;
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}
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sim_reg_size (n)
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{
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return rinfo[n].size;
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}
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int
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sim_trace ()
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{
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return 0;
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}
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void
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sim_stop_reason (reason, sigrc)
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enum sim_stop *reason;
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int *sigrc;
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{
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*reason = sim_stopped;
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*sigrc = saved_state.exception;
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}
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int
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sim_set_pc (x)
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SIM_ADDR x;
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{
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saved_state.pc = x;
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return 0;
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}
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void
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sim_info (verbose)
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int verbose;
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{
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double timetaken = (double) saved_state.ticks;
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double virttime = saved_state.cycles / 2.0e6;
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printf ("\n\n# instructions executed %10d\n", saved_state.insts);
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printf ("# cycles %10d\n", saved_state.cycles);
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printf ("# real time taken %10.4f\n", timetaken);
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printf ("# virtual time taken %10.4f\n", virttime);
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if (timetaken != 0)
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{
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printf ("# cycles/second %10d\n", (int) (saved_state.cycles / timetaken));
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printf ("# simulation ratio %10.4f\n", virttime / timetaken);
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}
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}
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void
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sim_open (kind, cb, abfd, argv)
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SIM_OPEN_KIND kind;
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host_callback *cb;
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struct _bfd *abfd;
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char **argv;
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{
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}
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#undef fetch8
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fetch8func (x)
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{
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if (x & ~MMASK)
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{
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saved_state.exception = SIGBUS;
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return 0;
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}
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return saved_state.memory[x];
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}
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fetch8 (x)
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{
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return fetch8func(x);
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}
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void
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sim_close (quitting)
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int quitting;
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{
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/* nothing to do */
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}
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int
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sim_load (prog, from_tty)
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char *prog;
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int from_tty;
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{
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/* Return nonzero so gdb will handle it. */
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return 1;
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}
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void
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sim_create_inferior (abfd, argv, env)
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struct _bfd *abfd;
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char **argv;
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char **env;
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{
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SIM_ADDR start_address;
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int pc;
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if (abfd != NULL)
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start_address = bfd_get_start_address (abfd);
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else
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start_address = 0; /*??*/
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/* ??? We assume this is a 4 byte quantity. */
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pc = start_address;
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sim_store_register (16, (unsigned char *) &pc);
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}
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void
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sim_set_callbacks (ptr)
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struct host_callback_struct *ptr;
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{
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}
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