Initial creation of sourceware repository

sim/fr30/ChangeLog

@@ -0,0 +1,287 @@
+1999-02-09  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (SIM_EXTRA_DEPS): Add fr30-desc.h, delete cpu-opc.h.
+	* configure.in (sim_link_files,sim_link_links): Delete.
+	* configure: Rebuild.
+	* decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+	* fr30.c (fr30bf_model_fr30_1_u_cti): CGEN_INSN_ATTR renamed to
+	CGEN_INSN_ATTR_VALUE.
+	* mloop.in (extract-pbb): Ditto. Use idesc->length to get insn length.
+	* sim-if.c (sim_open): fr30_cgen_cpu_open renamed from
+	fr30_cgen_opcode_open.  Set disassembler.
+	(sim_close): fr30_cgen_cpu_open renamed from fr30_cgen_opcode_open.
+	* sim-main.h: Don't include cpu-opc.h,cpu-sim.h. Include
+	fr30-desc.h,fr30-opc.h,fr30-sim.h.
+
+1999-01-27  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Rebuild.
+
+1999-01-15  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,decode.h,model.c: Regenerate.
+	* fr30.c (fr30bf_model_insn_before): Clear load_regs_pending.
+	(fr30bf_model_insn_after): Copy load_regs_pending to load_regs.
+	(fr30bf_model_fr30_1_u_exec): Check for load stalls.
+	(fr30bf_model_fr30_1_u_{cti,load,store}): Ditto.
+
+1999-01-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* arch.c,arch.h,cpuall.h: Regenerate.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+	* devices.c (device_io_write_buffer): Remove some m32r cruft.
+	* fr30-sim.h (FR30_MISC_PROFILE): Delete, plus supporting macros.
+	(EIT_*,MSPR_*,MLCR_*,MPMR_*): Delete, m32r cruft.
+	* fr30.c (fr30bf_model_insn_after): Update cycle counts.
+	(check_load_stall): New function.
+	(fr30bf_model_fr30_1_u_exec): Update argument list.
+	(fr30bf_model_fr30_1_u_{cti,load,store,ldm,stm}): New functions.
+	* sim-if.c (sim_open): Comment out memory mapped device allocation.
+	Delete FR30_MISC_PROFILE handling.
+	(print_fr30_misc_cpu): Delete.
+	* sim-main.h (_sim_cpu): Delete member fr30_misc_profile.
+	* traps.c (sim_engine_invalid_insn): PCADDR->IADDR.
+
+1999-01-11  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (fr30-clean): rm eng.h.
+
+	* sim-main.h: Delete inclusion of ansidecl.h.
+	Include sim-basics.h before cgen-types.h.
+	Delete inclusion of cgen-scache.h,cgen-cpu.h,cgen-trace.h,cpuall.h.
+	* cpu.h,sem-switch.c,sem.c: Regenerate.
+
+1999-01-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (MAIN_INCLUDE_DEPS): Delete.
+	(INCLUDE_DEPS,OPS_INCLUDE_DEPS): Delete.
+	(sim-if.o,arch.o,devices.o): Use SIM_MAIN_DEPS.
+	(FR30BF_INCLUDE_DEPS): Use CGEN_MAIN_CPU_DEPS.
+	(mloop.o,cpu.o,decode.o,sem.o,model.o): Simplify dependencies.
+	* cpu.c,cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+	* fr30-sim.h (fr30bf_h_sbit_[gs]et_handler): Declare.
+	([GS]ET_H_SBIT): Define.
+	(fr30bf_h_ccr_[gs]et_handler): Declare.
+	([GS]ET_H_CCR): Define.
+	(fr30bf_h_scr_[gs]et_handler): Declare.
+	([GS]ET_H_SCR): Define.
+	(fr30bf_h_ilm_[gs]et_handler): Declare.
+	([GS]ET_H_ILM): Define.
+	(fr30bf_h_ps_[gs]et_handler): Declare.
+	([GS]ET_H_PS): Define.
+	(fr30bf_h_dr_[gs]et_handler): Declare.
+	([GS]ET_H_DR): Define.
+	* fr30.c (all register access fns): Rename to ..._handler.
+	(fr30bf_h_*_get_handler,fr30bf_h_*_set_handler): Rewrite to use
+	CPU or GET_H_FOO/SET_H_FOO access macros as appropriate.
+	* sim-if.c (sim_open): Model probing code moved to sim-model.c.
+
+Fri Dec 18 17:09:34 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30.c (fr30bf_store_register): Call a_fr30_h_dr_set for
+	dedicated registers.
+
+Thu Dec 17 17:17:48 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* sem-switch.c,sem.c: Regenerate.
+
+Tue Dec 15 17:39:59 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (setup_int): Correct calls to SETMEMSI.
+	(fr30_int): Must calculate new pc after saving old one.
+	* fr30.c (fr30bf_h_sbit_get): New function.
+	(fr30bf_h_sbit_set): New function.
+	(fr30bf_h_ccr_set): Use fr30bf_h_sbit_set and move stack switching
+	logic to that function.
+	* cpu.[ch],decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+1998-12-14  Doug Evans  <devans@casey.cygnus.com>
+
+	* configure.in: --enable-cgen-maint moved to common/aclocal.m4.
+	* configure: Regenerate.
+
+	* sem-switch.c,sem.c: Regenerate.
+
+	* traps.c (setup_int): Use enums for register numbers.
+	(fr30_int): Ditto.
+
+1998-12-14  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.[ch],model.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Dec 10 18:43:13 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.[ch],cpu.[ch],decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+	* fr30.c (fr30bf_h_scr_get): Implement as separate bits.
+	(fr30bf_h_scr_set): Implement as separate bits.
+
+Wed Dec  9 13:25:37 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
+
+Tue Dec  8 13:15:23 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+Mon Dec  7 14:35:23 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (fr30_inte): New function.
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+1998-12-05  Doug Evans  <devans@casey.cygnus.com>
+
+	* cpu.h,cpuall.h,decode.c,sem-switch.c,sem.c: Regenerate.
+	* mloop.in (extract): Make static inline.  Rewrite.
+	(execute): Check ARGBUF_PROFILE_P before profiling.
+	Update calls to TRACE_INSN_INIT,TRACE_INSN_FINI.
+
+Fri Dec  4 16:18:25 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* sem.c,sem-switch.c: Regenerate.
+	* cpu.h,decode.c: Regenerate.
+
+Fri Dec  4 17:09:27 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+
+Fri Dec  4 00:22:43 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Dec  3 17:33:16 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30.c (fr30bf_h_ccr_get): New function.
+	(fr30bf_h_ccr_set): New function.
+	(fr30bf_h_ps_get): Use ccr access function.
+	(fr30bf_h_ps_set): Use ccr access function.
+	(fr30bf_h_scr_get): New function.
+	(fr30bf_h_scr_set): New function.
+	(fr30bf_h_ilm_get): New function.
+	(fr30bf_h_ilm_set): New function
+	(fr30bf_h_ps_get): Implement src and ilm.
+	(fr30bf_h_ps_set): Implement src and ilm.
+
+	* arch.c,arch.h,cpu.h,decode.c,decode.h,model.c,
+	sem-switch.c,sem.c: Regenerate.
+
+Thu Dec  3 00:15:11 1998  Doug Evans  <devans@canuck.cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerate.
+
+1998-11-30  Doug Evans  <devans@casey.cygnus.com>
+
+	* mloop.in (extract-pbb): Add delay slot support.
+	* cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Nov 26 11:28:30 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem.c,sem-switch.c: Regenerated.
+
+Mon Nov 23 18:30:36 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h,decode.c,model.c,sem-switch.c,sem.c: Regenerated.
+
+1998-11-20  Doug Evans  <devans@tobor.to.cygnus.com>
+
+	* fr30-sim.h (*-REGNUM): Sync up with gdb.
+	* fr30.c (decode_gdb_dr_regnum): New function.
+	(fr30bf_fetch_register): Implement.
+	(fr30bf_store_register): Ditto.
+	(fr30bf_h_ps_get,fr30bf_h_ps_set): Ditto.
+	(fr30bf_h_dr_get,fr30bf_h_dr_set): New functions.
+	* sem-switch.c,sem.c: Rebuild.
+	* traps.c (setup_int): New function
+	(fr30_int): Handle all int insn processing here.
+	Don't save ps,pc if breakpoint trap.
+	* cpu.c,cpu.h,decode.c,sem-switch.c,sem.c: Regenerate.
+
+Thu Nov 19 16:05:09 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* traps.c (fr30_int): Correct register usage.
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+Wed Nov 18 21:39:37 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* fr30-sim.h (TRAP_SYSCALL, TRAP_BREAKPOINT): Redefine for fr30.
+	* fr30.c (fr30bf_h_ps_get): New function.
+	(fr30bf_h_ps_set): New function.
+	* mloop.in: Set up fast-pbb model for fr30.
+	* traps.c (fr30_int): New function.
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+1998-11-18  Doug Evans  <devans@casey.cygnus.com>
+
+	* Makefile.in (FR30_OBJS): Delete extract.o.
+	(FR30BF_INCLUDE_DEPS): Add cgen-engine.h.
+	(extract.o): Delete rule for.
+	* mloop.in: Rewrite.
+	* cpu.c,cpu.h,decode.c,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
+
+Wed Nov 18 11:31:21 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+Mon Nov 16 19:23:44 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* extract.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+
+Thu Nov 12 19:27:50 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* extract.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+	* fr30.c: Get rid of unused functions.
+
+Mon Nov  9 18:25:47 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* arch.c: Regenerated.
+	* arch.h: Regenerated.
+	* cpu.c: Regenerated.
+	* cpu.h: Regenerated.
+	* decode.c: Regenerated.
+	* decode.h: Regenerated.
+	* extract.c: Regenerated.
+	* model.c: Regenerated.
+	* sem-switch.c: Regenerated.
+	* sem.c: Regenerated.
+	* fr30.c: Get rid of m32r stuff. Flesh out fr30 stuff.
+
+Thu Nov  5 15:26:22 1998  Dave Brolley  <brolley@cygnus.com>
+
+	* cpu.h: Regenerated.
+
+Tue Oct 27 15:39:48 1996  Dave Brolley  <brolley@cygnus.com>
+
+	* Directory created.

sim/fr30/Makefile.in

@@ -0,0 +1,90 @@
+# Makefile template for Configure for the fr30 simulator
+# Copyright (C) 1998 Free Software Foundation, Inc.
+# Contributed by Cygnus Support.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+## COMMON_PRE_CONFIG_FRAG
+
+FR30_OBJS = fr30.o cpu.o decode.o sem.o model.o mloop.o
+
+CONFIG_DEVICES = dv-sockser.o
+CONFIG_DEVICES =
+
+SIM_OBJS = \
+	$(SIM_NEW_COMMON_OBJS) \
+	sim-cpu.o \
+	sim-hload.o \
+	sim-hrw.o \
+	sim-model.o \
+	sim-reg.o \
+	cgen-utils.o cgen-trace.o cgen-scache.o \
+	cgen-run.o sim-reason.o sim-engine.o sim-stop.o \
+	sim-if.o arch.o \
+	$(FR30_OBJS) \
+	traps.o devices.o \
+	$(CONFIG_DEVICES)
+
+# Extra headers included by sim-main.h.
+SIM_EXTRA_DEPS = \
+	$(CGEN_INCLUDE_DEPS) \
+	arch.h cpuall.h fr30-sim.h $(srcdir)/../../opcodes/fr30-desc.h
+
+SIM_EXTRA_CFLAGS =
+
+SIM_RUN_OBJS = nrun.o
+SIM_EXTRA_CLEAN = fr30-clean
+
+# This selects the fr30 newlib/libgloss syscall definitions.
+NL_TARGET = -DNL_TARGET_fr30
+
+## COMMON_POST_CONFIG_FRAG
+
+arch = fr30
+
+sim-if.o: sim-if.c $(SIM_MAIN_DEPS) $(srcdir)/../common/sim-core.h
+
+arch.o: arch.c $(SIM_MAIN_DEPS)
+
+devices.o: devices.c $(SIM_MAIN_DEPS)
+
+# FR30 objs
+
+FR30BF_INCLUDE_DEPS = \
+	$(CGEN_MAIN_CPU_DEPS) \
+	cpu.h decode.h eng.h
+
+fr30.o: fr30.c $(FR30BF_INCLUDE_DEPS)
+
+# FIXME: Use of `mono' is wip.
+mloop.c eng.h: stamp-mloop
+stamp-mloop: $(srcdir)/../common/genmloop.sh mloop.in Makefile
+	$(SHELL) $(srccom)/genmloop.sh \
+		-mono -fast -pbb -switch sem-switch.c \
+		-cpu fr30bf -infile $(srcdir)/mloop.in
+	$(SHELL) $(srcroot)/move-if-change eng.hin eng.h
+	$(SHELL) $(srcroot)/move-if-change mloop.cin mloop.c
+	touch stamp-mloop
+mloop.o: mloop.c sem-switch.c $(FR30BF_INCLUDE_DEPS)
+
+cpu.o: cpu.c $(FR30BF_INCLUDE_DEPS)
+decode.o: decode.c $(FR30BF_INCLUDE_DEPS)
+sem.o: sem.c $(FR30BF_INCLUDE_DEPS)
+model.o: model.c $(FR30BF_INCLUDE_DEPS)
+
+fr30-clean:
+	rm -f mloop.c eng.h stamp-mloop
+	rm -f tmp-*
+

sim/fr30/README

@@ -0,0 +1,14 @@
+This is the fr30 simulator directory.
+
+It is still work-in-progress.  The current sources are reasonably
+well tested and lots of features are in.  However, there's lots
+more yet to come.
+
+There are lots of machine generated files in the source directory!
+They are only generated if you configure with --enable-cgen-maint,
+similar in behaviour to Makefile.in, configure under automake/autoconf.
+
+For details on the generator, see ../../cgen.
+
+devo/cgen isn't part of the comp-tools module yet.
+You'll need to check it out manually (also akin to automake/autoconf).

sim/fr30/TODO

@@ -0,0 +1,14 @@
+m32r-inherited stuff?
+----------------------
+- header file dependencies revisit
+- hooks cleanup
+- testsuites
+- FIXME's
+
+
+m32r stuff?
+----------------------
+- memory accesses still test if profiling is on even in fast mode
+- have semantic code use G/SET_H_FOO if not default [incl fun-access]
+- have G/SET_H_FOO macros call function if fun-access
+- --> can always use G/S_H_FOO macros

sim/fr30/arch.c

@@ -0,0 +1,695 @@
+/* Simulator support for fr30.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_FR30BF
+  & fr30_mach,
+#endif
+  0
+};
+
+/* Get the value of h-pc.  */
+
+USI
+a_fr30_h_pc_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_pc_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-pc.  */
+
+void
+a_fr30_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_pc_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-gr.  */
+
+SI
+a_fr30_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_gr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-gr.  */
+
+void
+a_fr30_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_gr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-cr.  */
+
+SI
+a_fr30_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_cr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-cr.  */
+
+void
+a_fr30_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_cr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-dr.  */
+
+SI
+a_fr30_h_dr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_dr_get (current_cpu, regno);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-dr.  */
+
+void
+a_fr30_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_dr_set (current_cpu, regno, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ps.  */
+
+USI
+a_fr30_h_ps_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ps_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ps.  */
+
+void
+a_fr30_h_ps_set (SIM_CPU *current_cpu, USI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ps_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-r13.  */
+
+SI
+a_fr30_h_r13_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_r13_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-r13.  */
+
+void
+a_fr30_h_r13_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_r13_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-r14.  */
+
+SI
+a_fr30_h_r14_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_r14_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-r14.  */
+
+void
+a_fr30_h_r14_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_r14_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-r15.  */
+
+SI
+a_fr30_h_r15_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_r15_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-r15.  */
+
+void
+a_fr30_h_r15_set (SIM_CPU *current_cpu, SI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_r15_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-nbit.  */
+
+BI
+a_fr30_h_nbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_nbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-nbit.  */
+
+void
+a_fr30_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_nbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-zbit.  */
+
+BI
+a_fr30_h_zbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_zbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-zbit.  */
+
+void
+a_fr30_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_zbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-vbit.  */
+
+BI
+a_fr30_h_vbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_vbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-vbit.  */
+
+void
+a_fr30_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_vbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-cbit.  */
+
+BI
+a_fr30_h_cbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_cbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-cbit.  */
+
+void
+a_fr30_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_cbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ibit.  */
+
+BI
+a_fr30_h_ibit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ibit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ibit.  */
+
+void
+a_fr30_h_ibit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ibit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-sbit.  */
+
+BI
+a_fr30_h_sbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_sbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-sbit.  */
+
+void
+a_fr30_h_sbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_sbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-tbit.  */
+
+BI
+a_fr30_h_tbit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_tbit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-tbit.  */
+
+void
+a_fr30_h_tbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_tbit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-d0bit.  */
+
+BI
+a_fr30_h_d0bit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_d0bit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-d0bit.  */
+
+void
+a_fr30_h_d0bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_d0bit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-d1bit.  */
+
+BI
+a_fr30_h_d1bit_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_d1bit_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-d1bit.  */
+
+void
+a_fr30_h_d1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_d1bit_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ccr.  */
+
+UQI
+a_fr30_h_ccr_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ccr_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ccr.  */
+
+void
+a_fr30_h_ccr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ccr_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-scr.  */
+
+UQI
+a_fr30_h_scr_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_scr_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-scr.  */
+
+void
+a_fr30_h_scr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_scr_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Get the value of h-ilm.  */
+
+UQI
+a_fr30_h_ilm_get (SIM_CPU *current_cpu)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      return fr30bf_h_ilm_get (current_cpu);
+#endif
+    default :
+      abort ();
+    }
+}
+
+/* Set a value for h-ilm.  */
+
+void
+a_fr30_h_ilm_set (SIM_CPU *current_cpu, UQI newval)
+{
+  switch (STATE_ARCHITECTURE (CPU_STATE (current_cpu))->mach)
+    {
+#ifdef HAVE_CPU_FR30BF
+    case bfd_mach_fr30 : 
+      fr30bf_h_ilm_set (current_cpu, newval);
+      break;
+#endif
+    default :
+      abort ();
+    }
+}
+

sim/fr30/arch.h

@@ -0,0 +1,87 @@
+/* Simulator header for fr30.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FR30_ARCH_H
+#define FR30_ARCH_H
+
+#define TARGET_BIG_ENDIAN 1
+
+/* Cover fns for register access.  */
+USI a_fr30_h_pc_get (SIM_CPU *);
+void a_fr30_h_pc_set (SIM_CPU *, USI);
+SI a_fr30_h_gr_get (SIM_CPU *, UINT);
+void a_fr30_h_gr_set (SIM_CPU *, UINT, SI);
+SI a_fr30_h_cr_get (SIM_CPU *, UINT);
+void a_fr30_h_cr_set (SIM_CPU *, UINT, SI);
+SI a_fr30_h_dr_get (SIM_CPU *, UINT);
+void a_fr30_h_dr_set (SIM_CPU *, UINT, SI);
+USI a_fr30_h_ps_get (SIM_CPU *);
+void a_fr30_h_ps_set (SIM_CPU *, USI);
+SI a_fr30_h_r13_get (SIM_CPU *);
+void a_fr30_h_r13_set (SIM_CPU *, SI);
+SI a_fr30_h_r14_get (SIM_CPU *);
+void a_fr30_h_r14_set (SIM_CPU *, SI);
+SI a_fr30_h_r15_get (SIM_CPU *);
+void a_fr30_h_r15_set (SIM_CPU *, SI);
+BI a_fr30_h_nbit_get (SIM_CPU *);
+void a_fr30_h_nbit_set (SIM_CPU *, BI);
+BI a_fr30_h_zbit_get (SIM_CPU *);
+void a_fr30_h_zbit_set (SIM_CPU *, BI);
+BI a_fr30_h_vbit_get (SIM_CPU *);
+void a_fr30_h_vbit_set (SIM_CPU *, BI);
+BI a_fr30_h_cbit_get (SIM_CPU *);
+void a_fr30_h_cbit_set (SIM_CPU *, BI);
+BI a_fr30_h_ibit_get (SIM_CPU *);
+void a_fr30_h_ibit_set (SIM_CPU *, BI);
+BI a_fr30_h_sbit_get (SIM_CPU *);
+void a_fr30_h_sbit_set (SIM_CPU *, BI);
+BI a_fr30_h_tbit_get (SIM_CPU *);
+void a_fr30_h_tbit_set (SIM_CPU *, BI);
+BI a_fr30_h_d0bit_get (SIM_CPU *);
+void a_fr30_h_d0bit_set (SIM_CPU *, BI);
+BI a_fr30_h_d1bit_get (SIM_CPU *);
+void a_fr30_h_d1bit_set (SIM_CPU *, BI);
+UQI a_fr30_h_ccr_get (SIM_CPU *);
+void a_fr30_h_ccr_set (SIM_CPU *, UQI);
+UQI a_fr30_h_scr_get (SIM_CPU *);
+void a_fr30_h_scr_set (SIM_CPU *, UQI);
+UQI a_fr30_h_ilm_get (SIM_CPU *);
+void a_fr30_h_ilm_set (SIM_CPU *, UQI);
+
+/* Enum declaration for model types.  */
+typedef enum model_type {
+  MODEL_FR30_1, MODEL_MAX
+} MODEL_TYPE;
+
+#define MAX_MODELS ((int) MODEL_MAX)
+
+/* Enum declaration for unit types.  */
+typedef enum unit_type {
+  UNIT_NONE, UNIT_FR30_1_U_STM, UNIT_FR30_1_U_LDM, UNIT_FR30_1_U_STORE
+ , UNIT_FR30_1_U_LOAD, UNIT_FR30_1_U_CTI, UNIT_FR30_1_U_EXEC, UNIT_MAX
+} UNIT_TYPE;
+
+#define MAX_UNITS (3)
+
+#endif /* FR30_ARCH_H */

sim/fr30/config.in

@@ -0,0 +1,162 @@
+/* config.in.  Generated automatically from configure.in by autoheader.  */
+
+/* Define if using alloca.c.  */
+#undef C_ALLOCA
+
+/* Define to empty if the keyword does not work.  */
+#undef const
+
+/* Define to one of _getb67, GETB67, getb67 for Cray-2 and Cray-YMP systems.
+   This function is required for alloca.c support on those systems.  */
+#undef CRAY_STACKSEG_END
+
+/* Define if you have alloca, as a function or macro.  */
+#undef HAVE_ALLOCA
+
+/* Define if you have <alloca.h> and it should be used (not on Ultrix).  */
+#undef HAVE_ALLOCA_H
+
+/* Define if you have a working `mmap' system call.  */
+#undef HAVE_MMAP
+
+/* Define as __inline if that's what the C compiler calls it.  */
+#undef inline
+
+/* Define to `long' if <sys/types.h> doesn't define.  */
+#undef off_t
+
+/* Define if you need to in order for stat and other things to work.  */
+#undef _POSIX_SOURCE
+
+/* Define as the return type of signal handlers (int or void).  */
+#undef RETSIGTYPE
+
+/* Define to `unsigned' if <sys/types.h> doesn't define.  */
+#undef size_t
+
+/* If using the C implementation of alloca, define if you know the
+   direction of stack growth for your system; otherwise it will be
+   automatically deduced at run-time.
+ STACK_DIRECTION > 0 => grows toward higher addresses
+ STACK_DIRECTION < 0 => grows toward lower addresses
+ STACK_DIRECTION = 0 => direction of growth unknown
+ */
+#undef STACK_DIRECTION
+
+/* Define if you have the ANSI C header files.  */
+#undef STDC_HEADERS
+
+/* Define if your processor stores words with the most significant
+   byte first (like Motorola and SPARC, unlike Intel and VAX).  */
+#undef WORDS_BIGENDIAN
+
+/* Define to 1 if NLS is requested.  */
+#undef ENABLE_NLS
+
+/* Define as 1 if you have gettext and don't want to use GNU gettext.  */
+#undef HAVE_GETTEXT
+
+/* Define as 1 if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if your locale.h file contains LC_MESSAGES.  */
+#undef HAVE_LC_MESSAGES
+
+/* Define if you have the __argz_count function.  */
+#undef HAVE___ARGZ_COUNT
+
+/* Define if you have the __argz_next function.  */
+#undef HAVE___ARGZ_NEXT
+
+/* Define if you have the __argz_stringify function.  */
+#undef HAVE___ARGZ_STRINGIFY
+
+/* Define if you have the __setfpucw function.  */
+#undef HAVE___SETFPUCW
+
+/* Define if you have the dcgettext function.  */
+#undef HAVE_DCGETTEXT
+
+/* Define if you have the getcwd function.  */
+#undef HAVE_GETCWD
+
+/* Define if you have the getpagesize function.  */
+#undef HAVE_GETPAGESIZE
+
+/* Define if you have the getrusage function.  */
+#undef HAVE_GETRUSAGE
+
+/* Define if you have the munmap function.  */
+#undef HAVE_MUNMAP
+
+/* Define if you have the putenv function.  */
+#undef HAVE_PUTENV
+
+/* Define if you have the setenv function.  */
+#undef HAVE_SETENV
+
+/* Define if you have the setlocale function.  */
+#undef HAVE_SETLOCALE
+
+/* Define if you have the sigaction function.  */
+#undef HAVE_SIGACTION
+
+/* Define if you have the stpcpy function.  */
+#undef HAVE_STPCPY
+
+/* Define if you have the strcasecmp function.  */
+#undef HAVE_STRCASECMP
+
+/* Define if you have the strchr function.  */
+#undef HAVE_STRCHR
+
+/* Define if you have the time function.  */
+#undef HAVE_TIME
+
+/* Define if you have the <argz.h> header file.  */
+#undef HAVE_ARGZ_H
+
+/* Define if you have the <fcntl.h> header file.  */
+#undef HAVE_FCNTL_H
+
+/* Define if you have the <fpu_control.h> header file.  */
+#undef HAVE_FPU_CONTROL_H
+
+/* Define if you have the <limits.h> header file.  */
+#undef HAVE_LIMITS_H
+
+/* Define if you have the <locale.h> header file.  */
+#undef HAVE_LOCALE_H
+
+/* Define if you have the <malloc.h> header file.  */
+#undef HAVE_MALLOC_H
+
+/* Define if you have the <nl_types.h> header file.  */
+#undef HAVE_NL_TYPES_H
+
+/* Define if you have the <stdlib.h> header file.  */
+#undef HAVE_STDLIB_H
+
+/* Define if you have the <string.h> header file.  */
+#undef HAVE_STRING_H
+
+/* Define if you have the <strings.h> header file.  */
+#undef HAVE_STRINGS_H
+
+/* Define if you have the <sys/param.h> header file.  */
+#undef HAVE_SYS_PARAM_H
+
+/* Define if you have the <sys/resource.h> header file.  */
+#undef HAVE_SYS_RESOURCE_H
+
+/* Define if you have the <sys/time.h> header file.  */
+#undef HAVE_SYS_TIME_H
+
+/* Define if you have the <time.h> header file.  */
+#undef HAVE_TIME_H
+
+/* Define if you have the <unistd.h> header file.  */
+#undef HAVE_UNISTD_H
+
+/* Define if you have the <values.h> header file.  */
+#undef HAVE_VALUES_H

sim/fr30/configure.in

@@ -0,0 +1,16 @@
+dnl Process this file with autoconf to produce a configure script.
+sinclude(../common/aclocal.m4)
+AC_PREREQ(2.5)dnl
+AC_INIT(Makefile.in)
+
+SIM_AC_COMMON
+
+SIM_AC_OPTION_ENDIAN(BIG_ENDIAN)
+SIM_AC_OPTION_ALIGNMENT(NONSTRICT_ALIGNMENT)
+SIM_AC_OPTION_HOSTENDIAN
+SIM_AC_OPTION_SCACHE(16384)
+SIM_AC_OPTION_DEFAULT_MODEL(fr30-1)
+SIM_AC_OPTION_ENVIRONMENT
+SIM_AC_OPTION_CGEN_MAINT
+
+SIM_AC_OUTPUT

sim/fr30/cpu.c

@@ -0,0 +1,356 @@
+/* Misc. support for CPU family fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#define WANT_CPU fr30bf
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+
+/* Get the value of h-pc.  */
+
+USI
+fr30bf_h_pc_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_pc);
+}
+
+/* Set a value for h-pc.  */
+
+void
+fr30bf_h_pc_set (SIM_CPU *current_cpu, USI newval)
+{
+  CPU (h_pc) = newval;
+}
+
+/* Get the value of h-gr.  */
+
+SI
+fr30bf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_gr[regno]);
+}
+
+/* Set a value for h-gr.  */
+
+void
+fr30bf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_gr[regno]) = newval;
+}
+
+/* Get the value of h-cr.  */
+
+SI
+fr30bf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return CPU (h_cr[regno]);
+}
+
+/* Set a value for h-cr.  */
+
+void
+fr30bf_h_cr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  CPU (h_cr[regno]) = newval;
+}
+
+/* Get the value of h-dr.  */
+
+SI
+fr30bf_h_dr_get (SIM_CPU *current_cpu, UINT regno)
+{
+  return GET_H_DR (regno);
+}
+
+/* Set a value for h-dr.  */
+
+void
+fr30bf_h_dr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
+{
+  SET_H_DR (regno, newval);
+}
+
+/* Get the value of h-ps.  */
+
+USI
+fr30bf_h_ps_get (SIM_CPU *current_cpu)
+{
+  return GET_H_PS ();
+}
+
+/* Set a value for h-ps.  */
+
+void
+fr30bf_h_ps_set (SIM_CPU *current_cpu, USI newval)
+{
+  SET_H_PS (newval);
+}
+
+/* Get the value of h-r13.  */
+
+SI
+fr30bf_h_r13_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_r13);
+}
+
+/* Set a value for h-r13.  */
+
+void
+fr30bf_h_r13_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_r13) = newval;
+}
+
+/* Get the value of h-r14.  */
+
+SI
+fr30bf_h_r14_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_r14);
+}
+
+/* Set a value for h-r14.  */
+
+void
+fr30bf_h_r14_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_r14) = newval;
+}
+
+/* Get the value of h-r15.  */
+
+SI
+fr30bf_h_r15_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_r15);
+}
+
+/* Set a value for h-r15.  */
+
+void
+fr30bf_h_r15_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_r15) = newval;
+}
+
+/* Get the value of h-nbit.  */
+
+BI
+fr30bf_h_nbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_nbit);
+}
+
+/* Set a value for h-nbit.  */
+
+void
+fr30bf_h_nbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_nbit) = newval;
+}
+
+/* Get the value of h-zbit.  */
+
+BI
+fr30bf_h_zbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_zbit);
+}
+
+/* Set a value for h-zbit.  */
+
+void
+fr30bf_h_zbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_zbit) = newval;
+}
+
+/* Get the value of h-vbit.  */
+
+BI
+fr30bf_h_vbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_vbit);
+}
+
+/* Set a value for h-vbit.  */
+
+void
+fr30bf_h_vbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_vbit) = newval;
+}
+
+/* Get the value of h-cbit.  */
+
+BI
+fr30bf_h_cbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_cbit);
+}
+
+/* Set a value for h-cbit.  */
+
+void
+fr30bf_h_cbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_cbit) = newval;
+}
+
+/* Get the value of h-ibit.  */
+
+BI
+fr30bf_h_ibit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_ibit);
+}
+
+/* Set a value for h-ibit.  */
+
+void
+fr30bf_h_ibit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_ibit) = newval;
+}
+
+/* Get the value of h-sbit.  */
+
+BI
+fr30bf_h_sbit_get (SIM_CPU *current_cpu)
+{
+  return GET_H_SBIT ();
+}
+
+/* Set a value for h-sbit.  */
+
+void
+fr30bf_h_sbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  SET_H_SBIT (newval);
+}
+
+/* Get the value of h-tbit.  */
+
+BI
+fr30bf_h_tbit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_tbit);
+}
+
+/* Set a value for h-tbit.  */
+
+void
+fr30bf_h_tbit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_tbit) = newval;
+}
+
+/* Get the value of h-d0bit.  */
+
+BI
+fr30bf_h_d0bit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_d0bit);
+}
+
+/* Set a value for h-d0bit.  */
+
+void
+fr30bf_h_d0bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_d0bit) = newval;
+}
+
+/* Get the value of h-d1bit.  */
+
+BI
+fr30bf_h_d1bit_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_d1bit);
+}
+
+/* Set a value for h-d1bit.  */
+
+void
+fr30bf_h_d1bit_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_d1bit) = newval;
+}
+
+/* Get the value of h-ccr.  */
+
+UQI
+fr30bf_h_ccr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_CCR ();
+}
+
+/* Set a value for h-ccr.  */
+
+void
+fr30bf_h_ccr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_CCR (newval);
+}
+
+/* Get the value of h-scr.  */
+
+UQI
+fr30bf_h_scr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_SCR ();
+}
+
+/* Set a value for h-scr.  */
+
+void
+fr30bf_h_scr_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_SCR (newval);
+}
+
+/* Get the value of h-ilm.  */
+
+UQI
+fr30bf_h_ilm_get (SIM_CPU *current_cpu)
+{
+  return GET_H_ILM ();
+}
+
+/* Set a value for h-ilm.  */
+
+void
+fr30bf_h_ilm_set (SIM_CPU *current_cpu, UQI newval)
+{
+  SET_H_ILM (newval);
+}
+
+/* Record trace results for INSN.  */
+
+void
+fr30bf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
+			    int *indices, TRACE_RECORD *tr)
+{
+}

sim/fr30/cpuall.h

@@ -0,0 +1,63 @@
+/* Simulator CPU header for fr30.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FR30_CPUALL_H
+#define FR30_CPUALL_H
+
+/* Include files for each cpu family.  */
+
+#ifdef WANT_CPU_FR30BF
+#include "eng.h"
+#include "cgen-engine.h"
+#include "cpu.h"
+#include "decode.h"
+#endif
+
+extern const MACH fr30_mach;
+
+#ifndef WANT_CPU
+/* The ARGBUF struct.  */
+struct argbuf {
+  /* These are the baseclass definitions.  */
+  IADDR addr;
+  const IDESC *idesc;
+  char trace_p;
+  char profile_p;
+  /* cpu specific data follows */
+};
+#endif
+
+#ifndef WANT_CPU
+/* A cached insn.
+
+   ??? SCACHE used to contain more than just argbuf.  We could delete the
+   type entirely and always just use ARGBUF, but for future concerns and as
+   a level of abstraction it is left in.  */
+
+struct scache {
+  struct argbuf argbuf;
+};
+#endif
+
+#endif /* FR30_CPUALL_H */

sim/fr30/decode.h

@@ -0,0 +1,289 @@
+/* Decode header for fr30bf.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+
+#ifndef FR30BF_DECODE_H
+#define FR30BF_DECODE_H
+
+extern const IDESC *fr30bf_decode (SIM_CPU *, IADDR,
+                                  CGEN_INSN_INT,
+                                  ARGBUF *);
+extern void fr30bf_init_idesc_table (SIM_CPU *);
+
+/* Enum declaration for instructions in cpu family fr30bf.  */
+typedef enum fr30bf_insn_type {
+  FR30BF_INSN_X_INVALID, FR30BF_INSN_X_AFTER, FR30BF_INSN_X_BEFORE, FR30BF_INSN_X_CTI_CHAIN
+ , FR30BF_INSN_X_CHAIN, FR30BF_INSN_X_BEGIN, FR30BF_INSN_ADD, FR30BF_INSN_ADDI
+ , FR30BF_INSN_ADD2, FR30BF_INSN_ADDC, FR30BF_INSN_ADDN, FR30BF_INSN_ADDNI
+ , FR30BF_INSN_ADDN2, FR30BF_INSN_SUB, FR30BF_INSN_SUBC, FR30BF_INSN_SUBN
+ , FR30BF_INSN_CMP, FR30BF_INSN_CMPI, FR30BF_INSN_CMP2, FR30BF_INSN_AND
+ , FR30BF_INSN_OR, FR30BF_INSN_EOR, FR30BF_INSN_ANDM, FR30BF_INSN_ANDH
+ , FR30BF_INSN_ANDB, FR30BF_INSN_ORM, FR30BF_INSN_ORH, FR30BF_INSN_ORB
+ , FR30BF_INSN_EORM, FR30BF_INSN_EORH, FR30BF_INSN_EORB, FR30BF_INSN_BANDL
+ , FR30BF_INSN_BORL, FR30BF_INSN_BEORL, FR30BF_INSN_BANDH, FR30BF_INSN_BORH
+ , FR30BF_INSN_BEORH, FR30BF_INSN_BTSTL, FR30BF_INSN_BTSTH, FR30BF_INSN_MUL
+ , FR30BF_INSN_MULU, FR30BF_INSN_MULH, FR30BF_INSN_MULUH, FR30BF_INSN_DIV0S
+ , FR30BF_INSN_DIV0U, FR30BF_INSN_DIV1, FR30BF_INSN_DIV2, FR30BF_INSN_DIV3
+ , FR30BF_INSN_DIV4S, FR30BF_INSN_LSL, FR30BF_INSN_LSLI, FR30BF_INSN_LSL2
+ , FR30BF_INSN_LSR, FR30BF_INSN_LSRI, FR30BF_INSN_LSR2, FR30BF_INSN_ASR
+ , FR30BF_INSN_ASRI, FR30BF_INSN_ASR2, FR30BF_INSN_LDI8, FR30BF_INSN_LDI20
+ , FR30BF_INSN_LDI32, FR30BF_INSN_LD, FR30BF_INSN_LDUH, FR30BF_INSN_LDUB
+ , FR30BF_INSN_LDR13, FR30BF_INSN_LDR13UH, FR30BF_INSN_LDR13UB, FR30BF_INSN_LDR14
+ , FR30BF_INSN_LDR14UH, FR30BF_INSN_LDR14UB, FR30BF_INSN_LDR15, FR30BF_INSN_LDR15GR
+ , FR30BF_INSN_LDR15DR, FR30BF_INSN_LDR15PS, FR30BF_INSN_ST, FR30BF_INSN_STH
+ , FR30BF_INSN_STB, FR30BF_INSN_STR13, FR30BF_INSN_STR13H, FR30BF_INSN_STR13B
+ , FR30BF_INSN_STR14, FR30BF_INSN_STR14H, FR30BF_INSN_STR14B, FR30BF_INSN_STR15
+ , FR30BF_INSN_STR15GR, FR30BF_INSN_STR15DR, FR30BF_INSN_STR15PS, FR30BF_INSN_MOV
+ , FR30BF_INSN_MOVDR, FR30BF_INSN_MOVPS, FR30BF_INSN_MOV2DR, FR30BF_INSN_MOV2PS
+ , FR30BF_INSN_JMP, FR30BF_INSN_JMPD, FR30BF_INSN_CALLR, FR30BF_INSN_CALLRD
+ , FR30BF_INSN_CALL, FR30BF_INSN_CALLD, FR30BF_INSN_RET, FR30BF_INSN_RET_D
+ , FR30BF_INSN_INT, FR30BF_INSN_INTE, FR30BF_INSN_RETI, FR30BF_INSN_BRAD
+ , FR30BF_INSN_BRA, FR30BF_INSN_BNOD, FR30BF_INSN_BNO, FR30BF_INSN_BEQD
+ , FR30BF_INSN_BEQ, FR30BF_INSN_BNED, FR30BF_INSN_BNE, FR30BF_INSN_BCD
+ , FR30BF_INSN_BC, FR30BF_INSN_BNCD, FR30BF_INSN_BNC, FR30BF_INSN_BND
+ , FR30BF_INSN_BN, FR30BF_INSN_BPD, FR30BF_INSN_BP, FR30BF_INSN_BVD
+ , FR30BF_INSN_BV, FR30BF_INSN_BNVD, FR30BF_INSN_BNV, FR30BF_INSN_BLTD
+ , FR30BF_INSN_BLT, FR30BF_INSN_BGED, FR30BF_INSN_BGE, FR30BF_INSN_BLED
+ , FR30BF_INSN_BLE, FR30BF_INSN_BGTD, FR30BF_INSN_BGT, FR30BF_INSN_BLSD
+ , FR30BF_INSN_BLS, FR30BF_INSN_BHID, FR30BF_INSN_BHI, FR30BF_INSN_DMOVR13
+ , FR30BF_INSN_DMOVR13H, FR30BF_INSN_DMOVR13B, FR30BF_INSN_DMOVR13PI, FR30BF_INSN_DMOVR13PIH
+ , FR30BF_INSN_DMOVR13PIB, FR30BF_INSN_DMOVR15PI, FR30BF_INSN_DMOV2R13, FR30BF_INSN_DMOV2R13H
+ , FR30BF_INSN_DMOV2R13B, FR30BF_INSN_DMOV2R13PI, FR30BF_INSN_DMOV2R13PIH, FR30BF_INSN_DMOV2R13PIB
+ , FR30BF_INSN_DMOV2R15PD, FR30BF_INSN_LDRES, FR30BF_INSN_STRES, FR30BF_INSN_COPOP
+ , FR30BF_INSN_COPLD, FR30BF_INSN_COPST, FR30BF_INSN_COPSV, FR30BF_INSN_NOP
+ , FR30BF_INSN_ANDCCR, FR30BF_INSN_ORCCR, FR30BF_INSN_STILM, FR30BF_INSN_ADDSP
+ , FR30BF_INSN_EXTSB, FR30BF_INSN_EXTUB, FR30BF_INSN_EXTSH, FR30BF_INSN_EXTUH
+ , FR30BF_INSN_LDM0, FR30BF_INSN_LDM1, FR30BF_INSN_STM0, FR30BF_INSN_STM1
+ , FR30BF_INSN_ENTER, FR30BF_INSN_LEAVE, FR30BF_INSN_XCHB, FR30BF_INSN_MAX
+} FR30BF_INSN_TYPE;
+
+#if ! WITH_SEM_SWITCH_FULL
+#define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,fn);
+#else
+#define SEMFULL(fn)
+#endif
+
+#if ! WITH_SEM_SWITCH_FAST
+#define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (fr30bf,_semf_,fn);
+#else
+#define SEMFAST(fn)
+#endif
+
+#define SEM(fn) SEMFULL (fn) SEMFAST (fn)
+
+/* The function version of the before/after handlers is always needed,
+   so we always want the SEMFULL declaration of them.  */
+extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,x_before);
+extern SEMANTIC_FN CONCAT3 (fr30bf,_sem_,x_after);
+
+SEM (x_invalid)
+SEM (x_after)
+SEM (x_before)
+SEM (x_cti_chain)
+SEM (x_chain)
+SEM (x_begin)
+SEM (add)
+SEM (addi)
+SEM (add2)
+SEM (addc)
+SEM (addn)
+SEM (addni)
+SEM (addn2)
+SEM (sub)
+SEM (subc)
+SEM (subn)
+SEM (cmp)
+SEM (cmpi)
+SEM (cmp2)
+SEM (and)
+SEM (or)
+SEM (eor)
+SEM (andm)
+SEM (andh)
+SEM (andb)
+SEM (orm)
+SEM (orh)
+SEM (orb)
+SEM (eorm)
+SEM (eorh)
+SEM (eorb)
+SEM (bandl)
+SEM (borl)
+SEM (beorl)
+SEM (bandh)
+SEM (borh)
+SEM (beorh)
+SEM (btstl)
+SEM (btsth)
+SEM (mul)
+SEM (mulu)
+SEM (mulh)
+SEM (muluh)
+SEM (div0s)
+SEM (div0u)
+SEM (div1)
+SEM (div2)
+SEM (div3)
+SEM (div4s)
+SEM (lsl)
+SEM (lsli)
+SEM (lsl2)
+SEM (lsr)
+SEM (lsri)
+SEM (lsr2)
+SEM (asr)
+SEM (asri)
+SEM (asr2)
+SEM (ldi8)
+SEM (ldi20)
+SEM (ldi32)
+SEM (ld)
+SEM (lduh)
+SEM (ldub)
+SEM (ldr13)
+SEM (ldr13uh)
+SEM (ldr13ub)
+SEM (ldr14)
+SEM (ldr14uh)
+SEM (ldr14ub)
+SEM (ldr15)
+SEM (ldr15gr)
+SEM (ldr15dr)
+SEM (ldr15ps)
+SEM (st)
+SEM (sth)
+SEM (stb)
+SEM (str13)
+SEM (str13h)
+SEM (str13b)
+SEM (str14)
+SEM (str14h)
+SEM (str14b)
+SEM (str15)
+SEM (str15gr)
+SEM (str15dr)
+SEM (str15ps)
+SEM (mov)
+SEM (movdr)
+SEM (movps)
+SEM (mov2dr)
+SEM (mov2ps)
+SEM (jmp)
+SEM (jmpd)
+SEM (callr)
+SEM (callrd)
+SEM (call)
+SEM (calld)
+SEM (ret)
+SEM (ret_d)
+SEM (int)
+SEM (inte)
+SEM (reti)
+SEM (brad)
+SEM (bra)
+SEM (bnod)
+SEM (bno)
+SEM (beqd)
+SEM (beq)
+SEM (bned)
+SEM (bne)
+SEM (bcd)
+SEM (bc)
+SEM (bncd)
+SEM (bnc)
+SEM (bnd)
+SEM (bn)
+SEM (bpd)
+SEM (bp)
+SEM (bvd)
+SEM (bv)
+SEM (bnvd)
+SEM (bnv)
+SEM (bltd)
+SEM (blt)
+SEM (bged)
+SEM (bge)
+SEM (bled)
+SEM (ble)
+SEM (bgtd)
+SEM (bgt)
+SEM (blsd)
+SEM (bls)
+SEM (bhid)
+SEM (bhi)
+SEM (dmovr13)
+SEM (dmovr13h)
+SEM (dmovr13b)
+SEM (dmovr13pi)
+SEM (dmovr13pih)
+SEM (dmovr13pib)
+SEM (dmovr15pi)
+SEM (dmov2r13)
+SEM (dmov2r13h)
+SEM (dmov2r13b)
+SEM (dmov2r13pi)
+SEM (dmov2r13pih)
+SEM (dmov2r13pib)
+SEM (dmov2r15pd)
+SEM (ldres)
+SEM (stres)
+SEM (copop)
+SEM (copld)
+SEM (copst)
+SEM (copsv)
+SEM (nop)
+SEM (andccr)
+SEM (orccr)
+SEM (stilm)
+SEM (addsp)
+SEM (extsb)
+SEM (extub)
+SEM (extsh)
+SEM (extuh)
+SEM (ldm0)
+SEM (ldm1)
+SEM (stm0)
+SEM (stm1)
+SEM (enter)
+SEM (leave)
+SEM (xchb)
+
+#undef SEMFULL
+#undef SEMFAST
+#undef SEM
+
+/* Function unit handlers (user written).  */
+
+extern int fr30bf_model_fr30_1_u_stm (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*reglist*/);
+extern int fr30bf_model_fr30_1_u_ldm (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*reglist*/);
+extern int fr30bf_model_fr30_1_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ri*/, INT /*Rj*/);
+extern int fr30bf_model_fr30_1_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Rj*/, INT /*Ri*/);
+extern int fr30bf_model_fr30_1_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ri*/);
+extern int fr30bf_model_fr30_1_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*Ri*/, INT /*Rj*/, INT /*Ri*/);
+
+/* Profiling before/after handlers (user written) */
+
+extern void fr30bf_model_insn_before (SIM_CPU *, int /*first_p*/);
+extern void fr30bf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
+
+#endif /* FR30BF_DECODE_H */

sim/fr30/devices.c

@@ -0,0 +1,99 @@
+/* fr30 device support
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+/* ??? All of this is just to get something going.  wip!  */
+
+#include "sim-main.h"
+
+#ifdef HAVE_DV_SOCKSER
+#include "dv-sockser.h"
+#endif
+
+device fr30_devices;
+
+int
+device_io_read_buffer (device *me, void *source, int space,
+		       address_word addr, unsigned nr_bytes,
+		       SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#ifdef HAVE_DV_SOCKSER
+  if (addr == UART_INCHAR_ADDR)
+    {
+      int c = dv_sockser_read (sd);
+      if (c == -1)
+	return 0;
+      *(char *) source = c;
+      return 1;
+    }
+  if (addr == UART_STATUS_ADDR)
+    {
+      int status = dv_sockser_status (sd);
+      unsigned char *p = source;
+      p[0] = 0;
+      p[1] = (((status & DV_SOCKSER_INPUT_EMPTY)
+#ifdef UART_INPUT_READY0
+	       ? UART_INPUT_READY : 0)
+#else
+	       ? 0 : UART_INPUT_READY)
+#endif
+	      + ((status & DV_SOCKSER_OUTPUT_EMPTY) ? UART_OUTPUT_READY : 0));
+      return 2;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+int
+device_io_write_buffer (device *me, const void *source, int space,
+			address_word addr, unsigned nr_bytes,
+			SIM_CPU *cpu, sim_cia cia)
+{
+  SIM_DESC sd = CPU_STATE (cpu);
+
+#if WITH_SCACHE
+  if (addr == MCCR_ADDR)
+    {
+      if ((*(const char *) source & MCCR_CP) != 0)
+	scache_flush (sd);
+      return nr_bytes;
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) != OPERATING_ENVIRONMENT)
+    return nr_bytes;
+
+#if HAVE_DV_SOCKSER
+  if (addr == UART_OUTCHAR_ADDR)
+    {
+      int rc = dv_sockser_write (sd, *(char *) source);
+      return rc == 1;
+    }
+#endif
+
+  return nr_bytes;
+}
+
+void device_error () {}

sim/fr30/fr30-sim.h

@@ -0,0 +1,108 @@
+/* collection of junk waiting time to sort out
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU Simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#ifndef FR30_SIM_H
+#define FR30_SIM_H
+
+/* gdb register numbers */
+#define PC_REGNUM	16
+#define PS_REGNUM	17
+#define TBR_REGNUM	18
+#define RP_REGNUM	19
+#define SSP_REGNUM	20
+#define USP_REGNUM	21
+#define MDH_REGNUM	22
+#define MDL_REGNUM	23
+
+extern BI fr30bf_h_sbit_get_handler (SIM_CPU *);
+extern void fr30bf_h_sbit_set_handler (SIM_CPU *, BI);
+#define GET_H_SBIT() fr30bf_h_sbit_get_handler (current_cpu)
+#define SET_H_SBIT(val) fr30bf_h_sbit_set_handler (current_cpu, (val))
+
+extern UQI fr30bf_h_ccr_get_handler (SIM_CPU *);
+extern void fr30bf_h_ccr_set_handler (SIM_CPU *, UQI);
+#define GET_H_CCR() fr30bf_h_ccr_get_handler (current_cpu)
+#define SET_H_CCR(val) fr30bf_h_ccr_set_handler (current_cpu, (val))
+
+extern UQI fr30bf_h_scr_get_handler (SIM_CPU *);
+extern void fr30bf_h_scr_set_handler (SIM_CPU *, UQI);
+#define GET_H_SCR() fr30bf_h_scr_get_handler (current_cpu)
+#define SET_H_SCR(val) fr30bf_h_scr_set_handler (current_cpu, (val))
+
+extern UQI fr30bf_h_ilm_get_handler (SIM_CPU *);
+extern void fr30bf_h_ilm_set_handler (SIM_CPU *, UQI);
+#define GET_H_ILM() fr30bf_h_ilm_get_handler (current_cpu)
+#define SET_H_ILM(val) fr30bf_h_ilm_set_handler (current_cpu, (val))
+
+extern USI fr30bf_h_ps_get_handler (SIM_CPU *);
+extern void fr30bf_h_ps_set_handler (SIM_CPU *, USI);
+#define GET_H_PS() fr30bf_h_ps_get_handler (current_cpu)
+#define SET_H_PS(val) fr30bf_h_ps_set_handler (current_cpu, (val))
+
+extern SI fr30bf_h_dr_get_handler (SIM_CPU *, UINT);
+extern void fr30bf_h_dr_set_handler (SIM_CPU *, UINT, SI);
+#define GET_H_DR(regno) fr30bf_h_dr_get_handler (current_cpu, (regno))
+#define SET_H_DR(regno, val) fr30bf_h_dr_set_handler (current_cpu, (regno), (val))
+
+#define GETTWI GETTSI
+#define SETTWI SETTSI
+
+/* Hardware/device support.
+   ??? Will eventually want to move device stuff to config files.  */
+
+/* Special purpose traps.  */
+#define TRAP_SYSCALL	10
+#define TRAP_BREAKPOINT	9
+
+/* Support for the MCCR register (Cache Control Register) is needed in order
+   for overlays to work correctly with the scache: cached instructions need
+   to be flushed when the instruction space is changed at runtime.  */
+
+/* Cache Control Register */
+#define MCCR_ADDR 0xffffffff
+#define MCCR_CP 0x80
+/* not supported */
+#define MCCR_CM0 2
+#define MCCR_CM1 1
+
+/* Serial device addresses.  */
+/* These are the values for the MSA2000 board.
+   ??? Will eventually need to move this to a config file.  */
+#define UART_INCHAR_ADDR	0xff004009
+#define UART_OUTCHAR_ADDR	0xff004007
+#define UART_STATUS_ADDR	0xff004002
+
+#define UART_INPUT_READY	0x4
+#define UART_OUTPUT_READY	0x1
+
+/* Start address and length of all device support.  */
+#define FR30_DEVICE_ADDR	0xff000000
+#define FR30_DEVICE_LEN		0x00ffffff
+
+/* sim_core_attach device argument.  */
+extern device fr30_devices;
+
+/* FIXME: Temporary, until device support ready.  */
+struct _device { int foo; };
+
+/* Handle the trap insn.  */
+USI fr30_int (SIM_CPU *, PCADDR, int);
+
+#endif /* FR30_SIM_H */

sim/fr30/fr30.c

@@ -0,0 +1,423 @@
+/* fr30 simulator support code
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#define WANT_CPU
+#define WANT_CPU_FR30BF
+
+#include "sim-main.h"
+#include "cgen-mem.h"
+#include "cgen-ops.h"
+
+/* Convert gdb dedicated register number to actual dr reg number.  */
+
+static int
+decode_gdb_dr_regnum (int gdb_regnum)
+{
+  switch (gdb_regnum)
+    {
+    case TBR_REGNUM : return H_DR_TBR;
+    case RP_REGNUM : return H_DR_RP;
+    case SSP_REGNUM : return H_DR_SSP;
+    case USP_REGNUM : return H_DR_USP;
+    case MDH_REGNUM : return H_DR_MDH;
+    case MDL_REGNUM : return H_DR_MDL;
+    }
+  abort ();
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+fr30bf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  if (rn < 16)
+    SETTWI (buf, a_fr30_h_gr_get (current_cpu, rn));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+	SETTWI (buf, a_fr30_h_pc_get (current_cpu));
+	break;
+      case PS_REGNUM :
+	SETTWI (buf, a_fr30_h_ps_get (current_cpu));
+	break;
+      case TBR_REGNUM :
+      case RP_REGNUM :
+      case SSP_REGNUM :
+      case USP_REGNUM :
+      case MDH_REGNUM :
+      case MDL_REGNUM :
+	SETTWI (buf, a_fr30_h_dr_get (current_cpu,
+				      decode_gdb_dr_regnum (rn)));
+	break;
+      default :
+	return 0;
+      }
+
+  return -1; /*FIXME*/
+}
+
+/* The contents of BUF are in target byte order.  */
+
+int
+fr30bf_store_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len)
+{
+  if (rn < 16)
+    a_fr30_h_gr_set (current_cpu, rn, GETTWI (buf));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+	a_fr30_h_pc_set (current_cpu, GETTWI (buf));
+	break;
+      case PS_REGNUM :
+	a_fr30_h_ps_set (current_cpu, GETTWI (buf));
+	break;
+      case TBR_REGNUM :
+      case RP_REGNUM :
+      case SSP_REGNUM :
+      case USP_REGNUM :
+      case MDH_REGNUM :
+      case MDL_REGNUM :
+	a_fr30_h_dr_set (current_cpu,
+			 decode_gdb_dr_regnum (rn),
+			 GETTWI (buf));
+	break;
+      default :
+	return 0;
+      }
+
+  return -1; /*FIXME*/
+}
+
+/* Cover fns to access the ccr bits.  */
+
+BI
+fr30bf_h_sbit_get_handler (SIM_CPU *current_cpu)
+{
+  return CPU (h_sbit);
+}
+
+void
+fr30bf_h_sbit_set_handler (SIM_CPU *current_cpu, BI newval)
+{
+  int old_sbit = CPU (h_sbit);
+  int new_sbit = (newval != 0);
+
+  CPU (h_sbit) = new_sbit;
+
+  /* When switching stack modes, update the registers.  */
+  if (old_sbit != new_sbit)
+    {
+      if (old_sbit)
+	{
+	  /* Switching user -> system.  */
+	  CPU (h_dr[H_DR_USP]) = CPU (h_gr[H_GR_SP]);
+	  CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_SSP]);
+	}
+      else
+	{
+	  /* Switching system -> user.  */
+	  CPU (h_dr[H_DR_SSP]) = CPU (h_gr[H_GR_SP]);
+	  CPU (h_gr[H_GR_SP]) = CPU (h_dr[H_DR_USP]);
+	}
+    }
+
+  /* TODO: r15 interlock */
+}
+
+/* Cover fns to access the ccr bits.  */
+
+UQI
+fr30bf_h_ccr_get_handler (SIM_CPU *current_cpu)
+{
+  int ccr = (  (GET_H_CBIT () << 0)
+	     | (GET_H_VBIT () << 1)
+	     | (GET_H_ZBIT () << 2)
+	     | (GET_H_NBIT () << 3)
+	     | (GET_H_IBIT () << 4)
+	     | (GET_H_SBIT () << 5));
+
+  return ccr;
+}
+
+void
+fr30bf_h_ccr_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  int ccr = newval & 0x3f;
+
+  SET_H_CBIT ((ccr & 1) != 0);
+  SET_H_VBIT ((ccr & 2) != 0);
+  SET_H_ZBIT ((ccr & 4) != 0);
+  SET_H_NBIT ((ccr & 8) != 0);
+  SET_H_IBIT ((ccr & 0x10) != 0);
+  SET_H_SBIT ((ccr & 0x20) != 0);
+}
+
+/* Cover fns to access the scr bits.  */
+
+UQI
+fr30bf_h_scr_get_handler (SIM_CPU *current_cpu)
+{
+  int scr = (  (GET_H_TBIT () << 0)
+	     | (GET_H_D0BIT () << 1)
+	     | (GET_H_D1BIT () << 2));
+  return scr;
+}
+
+void
+fr30bf_h_scr_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  int scr = newval & 7;
+
+  SET_H_TBIT  ((scr & 1) != 0);
+  SET_H_D0BIT ((scr & 2) != 0);
+  SET_H_D1BIT ((scr & 4) != 0);
+}
+
+/* Cover fns to access the ilm bits.  */
+
+UQI
+fr30bf_h_ilm_get_handler (SIM_CPU *current_cpu)
+{
+  return CPU (h_ilm);
+}
+
+void
+fr30bf_h_ilm_set_handler (SIM_CPU *current_cpu, UQI newval)
+{
+  int ilm = newval & 0x1f;
+  int current_ilm = CPU (h_ilm);
+
+  /* We can only set new ilm values < 16 if the current ilm is < 16.  Otherwise
+     we add 16 to the value we are given.  */
+  if (current_ilm >= 16 && ilm < 16)
+    ilm += 16;
+
+  CPU (h_ilm) = ilm;
+}
+
+/* Cover fns to access the ps register.  */
+
+USI
+fr30bf_h_ps_get_handler (SIM_CPU *current_cpu)
+{
+  int ccr = GET_H_CCR ();
+  int scr = GET_H_SCR ();
+  int ilm = GET_H_ILM ();
+
+  return ccr | (scr << 8) | (ilm << 16);
+}
+
+void
+fr30bf_h_ps_set_handler (SIM_CPU *current_cpu, USI newval)
+{
+  int ccr = newval & 0xff;
+  int scr = (newval >> 8) & 7;
+  int ilm = (newval >> 16) & 0x1f;
+
+  SET_H_CCR (ccr);
+  SET_H_SCR (scr);
+  SET_H_ILM (ilm);
+}
+
+/* Cover fns to access the dedicated registers.  */
+
+SI
+fr30bf_h_dr_get_handler (SIM_CPU *current_cpu, UINT dr)
+{
+  switch (dr)
+    {
+    case H_DR_SSP :
+      if (! GET_H_SBIT ())
+	return GET_H_GR (H_GR_SP);
+      else
+	return CPU (h_dr[H_DR_SSP]);
+    case H_DR_USP :
+      if (GET_H_SBIT ())
+	return GET_H_GR (H_GR_SP);
+      else
+	return CPU (h_dr[H_DR_USP]);
+    case H_DR_TBR :
+    case H_DR_RP :
+    case H_DR_MDH :
+    case H_DR_MDL :
+      return CPU (h_dr[dr]);
+    }
+  return 0;
+}
+
+void
+fr30bf_h_dr_set_handler (SIM_CPU *current_cpu, UINT dr, SI newval)
+{
+  switch (dr)
+    {
+    case H_DR_SSP :
+      if (! GET_H_SBIT ())
+	SET_H_GR (H_GR_SP, newval);
+      else
+	CPU (h_dr[H_DR_SSP]) = newval;
+      break;
+    case H_DR_USP :
+      if (GET_H_SBIT ())
+	SET_H_GR (H_GR_SP, newval);
+      else
+	CPU (h_dr[H_DR_USP]) = newval;
+      break;
+    case H_DR_TBR :
+    case H_DR_RP :
+    case H_DR_MDH :
+    case H_DR_MDL :
+      CPU (h_dr[dr]) = newval;
+      break;
+    }
+}
+
+#if WITH_PROFILE_MODEL_P
+
+/* FIXME: Some of these should be inline or macros.  Later.  */
+
+/* Initialize cycle counting for an insn.
+   FIRST_P is non-zero if this is the first insn in a set of parallel
+   insns.  */
+
+void
+fr30bf_model_insn_before (SIM_CPU *cpu, int first_p)
+{
+  MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+  d->load_regs_pending = 0;
+}
+
+/* Record the cycles computed for an insn.
+   LAST_P is non-zero if this is the last insn in a set of parallel insns,
+   and we update the total cycle count.
+   CYCLES is the cycle count of the insn.  */
+
+void
+fr30bf_model_insn_after (SIM_CPU *cpu, int last_p, int cycles)
+{
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+
+  PROFILE_MODEL_TOTAL_CYCLES (p) += cycles;
+  PROFILE_MODEL_CUR_INSN_CYCLES (p) = cycles;
+  d->load_regs = d->load_regs_pending;
+}
+
+static INLINE int
+check_load_stall (SIM_CPU *cpu, int regno)
+{
+  const MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+  UINT load_regs = d->load_regs;
+
+  if (regno != -1
+      && (load_regs & (1 << regno)) != 0)
+    {
+      PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+      ++ PROFILE_MODEL_LOAD_STALL_CYCLES (p);
+      if (TRACE_INSN_P (cpu))
+	cgen_trace_printf (cpu, " ; Load stall.");
+      return 1;
+    }
+  else
+    return 0;
+}
+
+int
+fr30bf_model_fr30_1_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_Ri, INT in_Rj, INT out_Ri)
+{
+  int cycles = idesc->timing->units[unit_num].done;
+  cycles += check_load_stall (cpu, in_Ri);
+  cycles += check_load_stall (cpu, in_Rj);
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_cti (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT in_Ri)
+{
+  PROFILE_DATA *p = CPU_PROFILE_DATA (cpu);
+  /* (1 << 1): The pc is the 2nd element in inputs, outputs.
+     ??? can be cleaned up */
+  int taken_p = (referenced & (1 << 1)) != 0;
+  int cycles = idesc->timing->units[unit_num].done;
+  int delay_slot_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT);
+
+  cycles += check_load_stall (cpu, in_Ri);
+  if (taken_p)
+    {
+      /* ??? Handling cti's without delay slots this way will run afoul of
+	 accurate system simulation.  Later.  */
+      if (! delay_slot_p)
+	{
+	  ++cycles;
+	  ++PROFILE_MODEL_CTI_STALL_CYCLES (p);
+	}
+      ++PROFILE_MODEL_TAKEN_COUNT (p);
+    }
+  else
+    ++PROFILE_MODEL_UNTAKEN_COUNT (p);
+
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_load (SIM_CPU *cpu, const IDESC *idesc,
+			    int unit_num, int referenced,
+			    INT in_Rj, INT out_Ri)
+{
+  MODEL_FR30_1_DATA *d = CPU_MODEL_DATA (cpu);
+  int cycles = idesc->timing->units[unit_num].done;
+  d->load_regs_pending |= 1 << out_Ri;
+  cycles += check_load_stall (cpu, in_Rj);
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_store (SIM_CPU *cpu, const IDESC *idesc,
+			     int unit_num, int referenced,
+			     INT in_Ri, INT in_Rj)
+{
+  int cycles = idesc->timing->units[unit_num].done;
+  cycles += check_load_stall (cpu, in_Ri);
+  cycles += check_load_stall (cpu, in_Rj);
+  return cycles;
+}
+
+int
+fr30bf_model_fr30_1_u_ldm (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT reglist)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+int
+fr30bf_model_fr30_1_u_stm (SIM_CPU *cpu, const IDESC *idesc,
+			   int unit_num, int referenced,
+			   INT reglist)
+{
+  return idesc->timing->units[unit_num].done;
+}
+
+#endif /* WITH_PROFILE_MODEL_P */

sim/fr30/mloop.in

@@ -0,0 +1,236 @@
+# Simulator main loop for fr30. -*- C -*-
+# Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+# Contributed by Cygnus Solutions.
+#
+# This file is part of the GNU Simulators.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2, or (at your option)
+# any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License along
+# with this program; if not, write to the Free Software Foundation, Inc.,
+# 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+# Syntax:
+# /bin/sh mainloop.in command
+#
+# Command is one of:
+#
+# init
+# support
+# extract-{simple,scache,pbb}
+# {full,fast}-exec-{simple,scache,pbb}
+#
+# A target need only provide a "full" version of one of simple,scache,pbb.
+# If the target wants it can also provide a fast version of same.
+# It can't provide more than this, however for illustration's sake the FR30
+# port provides examples of all.
+
+# ??? After a few more ports are done, revisit.
+# Will eventually need to machine generate a lot of this.
+
+case "x$1" in
+
+xsupport)
+
+cat <<EOF
+
+static INLINE const IDESC *
+extract (SIM_CPU *current_cpu, PCADDR pc, CGEN_INSN_INT insn, ARGBUF *abuf,
+         int fast_p)
+{
+  const IDESC *id = @cpu@_decode (current_cpu, pc, insn, abuf);
+  @cpu@_fill_argbuf (current_cpu, abuf, id, pc, fast_p);
+  if (! fast_p)
+    {
+      int trace_p = PC_IN_TRACE_RANGE_P (current_cpu, pc);
+      int profile_p = PC_IN_PROFILE_RANGE_P (current_cpu, pc);
+      @cpu@_fill_argbuf_tp (current_cpu, abuf, trace_p, profile_p);
+    }
+  return id;
+}
+
+static INLINE SEM_PC
+execute (SIM_CPU *current_cpu, SCACHE *sc, int fast_p)
+{
+  SEM_PC vpc;
+
+  if (fast_p)
+    {
+#if ! WITH_SEM_SWITCH_FAST
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_fast) (current_cpu, &sc->argbuf);
+#endif
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FAST */
+    }
+  else
+    {
+#if ! WITH_SEM_SWITCH_FULL
+      ARGBUF *abuf = &sc->argbuf;
+      const IDESC *idesc = abuf->idesc;
+#if WITH_SCACHE_PBB
+      int virtual_p = CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_VIRTUAL);
+#else
+      int virtual_p = 0;
+#endif
+
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-before */
+	  if (ARGBUF_PROFILE_P (abuf))
+	    PROFILE_COUNT_INSN (current_cpu, abuf->addr, idesc->num);
+	  /* FIXME: Later make cover macros: PROFILE_INSN_{INIT,FINI}.  */
+	  if (PROFILE_MODEL_P (current_cpu)
+	      && ARGBUF_PROFILE_P (abuf))
+	    @cpu@_model_insn_before (current_cpu, 1 /*first_p*/);
+	  TRACE_INSN_INIT (current_cpu, abuf, 1);
+	  TRACE_INSN (current_cpu, idesc->idata,
+		      (const struct argbuf *) abuf, abuf->addr);
+	}
+#if WITH_SCACHE
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, sc);
+#else
+      vpc = (*sc->argbuf.semantic.sem_full) (current_cpu, abuf);
+#endif
+      if (! virtual_p)
+	{
+	  /* FIXME: call x-after */
+	  if (PROFILE_MODEL_P (current_cpu)
+	      && ARGBUF_PROFILE_P (abuf))
+	    {
+	      int cycles;
+
+	      cycles = (*idesc->timing->model_fn) (current_cpu, sc);
+	      @cpu@_model_insn_after (current_cpu, 1 /*last_p*/, cycles);
+	    }
+	  TRACE_INSN_FINI (current_cpu, abuf, 1);
+	}
+#else
+      abort ();
+#endif /* WITH_SEM_SWITCH_FULL */
+    }
+
+  return vpc;
+}
+
+EOF
+
+;;
+
+xinit)
+
+cat <<EOF
+/*xxxinit*/
+EOF
+
+;;
+
+xextract-simple | xextract-scache)
+
+# Inputs:  current_cpu, vpc, sc, FAST_P
+# Outputs: sc filled in
+
+cat <<EOF
+{
+  CGEN_INSN_INT insn = GETIMEMUHI (current_cpu, vpc);
+  extract (current_cpu, vpc, insn, SEM_ARGBUF (sc), FAST_P);
+}
+EOF
+
+;;
+
+xextract-pbb)
+
+# Inputs:  current_cpu, pc, sc, max_insns, FAST_P
+# Outputs: sc, pc
+# sc must be left pointing past the last created entry.
+# pc must be left pointing past the last created entry.
+# If the pbb is terminated by a cti insn, SET_CTI_VPC(sc) must be called
+# to record the vpc of the cti insn.
+# SET_INSN_COUNT(n) must be called to record number of real insns.
+
+cat <<EOF
+{
+  const IDESC *idesc;
+  int icount = 0;
+
+  while (max_insns > 0)
+    {
+      UHI insn = GETIMEMUHI (current_cpu, pc);
+      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+      ++sc;
+      --max_insns;
+      ++icount;
+      pc += idesc->length;
+      if (IDESC_CTI_P (idesc))
+	{
+	  SET_CTI_VPC (sc - 1);
+
+	  /* Delay slot? */
+	  /* ??? breakpoints in delay slots */
+	  if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_DELAY_SLOT))
+	    {
+	      UHI insn = GETIMEMUHI (current_cpu, pc);
+	      idesc = extract (current_cpu, pc, insn, &sc->argbuf, FAST_P);
+	      if (CGEN_ATTR_VALUE (NULL, idesc->attrs, CGEN_INSN_NOT_IN_DELAY_SLOT))
+		{
+		  /* malformed program */
+		  sim_io_eprintf (CPU_STATE (current_cpu),
+				  "malformed program, \`%s' insn in delay slot\n",
+				  CGEN_INSN_NAME (idesc->idata));
+		}
+	      else
+		{
+		  ++sc;
+		  --max_insns;
+		  ++icount;
+		  pc += idesc->length;
+		}
+	    }
+	  break;
+	}
+    }
+
+ Finish:
+  SET_INSN_COUNT (icount);
+}
+EOF
+
+;;
+
+xfull-exec-* | xfast-exec-*)
+
+# Inputs: current_cpu, sc, FAST_P
+# Outputs: vpc
+# vpc contains the address of the next insn to execute
+
+cat <<EOF
+{
+#if (! FAST_P && WITH_SEM_SWITCH_FULL) || (FAST_P && WITH_SEM_SWITCH_FAST)
+#define DEFINE_SWITCH
+#include "sem-switch.c"
+#else
+  vpc = execute (current_cpu, vpc, FAST_P);
+#endif
+}
+EOF
+
+;;
+
+*)
+  echo "Invalid argument to mainloop.in: $1" >&2
+  exit 1
+  ;;
+
+esac

sim/fr30/sim-if.c

@@ -0,0 +1,208 @@
+/* Main simulator entry points specific to the FR30.
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#ifdef HAVE_STDLIB_H
+#include <stdlib.h>
+#endif
+#include "sim-options.h"
+#include "libiberty.h"
+#include "bfd.h"
+
+static void free_state (SIM_DESC);
+static void print_fr30_misc_cpu (SIM_CPU *cpu, int verbose);
+
+/* Records simulator descriptor so utilities like fr30_dump_regs can be
+   called from gdb.  */
+SIM_DESC current_state;
+
+/* Cover function of sim_state_free to free the cpu buffers as well.  */
+
+static void
+free_state (SIM_DESC sd)
+{
+  if (STATE_MODULES (sd) != NULL)
+    sim_module_uninstall (sd);
+  sim_cpu_free_all (sd);
+  sim_state_free (sd);
+}
+
+/* Create an instance of the simulator.  */
+
+SIM_DESC
+sim_open (kind, callback, abfd, argv)
+     SIM_OPEN_KIND kind;
+     host_callback *callback;
+     struct _bfd *abfd;
+     char **argv;
+{
+  char c;
+  int i;
+  SIM_DESC sd = sim_state_alloc (kind, callback);
+
+  /* The cpu data is kept in a separately allocated chunk of memory.  */
+  if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: pc is in mach-specific struct */
+  /* FIXME: watchpoints code shouldn't need this */
+  {
+    SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+    STATE_WATCHPOINTS (sd)->pc = &(PC);
+    STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
+  }
+#endif
+
+  if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0 /* FIXME: 'twould be nice if we could do this */
+  /* These options override any module options.
+     Obviously ambiguity should be avoided, however the caller may wish to
+     augment the meaning of an option.  */
+  if (extra_options != NULL)
+    sim_add_option_table (sd, extra_options);
+#endif
+
+  /* getopt will print the error message so we just have to exit if this fails.
+     FIXME: Hmmm...  in the case of gdb we need getopt to call
+     print_filtered.  */
+  if (sim_parse_args (sd, argv) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+#if 0
+  /* Allocate a handler for the control registers and other devices
+     if no memory for that range has been allocated by the user.
+     All are allocated in one chunk to keep things from being
+     unnecessarily complicated.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, FR30_DEVICE_ADDR, 1) == 0)
+    sim_core_attach (sd, NULL,
+		     0 /*level*/,
+		     access_read_write,
+		     0 /*space ???*/,
+		     FR30_DEVICE_ADDR, FR30_DEVICE_LEN /*nr_bytes*/,
+		     0 /*modulo*/,
+		     &fr30_devices,
+		     NULL /*buffer*/);
+#endif
+
+  /* Allocate core managed memory if none specified by user.
+     Use address 4 here in case the user wanted address 0 unmapped.  */
+  if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0)
+    sim_do_commandf (sd, "memory region 0,0x%lx", FR30_DEFAULT_MEM_SIZE);
+
+  /* check for/establish the reference program image */
+  if (sim_analyze_program (sd,
+			   (STATE_PROG_ARGV (sd) != NULL
+			    ? *STATE_PROG_ARGV (sd)
+			    : NULL),
+			   abfd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Establish any remaining configuration options.  */
+  if (sim_config (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  if (sim_post_argv_init (sd) != SIM_RC_OK)
+    {
+      free_state (sd);
+      return 0;
+    }
+
+  /* Open a copy of the cpu descriptor table.  */
+  {
+    CGEN_CPU_DESC cd = fr30_cgen_cpu_open (STATE_ARCHITECTURE (sd)->mach,
+					   CGEN_ENDIAN_BIG);
+    for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+      {
+	SIM_CPU *cpu = STATE_CPU (sd, i);
+	CPU_CPU_DESC (cpu) = cd;
+	CPU_DISASSEMBLER (cpu) = sim_cgen_disassemble_insn;
+      }
+    fr30_cgen_init_dis (cd);
+  }
+
+  /* Initialize various cgen things not done by common framework.
+     Must be done after fr30_cgen_cpu_open.  */
+  cgen_init (sd);
+
+  /* Store in a global so things like sparc32_dump_regs can be invoked
+     from the gdb command line.  */
+  current_state = sd;
+
+  return sd;
+}
+
+void
+sim_close (sd, quitting)
+     SIM_DESC sd;
+     int quitting;
+{
+  fr30_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
+  sim_module_uninstall (sd);
+}
+
+SIM_RC
+sim_create_inferior (sd, abfd, argv, envp)
+     SIM_DESC sd;
+     struct _bfd *abfd;
+     char **argv;
+     char **envp;
+{
+  SIM_CPU *current_cpu = STATE_CPU (sd, 0);
+  SIM_ADDR addr;
+
+  if (abfd != NULL)
+    addr = bfd_get_start_address (abfd);
+  else
+    addr = 0;
+  sim_pc_set (current_cpu, addr);
+
+#if 0
+  STATE_ARGV (sd) = sim_copy_argv (argv);
+  STATE_ENVP (sd) = sim_copy_argv (envp);
+#endif
+
+  return SIM_RC_OK;
+}
+
+void
+sim_do_command (sd, cmd)
+     SIM_DESC sd;
+     char *cmd;
+{ 
+  if (sim_args_command (sd, cmd) != SIM_RC_OK)
+    sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
+}

sim/fr30/sim-main.h

@@ -0,0 +1,70 @@
+/* Main header for the fr30.  */
+
+#define USING_SIM_BASE_H /* FIXME: quick hack */
+
+struct _sim_cpu; /* FIXME: should be in sim-basics.h */
+typedef struct _sim_cpu SIM_CPU;
+
+/* sim-basics.h includes config.h but cgen-types.h must be included before
+   sim-basics.h and cgen-types.h needs config.h.  */
+#include "config.h"
+
+#include "symcat.h"
+#include "sim-basics.h"
+#include "cgen-types.h"
+#include "fr30-desc.h"
+#include "fr30-opc.h"
+#include "arch.h"
+
+/* These must be defined before sim-base.h.  */
+typedef USI sim_cia;
+
+#define CIA_GET(cpu)     CPU_PC_GET (cpu)
+#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
+
+#include "sim-base.h"
+#include "cgen-sim.h"
+#include "fr30-sim.h"
+
+/* The _sim_cpu struct.  */
+
+struct _sim_cpu {
+  /* sim/common cpu base.  */
+  sim_cpu_base base;
+
+  /* Static parts of cgen.  */
+  CGEN_CPU cgen_cpu;
+
+  /* CPU specific parts go here.
+     Note that in files that don't need to access these pieces WANT_CPU_FOO
+     won't be defined and thus these parts won't appear.  This is ok in the
+     sense that things work.  It is a source of bugs though.
+     One has to of course be careful to not take the size of this
+     struct and no structure members accessed in non-cpu specific files can
+     go after here.  Oh for a better language.  */
+#if defined (WANT_CPU_FR30BF)
+  FR30BF_CPU_DATA cpu_data;
+#endif
+};
+
+/* The sim_state struct.  */
+
+struct sim_state {
+  sim_cpu *cpu;
+#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
+
+  CGEN_STATE cgen_state;
+
+  sim_state_base base;
+};
+
+/* Misc.  */
+
+/* Catch address exceptions.  */
+extern SIM_CORE_SIGNAL_FN fr30_core_signal;
+#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
+fr30_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
+		  (TRANSFER), (ERROR))
+
+/* Default memory size.  */
+#define FR30_DEFAULT_MEM_SIZE 0x800000 /* 8M */

sim/fr30/tconfig.in

@@ -0,0 +1,42 @@
+/* FR30 target configuration file.  -*- C -*- */
+
+/* Define this if the simulator can vary the size of memory.
+   See the xxx simulator for an example.
+   This enables the `-m size' option.
+   The memory size is stored in STATE_MEM_SIZE.  */
+/* Not used for FR30 since we use the memory module. TODO -- check this  */
+/* #define SIM_HAVE_MEM_SIZE */
+
+/* See sim-hload.c.  We properly handle LMA. -- TODO: check this */
+#define SIM_HANDLES_LMA 1
+
+/* For MSPR support.  FIXME: revisit.  */
+#define WITH_DEVICES 1
+
+/* FIXME: Revisit.  */
+#ifdef HAVE_DV_SOCKSER
+MODULE_INSTALL_FN dv_sockser_install;
+#define MODULE_LIST dv_sockser_install,
+#endif
+
+#if 0
+/* Enable watchpoints.  */
+#define WITH_WATCHPOINTS 1
+#endif
+
+/* ??? Temporary hack until model support unified.  */
+#define SIM_HAVE_MODEL
+
+/* Define this to enable the intrinsic breakpoint mechanism. */
+/* FIXME: may be able to remove SIM_HAVE_BREAKPOINTS since it essentially
+   duplicates ifdef SIM_BREAKPOINT (right?) */
+#if 0
+#define SIM_HAVE_BREAKPOINTS
+#define SIM_BREAKPOINT { 0x10, 0xf1 }
+#define SIM_BREAKPOINT_SIZE 2
+#endif
+
+/* This is a global setting.  Different cpu families can't mix-n-match -scache
+   and -pbb.  However some cpu families may use -simple while others use
+   one of -scache/-pbb. ???? */
+#define WITH_SCACHE_PBB 1

sim/fr30/traps.c

@@ -0,0 +1,217 @@
+/* fr30 exception, interrupt, and trap (EIT) support
+   Copyright (C) 1998, 1999 Free Software Foundation, Inc.
+   Contributed by Cygnus Solutions.
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
+
+#include "sim-main.h"
+#include "targ-vals.h"
+#include "cgen-engine.h"
+
+/* The semantic code invokes this for invalid (unrecognized) instructions.  */
+
+void
+sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+
+#if 0
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      h_bsm_set (current_cpu, h_sm_get (current_cpu));
+      h_bie_set (current_cpu, h_ie_get (current_cpu));
+      h_bcond_set (current_cpu, h_cond_get (current_cpu));
+      /* sm not changed */
+      h_ie_set (current_cpu, 0);
+      h_cond_set (current_cpu, 0);
+
+      h_bpc_set (current_cpu, cia);
+
+      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+			  EIT_RSVD_INSN_ADDR);
+    }
+  else
+#endif
+    sim_engine_halt (sd, current_cpu, NULL, cia, sim_stopped, SIM_SIGILL);
+}
+
+/* Process an address exception.  */
+
+void
+fr30_core_signal (SIM_DESC sd, SIM_CPU *current_cpu, sim_cia cia,
+		  unsigned int map, int nr_bytes, address_word addr,
+		  transfer_type transfer, sim_core_signals sig)
+{
+#if 0
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      h_bsm_set (current_cpu, h_sm_get (current_cpu));
+      h_bie_set (current_cpu, h_ie_get (current_cpu));
+      h_bcond_set (current_cpu, h_cond_get (current_cpu));
+      /* sm not changed */
+      h_ie_set (current_cpu, 0);
+      h_cond_set (current_cpu, 0);
+
+      h_bpc_set (current_cpu, cia);
+
+      sim_engine_restart (CPU_STATE (current_cpu), current_cpu, NULL,
+			  EIT_ADDR_EXCP_ADDR);
+    }
+  else
+#endif
+    sim_core_signal (sd, current_cpu, cia, map, nr_bytes, addr,
+		     transfer, sig);
+}
+
+/* Read/write functions for system call interface.  */
+
+static int
+syscall_read_mem (host_callback *cb, struct cb_syscall *sc,
+		  unsigned long taddr, char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_read_buffer (sd, cpu, read_map, buf, taddr, bytes);
+}
+
+static int
+syscall_write_mem (host_callback *cb, struct cb_syscall *sc,
+		   unsigned long taddr, const char *buf, int bytes)
+{
+  SIM_DESC sd = (SIM_DESC) sc->p1;
+  SIM_CPU *cpu = (SIM_CPU *) sc->p2;
+
+  return sim_core_write_buffer (sd, cpu, write_map, buf, taddr, bytes);
+}
+
+/* Subroutine of fr30_int to save the PS and PC and setup for INT and INTE.  */
+
+static void
+setup_int (SIM_CPU *current_cpu, PCADDR pc)
+{
+  USI ssp = a_fr30_h_dr_get (current_cpu, H_DR_SSP);
+  USI ps = a_fr30_h_ps_get (current_cpu);
+
+  ssp -= 4;
+  SETMEMSI (current_cpu, pc, ssp, ps);
+  ssp -= 4;
+  SETMEMSI (current_cpu, pc, ssp, pc + 2);
+  a_fr30_h_dr_set (current_cpu, H_DR_SSP, ssp);
+  a_fr30_h_sbit_set (current_cpu, 0);
+}
+
+/* Trap support.
+   The result is the pc address to continue at.
+   Preprocessing like saving the various registers has already been done.  */
+
+USI
+fr30_int (SIM_CPU *current_cpu, PCADDR pc, int num)
+{
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  host_callback *cb = STATE_CALLBACK (sd);
+
+#ifdef SIM_HAVE_BREAKPOINTS
+  /* Check for breakpoints "owned" by the simulator first, regardless
+     of --environment.  */
+  if (num == TRAP_BREAKPOINT)
+    {
+      /* First try sim-break.c.  If it's a breakpoint the simulator "owns"
+	 it doesn't return.  Otherwise it returns and let's us try.  */
+      sim_handle_breakpoint (sd, current_cpu, pc);
+      /* Fall through.  */
+    }
+#endif
+
+  if (STATE_ENVIRONMENT (sd) == OPERATING_ENVIRONMENT)
+    {
+      /* The new pc is the trap vector entry.
+	 We assume there's a branch there to some handler.  */
+      USI new_pc;
+      setup_int (current_cpu, pc);
+      a_fr30_h_ibit_set (current_cpu, 0);
+      new_pc = GETMEMSI (current_cpu, pc,
+			 a_fr30_h_dr_get (current_cpu, H_DR_TBR)
+			 + 1024 - ((num + 1) * 4));
+      return new_pc;
+    }
+
+  switch (num)
+    {
+    case TRAP_SYSCALL :
+      {
+	/* TODO: find out what the ABI for this is */
+	CB_SYSCALL s;
+
+	CB_SYSCALL_INIT (&s);
+	s.func = a_fr30_h_gr_get (current_cpu, 0);
+	s.arg1 = a_fr30_h_gr_get (current_cpu, 4);
+	s.arg2 = a_fr30_h_gr_get (current_cpu, 5);
+	s.arg3 = a_fr30_h_gr_get (current_cpu, 6);
+
+	if (s.func == TARGET_SYS_exit)
+	  {
+	    sim_engine_halt (sd, current_cpu, NULL, pc, sim_exited, s.arg1);
+	  }
+
+	s.p1 = (PTR) sd;
+	s.p2 = (PTR) current_cpu;
+	s.read_mem = syscall_read_mem;
+	s.write_mem = syscall_write_mem;
+	cb_syscall (cb, &s);
+	a_fr30_h_gr_set (current_cpu, 2, s.errcode); /* TODO: check this one */
+	a_fr30_h_gr_set (current_cpu, 4, s.result);
+	a_fr30_h_gr_set (current_cpu, 1, s.result2); /* TODO: check this one */
+	break;
+      }
+
+    case TRAP_BREAKPOINT:
+      sim_engine_halt (sd, current_cpu, NULL, pc,
+		       sim_stopped, SIM_SIGTRAP);
+      break;
+
+    default :
+      {
+	USI new_pc;
+	setup_int (current_cpu, pc);
+	a_fr30_h_ibit_set (current_cpu, 0);
+	new_pc = GETMEMSI (current_cpu, pc,
+			   a_fr30_h_dr_get (current_cpu, H_DR_TBR)
+			   + 1024 - ((num + 1) * 4));
+	return new_pc;
+      }
+    }
+
+  /* Fake an "reti" insn.
+     Since we didn't push anything to stack, all we need to do is
+     update pc.  */
+  return pc + 2;
+}
+
+USI
+fr30_inte (SIM_CPU *current_cpu, PCADDR pc, int num)
+{
+  /* The new pc is the trap #9 vector entry.
+     We assume there's a branch there to some handler.  */
+  USI new_pc;
+  setup_int (current_cpu, pc);
+  a_fr30_h_ilm_set (current_cpu, 4);
+  new_pc = GETMEMSI (current_cpu, pc,
+		     a_fr30_h_dr_get (current_cpu, H_DR_TBR)
+		     + 1024 - ((9 + 1) * 4));
+  return new_pc;
+}