Initial creation of sourceware repository
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Stan Shebs
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425
sim/arm/armemu.h
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425
sim/arm/armemu.h
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/* armemu.h -- ARMulator emulation macros: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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extern ARMword isize;
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/***************************************************************************\
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* Condition code values *
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\***************************************************************************/
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#define EQ 0
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#define NE 1
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#define CS 2
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#define CC 3
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#define MI 4
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#define PL 5
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#define VS 6
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#define VC 7
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#define HI 8
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#define LS 9
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#define GE 10
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#define LT 11
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#define GT 12
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#define LE 13
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#define AL 14
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#define NV 15
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/***************************************************************************\
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* Shift Opcodes *
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\***************************************************************************/
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#define LSL 0
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#define LSR 1
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#define ASR 2
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#define ROR 3
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/***************************************************************************\
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* Macros to twiddle the status flags and mode *
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\***************************************************************************/
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#define NBIT ((unsigned)1L << 31)
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#define ZBIT (1L << 30)
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#define CBIT (1L << 29)
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#define VBIT (1L << 28)
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#define IBIT (1L << 7)
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#define FBIT (1L << 6)
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#define IFBITS (3L << 6)
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#define R15IBIT (1L << 27)
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#define R15FBIT (1L << 26)
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#define R15IFBITS (3L << 26)
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#define POS(i) ( (~(i)) >> 31 )
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#define NEG(i) ( (i) >> 31 )
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#ifdef MODET /* Thumb support */
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/* ??? This bit is actually in the low order bit of the PC in the hardware.
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It isn't clear if the simulator needs to model that or not. */
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#define TBIT (1L << 5)
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#define TFLAG state->TFlag
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#define SETT state->TFlag = 1
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#define CLEART state->TFlag = 0
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#define ASSIGNT(res) state->TFlag = res
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#endif
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#define NFLAG state->NFlag
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#define SETN state->NFlag = 1
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#define CLEARN state->NFlag = 0
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#define ASSIGNN(res) state->NFlag = res
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#define ZFLAG state->ZFlag
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#define SETZ state->ZFlag = 1
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#define CLEARZ state->ZFlag = 0
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#define ASSIGNZ(res) state->ZFlag = res
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#define CFLAG state->CFlag
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#define SETC state->CFlag = 1
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#define CLEARC state->CFlag = 0
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#define ASSIGNC(res) state->CFlag = res
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#define VFLAG state->VFlag
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#define SETV state->VFlag = 1
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#define CLEARV state->VFlag = 0
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#define ASSIGNV(res) state->VFlag = res
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#define IFLAG (state->IFFlags >> 1)
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#define FFLAG (state->IFFlags & 1)
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#define IFFLAGS state->IFFlags
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#define ASSIGNINT(res) state->IFFlags = (((res) >> 6) & 3)
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#define ASSIGNR15INT(res) state->IFFlags = (((res) >> 26) & 3) ;
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#define CCBITS (0xf0000000L)
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#define INTBITS (0xc0L)
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#if defined MODET && defined MODE32
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#define PCBITS (0xffffffffL)
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#else
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#define PCBITS (0xfffffffcL)
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#endif
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#define MODEBITS (0x1fL)
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#define R15INTBITS (3L << 26)
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#if defined MODET && defined MODE32
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#define R15PCBITS (0x03ffffffL)
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#else
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#define R15PCBITS (0x03fffffcL)
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#endif
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#define R15PCMODEBITS (0x03ffffffL)
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#define R15MODEBITS (0x3L)
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#ifdef MODE32
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#define PCMASK PCBITS
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#define PCWRAP(pc) (pc)
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#else
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#define PCMASK R15PCBITS
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#define PCWRAP(pc) ((pc) & R15PCBITS)
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#endif
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#define PC (state->Reg[15] & PCMASK)
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#define R15CCINTMODE (state->Reg[15] & (CCBITS | R15INTBITS | R15MODEBITS))
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#define R15INT (state->Reg[15] & R15INTBITS)
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#define R15INTPC (state->Reg[15] & (R15INTBITS | R15PCBITS))
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#define R15INTPCMODE (state->Reg[15] & (R15INTBITS | R15PCBITS | R15MODEBITS))
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#define R15INTMODE (state->Reg[15] & (R15INTBITS | R15MODEBITS))
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#define R15PC (state->Reg[15] & R15PCBITS)
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#define R15PCMODE (state->Reg[15] & (R15PCBITS | R15MODEBITS))
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#define R15MODE (state->Reg[15] & R15MODEBITS)
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#define ECC ((NFLAG << 31) | (ZFLAG << 30) | (CFLAG << 29) | (VFLAG << 28))
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#define EINT (IFFLAGS << 6)
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#define ER15INT (IFFLAGS << 26)
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#define EMODE (state->Mode)
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#ifdef MODET
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#define CPSR (ECC | EINT | EMODE | (TFLAG << 5))
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#else
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#define CPSR (ECC | EINT | EMODE)
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#endif
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#ifdef MODE32
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#define PATCHR15
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#else
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#define PATCHR15 state->Reg[15] = ECC | ER15INT | EMODE | R15PC
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#endif
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#define GETSPSR(bank) bank>0?state->Spsr[bank]:ECC | EINT | EMODE ;
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#define SETPSR(d,s) d = (s) & (ARMword)(CCBITS | INTBITS | MODEBITS)
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#define SETINTMODE(d,s) d = ((d) & CCBITS) | ((s) & (INTBITS | MODEBITS))
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#define SETCC(d,s) d = ((d) & (INTBITS | MODEBITS)) | ((s) & CCBITS)
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#define SETR15PSR(s) if (state->Mode == USER26MODE) { \
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state->Reg[15] = ((s) & CCBITS) | R15PC | ER15INT | EMODE ; \
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ASSIGNN((state->Reg[15] & NBIT) != 0) ; \
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ASSIGNZ((state->Reg[15] & ZBIT) != 0) ; \
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ASSIGNC((state->Reg[15] & CBIT) != 0) ; \
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ASSIGNV((state->Reg[15] & VBIT) != 0) ; \
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} \
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else { \
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state->Reg[15] = R15PC | (s) & (CCBITS | R15INTBITS | R15MODEBITS) ; \
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ARMul_R15Altered(state) ; \
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}
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#define SETABORT(i,m) state->Cpsr = ECC | EINT | (i) | (m)
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#ifndef MODE32
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#define VECTORS 0x20
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#define LEGALADDR 0x03ffffff
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#define VECTORACCESS(address) (address < VECTORS && ARMul_MODE26BIT && state->prog32Sig)
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#define ADDREXCEPT(address) (address > LEGALADDR && !state->data32Sig)
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#endif
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#define INTERNALABORT(address) if (address < VECTORS) \
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state->Aborted = ARMul_DataAbortV ; \
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else \
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state->Aborted = ARMul_AddrExceptnV ;
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#ifdef MODE32
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#define TAKEABORT ARMul_Abort(state,ARMul_DataAbortV)
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#else
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#define TAKEABORT if (state->Aborted == ARMul_AddrExceptnV) \
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ARMul_Abort(state,ARMul_AddrExceptnV) ; \
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else \
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ARMul_Abort(state,ARMul_DataAbortV)
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#endif
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#define CPTAKEABORT if (!state->Aborted) \
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ARMul_Abort(state,ARMul_UndefinedInstrV) ; \
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else if (state->Aborted == ARMul_AddrExceptnV) \
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ARMul_Abort(state,ARMul_AddrExceptnV) ; \
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else \
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ARMul_Abort(state,ARMul_DataAbortV)
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/***************************************************************************\
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* Different ways to start the next instruction *
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\***************************************************************************/
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#define SEQ 0
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#define NONSEQ 1
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#define PCINCEDSEQ 2
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#define PCINCEDNONSEQ 3
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#define PRIMEPIPE 4
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#define RESUME 8
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#define NORMALCYCLE state->NextInstr = 0
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#define BUSUSEDN state->NextInstr |= 1 /* the next fetch will be an N cycle */
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#define BUSUSEDINCPCS state->Reg[15] += isize ; /* a standard PC inc and an S cycle */ \
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state->NextInstr = (state->NextInstr & 0xff) | 2
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#define BUSUSEDINCPCN state->Reg[15] += isize ; /* a standard PC inc and an N cycle */ \
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state->NextInstr |= 3
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#define INCPC state->Reg[15] += isize ; /* a standard PC inc */ \
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state->NextInstr |= 2
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#define FLUSHPIPE state->NextInstr |= PRIMEPIPE
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/***************************************************************************\
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* Cycle based emulation *
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\***************************************************************************/
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#define OUTPUTCP(i,a,b)
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#define NCYCLE
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#define SCYCLE
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#define ICYCLE
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#define CCYCLE
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#define NEXTCYCLE(c)
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/***************************************************************************\
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* States of the cycle based state machine *
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\***************************************************************************/
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/***************************************************************************\
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* Macros to extract parts of instructions *
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\***************************************************************************/
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#define DESTReg (BITS(12,15))
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#define LHSReg (BITS(16,19))
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#define RHSReg (BITS(0,3))
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#define DEST (state->Reg[DESTReg])
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#ifdef MODE32
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#ifdef MODET
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#define LHS ((LHSReg == 15) ? (state->Reg[15] & 0xFFFFFFFC): (state->Reg[LHSReg]))
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#else
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#define LHS (state->Reg[LHSReg])
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#endif
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#else
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#define LHS ((LHSReg == 15) ? R15PC : (state->Reg[LHSReg]) )
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#endif
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#define MULDESTReg (BITS(16,19))
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#define MULLHSReg (BITS(0,3))
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#define MULRHSReg (BITS(8,11))
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#define MULACCReg (BITS(12,15))
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#define DPImmRHS (ARMul_ImmedTable[BITS(0,11)])
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#define DPSImmRHS temp = BITS(0,11) ; \
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rhs = ARMul_ImmedTable[temp] ; \
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if (temp > 255) /* there was a shift */ \
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ASSIGNC(rhs >> 31) ;
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#ifdef MODE32
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#define DPRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
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: GetDPRegRHS(state, instr))
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#define DPSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
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: GetDPSRegRHS(state, instr))
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#else
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#define DPRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
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: GetDPRegRHS(state, instr))
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#define DPSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
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: GetDPSRegRHS(state, instr))
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#endif
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#define LSBase state->Reg[LHSReg]
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#define LSImmRHS (BITS(0,11))
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#ifdef MODE32
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#define LSRegRHS ((BITS(4,11)==0) ? state->Reg[RHSReg] \
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: GetLSRegRHS(state, instr))
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#else
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#define LSRegRHS ((BITS(0,11)<15) ? state->Reg[RHSReg] \
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: GetLSRegRHS(state, instr))
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#endif
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#define LSMNumRegs ((ARMword)ARMul_BitList[BITS(0,7)] + \
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(ARMword)ARMul_BitList[BITS(8,15)] )
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#define LSMBaseFirst ((LHSReg == 0 && BIT(0)) || \
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(BIT(LHSReg) && BITS(0,LHSReg-1) == 0))
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#define SWAPSRC (state->Reg[RHSReg])
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#define LSCOff (BITS(0,7) << 2)
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#define CPNum BITS(8,11)
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/***************************************************************************\
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* Macro to rotate n right by b bits *
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\***************************************************************************/
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#define ROTATER(n,b) (((n)>>(b))|((n)<<(32-(b))))
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/***************************************************************************\
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* Macros to store results of instructions *
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\***************************************************************************/
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#define WRITEDEST(d) if (DESTReg==15) \
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WriteR15(state, d) ; \
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else \
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DEST = d
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#define WRITESDEST(d) if (DESTReg == 15) \
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WriteSR15(state, d) ; \
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else { \
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DEST = d ; \
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ARMul_NegZero(state, d) ; \
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}
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#define BYTETOBUS(data) ((data & 0xff) | \
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((data & 0xff) << 8) | \
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((data & 0xff) << 16) | \
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((data & 0xff) << 24))
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#define BUSTOBYTE(address,data) \
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if (state->bigendSig) \
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temp = (data >> (((address ^ 3) & 3) << 3)) & 0xff ; \
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else \
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temp = (data >> ((address & 3) << 3)) & 0xff
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#define LOADMULT(instr,address,wb) LoadMult(state,instr,address,wb)
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#define LOADSMULT(instr,address,wb) LoadSMult(state,instr,address,wb)
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#define STOREMULT(instr,address,wb) StoreMult(state,instr,address,wb)
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#define STORESMULT(instr,address,wb) StoreSMult(state,instr,address,wb)
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#define POSBRANCH ((instr & 0x7fffff) << 2)
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#define NEGBRANCH (0xff000000 | ((instr & 0xffffff) << 2))
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/***************************************************************************\
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* Values for Emulate *
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\***************************************************************************/
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#define STOP 0 /* stop */
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#define CHANGEMODE 1 /* change mode */
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#define ONCE 2 /* execute just one interation */
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#define RUN 3 /* continuous execution */
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/***************************************************************************\
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* Stuff that is shared across modes *
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\***************************************************************************/
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extern ARMword ARMul_Emulate26(ARMul_State *state) ;
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extern ARMword ARMul_Emulate32(ARMul_State *state) ;
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extern unsigned ARMul_MultTable[] ; /* Number of I cycles for a mult */
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extern ARMword ARMul_ImmedTable[] ; /* immediate DP LHS values */
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extern char ARMul_BitList[] ; /* number of bits in a byte table */
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extern void ARMul_Abort26(ARMul_State *state, ARMword) ;
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extern void ARMul_Abort32(ARMul_State *state, ARMword) ;
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extern unsigned ARMul_NthReg(ARMword instr,unsigned number) ;
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extern void ARMul_MSRCpsr(ARMul_State *state, ARMword instr, ARMword rhs) ;
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extern void ARMul_NegZero(ARMul_State *state, ARMword result) ;
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extern void ARMul_AddCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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extern void ARMul_AddOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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extern void ARMul_SubCarry(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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extern void ARMul_SubOverflow(ARMul_State *state, ARMword a, ARMword b, ARMword result) ;
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extern void ARMul_CPSRAltered(ARMul_State *state) ;
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extern void ARMul_R15Altered(ARMul_State *state) ;
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extern ARMword ARMul_SwitchMode(ARMul_State *state,ARMword oldmode, ARMword newmode) ;
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extern unsigned ARMul_NthReg(ARMword instr, unsigned number) ;
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extern void ARMul_LDC(ARMul_State *state,ARMword instr,ARMword address) ;
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extern void ARMul_STC(ARMul_State *state,ARMword instr,ARMword address) ;
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extern void ARMul_MCR(ARMul_State *state,ARMword instr, ARMword source) ;
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extern ARMword ARMul_MRC(ARMul_State *state,ARMword instr) ;
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extern void ARMul_CDP(ARMul_State *state,ARMword instr) ;
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extern unsigned IntPending(ARMul_State *state) ;
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extern ARMword ARMul_Align(ARMul_State *state, ARMword address, ARMword data) ;
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#define EVENTLISTSIZE 1024L
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/* Thumb support: */
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typedef enum {
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t_undefined, /* undefined Thumb instruction */
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t_decoded, /* instruction decoded to ARM equivalent */
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t_branch /* Thumb branch (already processed) */
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} tdstate;
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extern tdstate ARMul_ThumbDecode(ARMul_State *state,ARMword pc,ARMword tinstr, ARMword *ainstr);
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/***************************************************************************\
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* Macros to scrutinize instructions *
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\***************************************************************************/
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#define UNDEF_Test
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#define UNDEF_Shift
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#define UNDEF_MSRPC
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#define UNDEF_MRSPC
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#define UNDEF_MULPCDest
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#define UNDEF_MULDestEQOp1
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#define UNDEF_LSRBPC
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#define UNDEF_LSRBaseEQOffWb
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#define UNDEF_LSRBaseEQDestWb
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#define UNDEF_LSRPCBaseWb
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#define UNDEF_LSRPCOffWb
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#define UNDEF_LSMNoRegs
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#define UNDEF_LSMPCBase
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#define UNDEF_LSMUserBankWb
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#define UNDEF_LSMBaseInListWb
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#define UNDEF_SWPPC
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#define UNDEF_CoProHS
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#define UNDEF_MCRPC
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#define UNDEF_LSCPCBaseWb
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#define UNDEF_UndefNotBounced
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#define UNDEF_ShortInt
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#define UNDEF_IllegalMode
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#define UNDEF_Prog32SigChange
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#define UNDEF_Data32SigChange
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