FreeChainXenon/binutils-gdb
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* sparc-tdep.h (struct gdbarch_tdep): Add step_trap member.

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(sparc_address_from_register): New prototype.
(sparcnbsd_step_trap): New prototype.
* sparc-tdep.c (sparc_address_from_register): Make globally
visible.
(sparc_analyze_control_transfer): Change prototype to accept
`struct gdbarch *' as first argument.  Allow for optional hnadling
for trap instructions.
(sparc_step_trap): New function.
(sparc_software_single_step): Adjust call to
sparc_analyze_control_trabsfer.
(sparc32_gdbarch_init): Initialize TDEP->step_trap.
* sparcnbsd-tdep.c (sparcnbsd_step_trap): New function.
(sparc32nbsd_init_abi): Set TDEP->step_trap.
* sparc64obsd-tdep.c (sparc64obsd_init_abi): Set TDEP->step_trap.
* sparc64nbsd-tdep.c (sparc64nbsd_init_abi): Set TDEP->step_trap.
This commit is contained in:
Mark Kettenis 2006-01-22 20:07:38 +00:00
parent 0a8f48b9a8
commit c893be758b
6 changed files with 87 additions and 10 deletions
Download patch file Download diff file Expand all files Collapse all files

24
gdb/sparc-tdep.c
View file

@ -170,7 +170,7 @@ sparc_fetch_wcookie (void)
/* Return the contents if register REGNUM as an address. */
static CORE_ADDR
CORE_ADDR
sparc_address_from_register (int regnum)
{
ULONGEST addr;
@ -1000,7 +1000,8 @@ sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
software single-step mechanism. */
static CORE_ADDR
sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
sparc_analyze_control_transfer (struct gdbarch *arch,
CORE_ADDR pc, CORE_ADDR *npc)
{
unsigned long insn = sparc_fetch_instruction (pc);
int conditional_p = X_COND (insn) & 0x7;
@ -1038,11 +1039,14 @@ sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
branch_p = 1;
offset = 4 * X_DISP19 (insn);
}
else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
{
/* Trap instruction (TRAP). */
return gdbarch_tdep (arch)->step_trap (insn);
}
/* FIXME: Handle DONE and RETRY instructions. */
/* FIXME: Handle the Trap instruction. */
if (branch_p)
{
if (conditional_p)
@ -1070,10 +1074,17 @@ sparc_analyze_control_transfer (CORE_ADDR pc, CORE_ADDR *npc)
return 0;
}
static CORE_ADDR
sparc_step_trap (unsigned long insn)
{
return 0;
}
void
sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
{
struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
struct gdbarch *arch = current_gdbarch;
struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
static CORE_ADDR npc, nnpc;
static gdb_byte npc_save[4], nnpc_save[4];
@ -1085,7 +1096,7 @@ sparc_software_single_step (enum target_signal sig, int insert_breakpoints_p)
orig_npc = npc = sparc_address_from_register (tdep->npc_regnum);
/* Analyze the instruction at PC. */
nnpc = sparc_analyze_control_transfer (pc, &npc);
nnpc = sparc_analyze_control_transfer (arch, pc, &npc);
if (npc != 0)
target_insert_breakpoint (npc, npc_save);
if (nnpc != 0)
@ -1188,6 +1199,7 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
tdep->fpregset = NULL;
tdep->sizeof_fpregset = 0;
tdep->plt_entry_size = 0;
tdep->step_trap = sparc_step_trap;
set_gdbarch_long_double_bit (gdbarch, 128);
set_gdbarch_long_double_format (gdbarch, &floatformat_sparc_quad);