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* sparcl-tdep.c: Clean up formatting and indentation.

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This commit is contained in:
Stu Grossman 1995-01-27 01:34:48 +00:00
parent ae02b41c50
commit c746aa850b
2 changed files with 104 additions and 96 deletions
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4
gdb/ChangeLog
View file

@ -1,3 +1,7 @@
Thu Jan 26 17:32:54 1995 Stu Grossman (grossman@cygnus.com)
* sparcl-tdep.c: Clean up formatting and indentation.
Thu Jan 26 10:49:59 1995 Steve Chamberlain <sac@splat> Thu Jan 26 10:49:59 1995 Steve Chamberlain <sac@splat>
* remote-hms.c (hms_ops): Change ref of hr_load_image * remote-hms.c (hms_ops): Change ref of hr_load_image

194
gdb/sparcl-tdep.c
View file

@ -42,65 +42,65 @@ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
#define DDV_MASK 0x1 #define DDV_MASK 0x1
int int
sparclite_insert_watchpoint(addr, len, type) sparclite_insert_watchpoint (addr, len, type)
CORE_ADDR addr; CORE_ADDR addr;
int len; int len;
int type; int type;
{ {
CORE_ADDR dcr; CORE_ADDR dcr;
dcr = read_register (DCR_REGNUM); dcr = read_register (DCR_REGNUM);
if (!(dcr & DDA1_ENABLE)) if (!(dcr & DDA1_ENABLE))
{
write_register (DDA1_REGNUM, addr);
dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
if (type == 1)
{ {
write_register (DDV1_REGNUM, 0); write_register (DDA1_REGNUM, addr);
write_register (DDV2_REGNUM, 0xffffffff); dcr &= ~(DDA1_ASI_MASK | DDV_TYPE_MASK);
dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK)); dcr |= (DDA1_SUP_ASI | DDA1_ENABLE);
if (type == 1)
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_LOAD & (~DDV_COND & ~DDV_MASK));
}
else if (type == 0)
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
}
else
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_ACCESS);
}
write_register (DCR_REGNUM, dcr);
} }
else if (type == 0)
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_STORE & (~DDV_COND & ~DDV_MASK));
}
else
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_ACCESS);
}
write_register (DCR_REGNUM, dcr);
}
else if (!(dcr & DDA2_ENABLE)) else if (!(dcr & DDA2_ENABLE))
{
write_register (DDA2_REGNUM, addr);
dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
if (type == 1)
{ {
write_register (DDV1_REGNUM, 0); write_register (DDA2_REGNUM, addr);
write_register (DDV2_REGNUM, 0xffffffff); dcr &= ~(DDA2_ASI_MASK & DDV_TYPE_MASK);
dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK); dcr |= (DDA2_SUP_ASI | DDA2_ENABLE);
if (type == 1)
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_LOAD & ~DDV_COND & ~DDV_MASK);
}
else if (type == 0)
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
}
else
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_ACCESS);
}
write_register (DCR_REGNUM, dcr);
} }
else if (type == 0)
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_STORE & ~DDV_COND & ~DDV_MASK);
}
else
{
write_register (DDV1_REGNUM, 0);
write_register (DDV2_REGNUM, 0xffffffff);
dcr |= (DDV_TYPE_ACCESS);
}
write_register (DCR_REGNUM, dcr);
}
else else
return -1; return -1;
@ -108,23 +108,21 @@ CORE_ADDR dcr;
} }
int int
sparclite_remove_watchpoint(addr, len, type) sparclite_remove_watchpoint (addr, len, type)
CORE_ADDR addr; CORE_ADDR addr;
int len; int len;
int type; int type;
{ {
CORE_ADDR dcr, dda1, dda2; CORE_ADDR dcr, dda1, dda2;
dcr = read_register (DCR_REGNUM); dcr = read_register (DCR_REGNUM);
dda1 = read_register (DDA1_REGNUM); dda1 = read_register (DDA1_REGNUM);
dda2 = read_register (DDA2_REGNUM); dda2 = read_register (DDA2_REGNUM);
if ((dcr & DDA1_ENABLE) && addr == dda1) { if ((dcr & DDA1_ENABLE) && addr == dda1)
write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE)); write_register (DCR_REGNUM, (dcr & ~DDA1_ENABLE));
} else if ((dcr & DDA2_ENABLE) && addr == dda2)
else if ((dcr & DDA2_ENABLE) && addr == dda2) {
write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE)); write_register (DCR_REGNUM, (dcr & ~DDA2_ENABLE));
}
else else
return -1; return -1;
@ -132,22 +130,24 @@ CORE_ADDR dcr, dda1, dda2;
} }
int int
sparclite_insert_hw_breakpoint(addr, len) sparclite_insert_hw_breakpoint (addr, len)
CORE_ADDR addr; CORE_ADDR addr;
int len; int len;
{ {
CORE_ADDR dcr; CORE_ADDR dcr;
dcr = read_register (DCR_REGNUM); dcr = read_register (DCR_REGNUM);
if (!(dcr & DIA1_ENABLE)) { if (!(dcr & DIA1_ENABLE))
write_register (DIA1_REGNUM, addr); {
write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE)); write_register (DIA1_REGNUM, addr);
} write_register (DCR_REGNUM, (dcr | DIA1_ENABLE | DIA1_SUP_MODE));
else if (!(dcr & DIA2_ENABLE)) { }
write_register (DIA2_REGNUM, addr); else if (!(dcr & DIA2_ENABLE))
write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE)); {
} write_register (DIA2_REGNUM, addr);
write_register (DCR_REGNUM, (dcr | DIA2_ENABLE | DIA2_SUP_MODE));
}
else else
return -1; return -1;
@ -155,22 +155,20 @@ CORE_ADDR dcr;
} }
int int
sparclite_remove_hw_breakpoint(addr, shadow) sparclite_remove_hw_breakpoint (addr, shadow)
CORE_ADDR addr; CORE_ADDR addr;
int shadow; int shadow;
{ {
CORE_ADDR dcr, dia1, dia2; CORE_ADDR dcr, dia1, dia2;
dcr = read_register (DCR_REGNUM); dcr = read_register (DCR_REGNUM);
dia1 = read_register (DIA1_REGNUM); dia1 = read_register (DIA1_REGNUM);
dia2 = read_register (DIA2_REGNUM); dia2 = read_register (DIA2_REGNUM);
if ((dcr & DIA1_ENABLE) && addr == dia1) { if ((dcr & DIA1_ENABLE) && addr == dia1)
write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE)); write_register (DCR_REGNUM, (dcr & ~DIA1_ENABLE));
} else if ((dcr & DIA2_ENABLE) && addr == dia2)
else if ((dcr & DIA2_ENABLE) && addr == dia2) {
write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE)); write_register (DCR_REGNUM, (dcr & ~DIA2_ENABLE));
}
else else
return -1; return -1;
@ -178,25 +176,28 @@ CORE_ADDR dcr, dia1, dia2;
} }
int int
sparclite_check_watch_resources(type, cnt, ot) sparclite_check_watch_resources (type, cnt, ot)
int type; int type;
int cnt; int cnt;
int ot; int ot;
{ {
if (type == bp_hardware_breakpoint) { if (type == bp_hardware_breakpoint)
if (TARGET_HW_BREAK_LIMIT == 0) return 0; if (TARGET_HW_BREAK_LIMIT == 0)
else if (cnt <= TARGET_HW_BREAK_LIMIT) return 1; return 0;
} else if (cnt <= TARGET_HW_BREAK_LIMIT)
else { return 1;
if (TARGET_HW_WATCH_LIMIT == 0) return 0; else
else if (ot) return -1; if (TARGET_HW_WATCH_LIMIT == 0)
else if (cnt <= TARGET_HW_WATCH_LIMIT) return 1; return 0;
} else if (ot)
return -1;
else if (cnt <= TARGET_HW_WATCH_LIMIT)
return 1;
return -1; return -1;
} }
CORE_ADDR CORE_ADDR
sparclite_stopped_data_address() sparclite_stopped_data_address ()
{ {
CORE_ADDR dsr, dda1, dda2; CORE_ADDR dsr, dda1, dda2;
@ -204,7 +205,10 @@ sparclite_stopped_data_address()
dda1 = read_register (DDA1_REGNUM); dda1 = read_register (DDA1_REGNUM);
dda2 = read_register (DDA2_REGNUM); dda2 = read_register (DDA2_REGNUM);
if (dsr & 0x10) return dda1; if (dsr & 0x10)
else if (dsr & 0x20) return dda2; return dda1;
else return 0; else if (dsr & 0x20)
return dda2;
else
return 0;
} }