FreeChainXenon/binutils-gdb
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* m32c.cpu (Imm-8-s4n, Imm-12-s4n): New.

Browse source 
(arith-jnz16-imm4-dst-defn, arith-jnz32-imm4-dst-defn,
arith-jnz-imm4-dst-mach, arith-jnz-imm4-dst): Keep track of which
imm operand is needed.
(adjnz, sbjnz): Pass the right operands.
(unary-insn-defn, unary16-defn, unary32-defn, unary-insn-mach,
unary-insn): Add -g variants for opcodes that need to support :G.
(not.BW:G, push.BW:G): Call it.
(stzx16-imm8-imm8-dsp8sb, stzx16-imm8-imm8-dsp8fb,
stzx16-imm8-imm8-abs16): Fix operand typos.
* m32c.opc (m32c_asm_hash): Support bnCND.
(parse_signed4n, print_signed4n): New.

* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
This commit is contained in:
DJ Delorie 2005-10-27 23:54:17 +00:00
parent 53dfbcc78f
commit c6552317c1
11 changed files with 3234 additions and 2804 deletions
Download patch file Download diff file Expand all files Collapse all files

31
opcodes/m32c-asm.c
View file

@ -191,6 +191,31 @@ parse_signed4 (CGEN_CPU_DESC cd, const char **strp,
return 0;
}
static const char *
parse_signed4n (CGEN_CPU_DESC cd, const char **strp,
int opindex, signed long *valuep)
{
const char *errmsg = 0;
signed long value;
long have_zero = 0;
if (strncmp (*strp, "0x0", 3) == 0
|| (**strp == '0' && *(*strp + 1) != 'x'))
have_zero = 1;
PARSE_SIGNED;
if (value < -7 || value > 8)
return _("Immediate is out of range -7 to 8");
/* If this field may require a relocation then use larger dsp16. */
if (! have_zero && value == 0)
return _("Immediate is out of range -7 to 8");
*valuep = -value;
return 0;
}
static const char *
parse_signed8 (CGEN_CPU_DESC cd, const char **strp,
int opindex, signed long *valuep)
@ -1172,6 +1197,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_IMM_12_S4 :
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_12_S4, (long *) (& fields->f_imm_12_s4));
break;
case M32C_OPERAND_IMM_12_S4N :
errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_12_S4N, (long *) (& fields->f_imm_12_s4));
break;
case M32C_OPERAND_IMM_13_U3 :
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_13_U3, (long *) (& fields->f_imm_13_u3));
break;
@ -1241,6 +1269,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_IMM_8_S4 :
errmsg = parse_signed4 (cd, strp, M32C_OPERAND_IMM_8_S4, (long *) (& fields->f_imm_8_s4));
break;
case M32C_OPERAND_IMM_8_S4N :
errmsg = parse_signed4n (cd, strp, M32C_OPERAND_IMM_8_S4N, (long *) (& fields->f_imm_8_s4));
break;
case M32C_OPERAND_IMM_SH_12_S4 :
errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_shimm, & fields->f_imm_12_s4);
break;