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aarch64: Add support for GCSB DSYNC instruction.

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This patch adds support for Guarded control stack data synchronization
instruction (GCSB DSYNC). This instruction is allocated to existing
HINT space and uses the HINT number 19 and to match this an entry is
added to the aarch64_hint_options array.
This commit is contained in:
Srinath Parvathaneni 2023-11-02 13:07:29 +00:00 • committed by srinath
parent f985c2512a
commit c58f84d899
13 changed files with 2296 additions and 2300 deletions
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85
gas/config/tc-aarch64.c
View file

@ -4417,12 +4417,13 @@ parse_barrier (char **str)
return o->value;
}
/* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record
return 0 if successful. Otherwise return PARSE_FAIL. */
/* Parse an option for barrier, bti and guarded control stack data
synchronization instructions. Return true on matching the target
options else return false. */
static int
parse_barrier_psb (char **str,
const struct aarch64_name_value_pair ** hint_opt)
static bool
parse_hint_opt (const char *name, char **str,
const struct aarch64_name_value_pair ** hint_opt)
{
char *p, *q;
const struct aarch64_name_value_pair *o;
@ -4433,64 +4434,19 @@ parse_barrier_psb (char **str,
o = str_hash_find_n (aarch64_hint_opt_hsh, p, q - p);
if (!o)
{
set_fatal_syntax_error
( _("unknown or missing option to PSB/TSB"));
return PARSE_FAIL;
}
return false;
if (o->value != 0x11)
{
/* PSB only accepts option name 'CSYNC'. */
set_syntax_error
(_("the specified option is not accepted for PSB/TSB"));
return PARSE_FAIL;
}
if ((strcmp ("gcsb", name) == 0 && o->value != HINT_OPD_DSYNC)
|| ((strcmp ("psb", name) == 0 || strcmp ("tsb", name) == 0)
&& o->value != HINT_OPD_CSYNC)
|| ((strcmp ("bti", name) == 0)
&& (o->value != HINT_OPD_C && o->value != HINT_OPD_J
&& o->value != HINT_OPD_JC)))
return false;
*str = q;
*hint_opt = o;
return 0;
}
/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
return 0 if successful. Otherwise return PARSE_FAIL. */
static int
parse_bti_operand (char **str,
const struct aarch64_name_value_pair ** hint_opt)
{
char *p, *q;
const struct aarch64_name_value_pair *o;
p = q = *str;
while (ISALPHA (*q))
q++;
o = str_hash_find_n (aarch64_hint_opt_hsh, p, q - p);
if (!o)
{
set_fatal_syntax_error
( _("unknown option to BTI"));
return PARSE_FAIL;
}
switch (o->value)
{
/* Valid BTI operands. */
case HINT_OPD_C:
case HINT_OPD_J:
case HINT_OPD_JC:
break;
default:
set_syntax_error
(_("unknown option to BTI"));
return PARSE_FAIL;
}
*str = q;
*hint_opt = o;
return 0;
return true;
}
/* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER.
@ -7777,8 +7733,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_BARRIER_PSB:
val = parse_barrier_psb (&str, &(info->hint_option));
if (val == PARSE_FAIL)
if (!parse_hint_opt (opcode->name, &str, &(info->hint_option)))
goto failure;
break;
@ -7833,9 +7788,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
info->qualifier = vectype_to_qualifier (&vectype);
break;
case AARCH64_OPND_BARRIER_GCSB:
if (!parse_hint_opt (opcode->name, &str, &(info->hint_option)))
goto failure;
break;
case AARCH64_OPND_BTI_TARGET:
val = parse_bti_operand (&str, &(info->hint_option));
if (val == PARSE_FAIL)
if (!parse_hint_opt (opcode->name, &str, &(info->hint_option)))
goto failure;
break;

1
gas/testsuite/gas/aarch64/gcs-1.d
View file

@ -12,6 +12,7 @@
.*: d50877bf gcspopcx
.*: d50877df gcspopx
.*: d52b773f gcspopm
.*: d503227f gcsb dsync
.*: d50b7700 gcspushm x0
.*: d50b770f gcspushm x15
.*: d50b771e gcspushm x30

1
gas/testsuite/gas/aarch64/gcs-1.s
View file

@ -3,6 +3,7 @@
gcspopcx
gcspopx
gcspopm
gcsb dsync
.irp op gcspushm, gcsss1, gcsss2, gcspopm
.irp reg1 x0, x15, x30, xzr

4
gas/testsuite/gas/aarch64/hint-bad.d Normal file
View file

@ -0,0 +1,4 @@
#name: Barrier and BTI instructions with wrong targets.
#as: -march=armv8-a
#source: hint-bad.s
#error_output: hint-bad.l

8
gas/testsuite/gas/aarch64/hint-bad.l Normal file
View file

@ -0,0 +1,8 @@
[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: operand 1 must be the GCSB option name DSYNC -- `gcsb'
[^ :]+:[0-9]+: Error: operand 1 must be the GCSB option name DSYNC -- `gcsb csync'
[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `psb'
[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `psb dsync'
[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `tsb'
[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `tsb dsync'
[^ :]+:[0-9]+: Error: operand 1 must be BTI targets j/c/jc -- `bti jj'

8
gas/testsuite/gas/aarch64/hint-bad.s Normal file
View file

@ -0,0 +1,8 @@
.text
gcsb
gcsb csync
psb
psb dsync
tsb
tsb dsync
bti jj

2
gas/testsuite/gas/aarch64/system.d
View file

@ -34,7 +34,7 @@ Disassembly of section \.text:
.*: d503221f (hint #0x10|esb)
.*: d503223f (hint #0x11|psb csync)
.*: d503225f (hint #0x12|tsb csync)
.*: d503227f hint #0x13
.*: d503227f (hint #0x13|gcsb dsync)
.*: d503229f (hint #0x14|csdb)
.*: d50322bf hint #0x15
.*: d50322df (hint #0x16|clearbhb)

2
include/opcode/aarch64.h
View file

@ -517,6 +517,7 @@ enum aarch64_opnd
AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_RPRFMOP, /* Range prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
@ -1477,6 +1478,7 @@ struct aarch64_inst
/* Defining the HINT #imm values for the aarch64_hint_options. */
#define HINT_OPD_CSYNC 0x11
#define HINT_OPD_DSYNC 0x13
#define HINT_OPD_C 0x22
#define HINT_OPD_J 0x24
#define HINT_OPD_JC 0x26

340
opcodes/aarch64-asm-2.c
View file

@ -426,14 +426,15 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1188: /* movz */
value = 1188; /* --> movz. */
break;
case 1262: /* autibsp */
case 1261: /* autibz */
case 1260: /* autiasp */
case 1259: /* autiaz */
case 1258: /* pacibsp */
case 1257: /* pacibz */
case 1256: /* paciasp */
case 1255: /* paciaz */
case 1263: /* autibsp */
case 1262: /* autibz */
case 1261: /* autiasp */
case 1260: /* autiaz */
case 1259: /* pacibsp */
case 1258: /* pacibz */
case 1257: /* paciasp */
case 1256: /* paciaz */
case 1241: /* gcsb */
case 1221: /* clearbhb */
case 1220: /* tsb */
case 1219: /* psb */
@ -463,142 +464,142 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1224: /* dsb */
value = 1224; /* --> dsb. */
break;
case 1250: /* cpp */
case 1249: /* dvp */
case 1248: /* cfp */
case 1245: /* tlbi */
case 1244: /* ic */
case 1243: /* dc */
case 1242: /* at */
case 1241: /* sys */
value = 1241; /* --> sys. */
case 1251: /* cpp */
case 1250: /* dvp */
case 1249: /* cfp */
case 1246: /* tlbi */
case 1245: /* ic */
case 1244: /* dc */
case 1243: /* at */
case 1242: /* sys */
value = 1242; /* --> sys. */
break;
case 1246: /* wfet */
value = 1246; /* --> wfet. */
case 1247: /* wfet */
value = 1247; /* --> wfet. */
break;
case 1247: /* wfit */
value = 1247; /* --> wfit. */
case 1248: /* wfit */
value = 1248; /* --> wfit. */
break;
case 2064: /* bic */
case 1311: /* and */
value = 1311; /* --> and. */
case 2065: /* bic */
case 1312: /* and */
value = 1312; /* --> and. */
break;
case 1294: /* mov */
case 1313: /* and */
value = 1313; /* --> and. */
case 1295: /* mov */
case 1314: /* and */
value = 1314; /* --> and. */
break;
case 1298: /* movs */
case 1314: /* ands */
value = 1314; /* --> ands. */
case 1299: /* movs */
case 1315: /* ands */
value = 1315; /* --> ands. */
break;
case 2065: /* cmple */
case 1349: /* cmpge */
value = 1349; /* --> cmpge. */
case 2066: /* cmple */
case 1350: /* cmpge */
value = 1350; /* --> cmpge. */
break;
case 2068: /* cmplt */
case 1352: /* cmpgt */
value = 1352; /* --> cmpgt. */
case 2069: /* cmplt */
case 1353: /* cmpgt */
value = 1353; /* --> cmpgt. */
break;
case 2066: /* cmplo */
case 1354: /* cmphi */
value = 1354; /* --> cmphi. */
case 2067: /* cmplo */
case 1355: /* cmphi */
value = 1355; /* --> cmphi. */
break;
case 2067: /* cmpls */
case 1357: /* cmphs */
value = 1357; /* --> cmphs. */
case 2068: /* cmpls */
case 1358: /* cmphs */
value = 1358; /* --> cmphs. */
break;
case 1291: /* mov */
case 1379: /* cpy */
value = 1379; /* --> cpy. */
break;
case 1293: /* mov */
case 1292: /* mov */
case 1380: /* cpy */
value = 1380; /* --> cpy. */
break;
case 2075: /* fmov */
case 1296: /* mov */
case 1294: /* mov */
case 1381: /* cpy */
value = 1381; /* --> cpy. */
break;
case 1285: /* mov */
case 1393: /* dup */
value = 1393; /* --> dup. */
case 2076: /* fmov */
case 1297: /* mov */
case 1382: /* cpy */
value = 1382; /* --> cpy. */
break;
case 1288: /* mov */
case 1284: /* mov */
case 1286: /* mov */
case 1394: /* dup */
value = 1394; /* --> dup. */
break;
case 2074: /* fmov */
case 1290: /* mov */
case 1289: /* mov */
case 1285: /* mov */
case 1395: /* dup */
value = 1395; /* --> dup. */
break;
case 1289: /* mov */
case 1396: /* dupm */
value = 1396; /* --> dupm. */
case 2075: /* fmov */
case 1291: /* mov */
case 1396: /* dup */
value = 1396; /* --> dup. */
break;
case 2069: /* eon */
case 1398: /* eor */
value = 1398; /* --> eor. */
case 1290: /* mov */
case 1397: /* dupm */
value = 1397; /* --> dupm. */
break;
case 1299: /* not */
case 1400: /* eor */
value = 1400; /* --> eor. */
case 2070: /* eon */
case 1399: /* eor */
value = 1399; /* --> eor. */
break;
case 1300: /* nots */
case 1401: /* eors */
value = 1401; /* --> eors. */
case 1300: /* not */
case 1401: /* eor */
value = 1401; /* --> eor. */
break;
case 2070: /* facle */
case 1406: /* facge */
value = 1406; /* --> facge. */
case 1301: /* nots */
case 1402: /* eors */
value = 1402; /* --> eors. */
break;
case 2071: /* faclt */
case 1407: /* facgt */
value = 1407; /* --> facgt. */
case 2071: /* facle */
case 1407: /* facge */
value = 1407; /* --> facge. */
break;
case 2072: /* fcmle */
case 1420: /* fcmge */
value = 1420; /* --> fcmge. */
case 2072: /* faclt */
case 1408: /* facgt */
value = 1408; /* --> facgt. */
break;
case 2073: /* fcmlt */
case 1422: /* fcmgt */
value = 1422; /* --> fcmgt. */
case 2073: /* fcmle */
case 1421: /* fcmge */
value = 1421; /* --> fcmge. */
break;
case 2074: /* fcmlt */
case 1423: /* fcmgt */
value = 1423; /* --> fcmgt. */
break;
case 1283: /* fmov */
case 1429: /* fcpy */
value = 1429; /* --> fcpy. */
break;
case 1282: /* fmov */
case 1428: /* fcpy */
value = 1428; /* --> fcpy. */
case 1452: /* fdup */
value = 1452; /* --> fdup. */
break;
case 1281: /* fmov */
case 1451: /* fdup */
value = 1451; /* --> fdup. */
break;
case 1283: /* mov */
case 1783: /* orr */
value = 1783; /* --> orr. */
break;
case 2076: /* orn */
case 1284: /* mov */
case 1784: /* orr */
value = 1784; /* --> orr. */
break;
case 2077: /* orn */
case 1785: /* orr */
value = 1785; /* --> orr. */
break;
case 1288: /* mov */
case 1287: /* mov */
case 1286: /* mov */
case 1786: /* orr */
value = 1786; /* --> orr. */
case 1787: /* orr */
value = 1787; /* --> orr. */
break;
case 1297: /* movs */
case 1787: /* orrs */
value = 1787; /* --> orrs. */
case 1298: /* movs */
case 1788: /* orrs */
value = 1788; /* --> orrs. */
break;
case 1292: /* mov */
case 1850: /* sel */
value = 1850; /* --> sel. */
break;
case 1295: /* mov */
case 1293: /* mov */
case 1851: /* sel */
value = 1851; /* --> sel. */
break;
case 1296: /* mov */
case 1852: /* sel */
value = 1852; /* --> sel. */
break;
default: return NULL;
}
@ -642,7 +643,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 30:
case 31:
case 32:
case 169:
case 170:
case 171:
case 172:
@ -656,7 +656,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 180:
case 181:
case 182:
case 197:
case 183:
case 198:
case 199:
case 200:
@ -665,20 +665,22 @@ aarch64_insert_operand (const aarch64_operand *self,
case 203:
case 204:
case 205:
case 212:
case 215:
case 219:
case 226:
case 206:
case 213:
case 216:
case 220:
case 227:
case 234:
case 228:
case 235:
case 236:
case 237:
case 238:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 110:
case 269:
case 271:
case 111:
case 270:
case 272:
return aarch64_ins_none (self, info, code, inst, errors);
case 16:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -690,7 +692,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 34:
case 35:
case 36:
case 273:
case 274:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 37:
return aarch64_ins_reglist (self, info, code, inst, errors);
@ -726,9 +728,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 84:
case 85:
case 109:
case 166:
case 168:
case 189:
case 167:
case 169:
case 190:
case 191:
case 192:
@ -736,13 +737,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 194:
case 195:
case 196:
case 240:
case 267:
case 197:
case 241:
case 268:
case 270:
case 272:
case 277:
case 269:
case 271:
case 273:
case 278:
case 279:
return aarch64_ins_imm (self, info, code, inst, errors);
case 45:
case 46:
@ -752,10 +754,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 49:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 53:
case 156:
case 157:
return aarch64_ins_fpimm (self, info, code, inst, errors);
case 71:
case 164:
case 165:
return aarch64_ins_limm (self, info, code, inst, errors);
case 72:
return aarch64_ins_aimm (self, info, code, inst, errors);
@ -765,11 +767,11 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors);
case 76:
case 77:
case 161:
case 162:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 78:
case 160:
case 162:
case 161:
case 163:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 79:
case 80:
@ -810,26 +812,25 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
case 108:
return aarch64_ins_prfop (self, info, code, inst, errors);
case 111:
return aarch64_ins_hint (self, info, code, inst, errors);
case 112:
return aarch64_ins_hint (self, info, code, inst, errors);
case 113:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 114:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 115:
case 116:
case 117:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 118:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 119:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 120:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 121:
case 122:
case 123:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 124:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 125:
case 126:
case 127:
@ -844,8 +845,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 136:
case 137:
case 138:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 139:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 140:
case 141:
case 142:
@ -853,77 +854,77 @@ aarch64_insert_operand (const aarch64_operand *self,
case 144:
case 145:
case 146:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 147:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 148:
case 149:
case 150:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 151:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 152:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 153:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 154:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 155:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 156:
return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 157:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 158:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 159:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 160:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 163:
case 164:
return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 165:
case 166:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 167:
case 168:
return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 183:
case 184:
case 185:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 186:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 187:
case 188:
case 253:
case 189:
case 254:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 206:
case 207:
case 208:
case 209:
case 210:
case 211:
case 212:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 213:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 214:
case 216:
case 233:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 215:
case 217:
case 234:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 218:
case 220:
case 219:
case 221:
case 222:
case 223:
case 232:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 224:
case 233:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
case 225:
case 226:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
case 228:
case 230:
case 241:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 229:
case 231:
case 242:
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 230:
case 232:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
case 238:
case 239:
case 254:
case 240:
case 255:
case 256:
case 257:
@ -936,26 +937,27 @@ aarch64_insert_operand (const aarch64_operand *self,
case 264:
case 265:
case 266:
case 267:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 242:
case 243:
case 244:
case 245:
case 246:
case 247:
case 248:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 249:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
case 250:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
case 251:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case 252:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
case 253:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case 274:
case 275:
case 276:
case 277:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
default: assert (0); abort ();
}

4116
opcodes/aarch64-dis-2.c
View file

File diff suppressed because it is too large Load diff

19
opcodes/aarch64-opc-2.c
View file

@ -135,7 +135,8 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "RPRFMOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm1_15, FLD_imm2_12, FLD_imm3_0}, "a range prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_GCSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the GCSB option name DSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI_TARGET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 32"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
@ -380,18 +381,18 @@ static const unsigned op_enum_table [] =
391,
413,
415,
1286,
1287,
1292,
1284,
1283,
1288,
1295,
1297,
1293,
1285,
1284,
1289,
1296,
1298,
1294,
1300,
1299,
1295,
1301,
1300,
131,
};

5
opcodes/aarch64-opc.c
View file

@ -554,6 +554,7 @@ const struct aarch64_name_value_pair aarch64_hint_options[] =
/* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
{ " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
{ "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
{ "dsync", HINT_OPD_DSYNC }, /* GCSB DSYNC. */
{ "c", HINT_OPD_C }, /* BTI C. */
{ "j", HINT_OPD_J }, /* BTI J. */
{ "jc", HINT_OPD_JC }, /* BTI JC. */
@ -4629,6 +4630,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
snprintf (buf, size, "{%s}", style_reg (styler, "zt0"));
break;
case AARCH64_OPND_BARRIER_GCSB:
snprintf (buf, size, "%s", style_sub_mnem (styler, "dsync"));
break;
case AARCH64_OPND_BTI_TARGET:
if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
snprintf (buf, size, "%s",

5
opcodes/aarch64-tbl.h
View file

@ -4156,6 +4156,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS),
CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
@ -6300,7 +6301,9 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a range prefetch operation specifier") \
Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \
"the PSB/TSB option name CSYNC") \
Y(SYSTEM, hint, "BTI", 0, F (), \
Y(SYSTEM, none, "BARRIER_GCSB", 0, F (), \
"the GCSB option name DSYNC") \
Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \
"BTI targets j/c/jc") \
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
4 << OPD_F_OD_LSB, F(FLD_Rn), \