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Added seven new instructions ld, ld2w, sac, sachi, slae, st and

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st2w for d10v. Created new testsuite for d10v to verify new
instructions.
This commit is contained in:
Diego Novillo 1999-10-07 06:17:04 +00:00
parent 07147777d3
commit c43185deeb
7 changed files with 52 additions and 5 deletions
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5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
Thu Oct 7 00:11:50 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* config/tc-d10v.c (check_range): Check range for RESTRICTED_NUM3
operands.
Mon Oct 4 17:24:23 1999 Nick Clifton <nickc@cygnus.com>
Doug Evans <devans@cygnus.com>

17
gas/config/tc-d10v.c
View file

@ -196,10 +196,19 @@ check_range (num, bits, flags)
if (flags & OPERAND_SIGNED)
{
max = (1 << (bits - 1))-1;
min = - (1 << (bits - 1));
if (((long)num > max) || ((long)num < min))
retval = 1;
/* Signed 3-bit integers are restricted to the (-2, 3) range */
if (flags & RESTRICTED_NUM3)
{
if ((long) num < -2 || (long) num > 3)
retval = 1;
}
else
{
max = (1 << (bits - 1)) - 1;
min = - (1 << (bits - 1));
if (((long) num > max) || ((long) num < min))
retval = 1;
}
}
else
{

7
gas/testsuite/ChangeLog
View file

@ -1,3 +1,10 @@
Thu Oct 7 00:12:04 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* gas/d10v: New directory.
* gas/d10v/d10.exp: New file.
* gas/d10v/inst.s: New file.
* gas/d10v/inst.d: New file.
Thu Oct 7 12:52:25 1999 Geoffrey Keating <geoffk@cygnus.com>
* gas/mips/elf-rel.s: New file.

4
include/opcode/ChangeLog
View file

@ -1,3 +1,7 @@
Thu Oct 7 00:12:25 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* d10v.h: Add flag RESTRICTED_NUM3 for imm3 operands.
Thu Sep 23 07:08:38 1999 Jerry Quinn <jquinn@nortelnetworks.com>
* hppa.h (pa_opcodes): Add "call" and "ret". Clean up "b", "bve"

4
include/opcode/d10v.h
View file

@ -176,6 +176,10 @@ extern const struct d10v_operand d10v_operands[];
/* general purpose register */
#define OPERAND_GPR (0x40000)
/* special imm3 values with range restricted to -2 <= imm3 <= 3 */
/* needed for rac/rachi */
#define RESTRICTED_NUM3 (0x80000)
/* Structure to hold information about predefined registers. */
struct pd_reg
{

7
opcodes/ChangeLog
View file

@ -1,3 +1,10 @@
Thu Oct 7 00:12:43 MDT 1999 Diego Novillo <dnovillo@cygnus.com>
* d10v-opc.c (d10v_operands): Add RESTRICTED_NUM3 flag for
rac/rachi instructions.
(d10v_opcodes): Added seven new instructions ld, ld2w, sac, sachi,
slae, st and st2w.
1999-10-04 Doug Evans <devans@casey.cygnus.com>
* fr30-asm.c,fr30-desc.h: Rebuild.

13
opcodes/d10v-opc.c
View file

@ -115,7 +115,7 @@ const struct d10v_operand d10v_operands[] =
#define NUM16 (RDSTE + 1)
{ 16, 0, OPERAND_NUM|OPERAND_SIGNED },
#define NUM3 (NUM16 + 1) /* rac, rachi */
{ 3, 1, OPERAND_NUM|OPERAND_SIGNED },
{ 3, 1, OPERAND_NUM|OPERAND_SIGNED|RESTRICTED_NUM3 },
#define NUM4 (NUM3 + 1)
{ 4, 1, OPERAND_NUM|OPERAND_SIGNED },
#define UNUM4 (NUM4 + 1)
@ -226,10 +226,12 @@ const struct d10v_opcode d10v_opcodes[] = {
{ "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6401, 0x7e01, { RDST, ATSIGN, RSRC, MINUS } },
{ "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6001, 0x7e01, { RDST, ATSIGN, RSRC, PLUS } },
{ "ld", SHORT_2, 1, MU, PAR|RMEM, 0x6000, 0x7e01, { RDST, ATSIGN, RSRC } },
{ "ld", LONG_L, 1, MU, SEQ, 0x32010000, 0x3f0f0000, { RDST, ATSIGN, NUM16 } },
{ "ld2w", LONG_L, 1, MU, SEQ, 0x31000000, 0x3f100000, { RDSTE, ATPAR, NUM16, RSRC } },
{ "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6601, 0x7e21, { RDSTE, ATSIGN, RSRC, MINUS } },
{ "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6201, 0x7e21, { RDSTE, ATSIGN, RSRC, PLUS } },
{ "ld2w", SHORT_2, 1, MU, PAR|RMEM, 0x6200, 0x7e21, { RDSTE, ATSIGN, RSRC } },
{ "ld2w", LONG_L, 1, MU, SEQ, 0x33010000, 0x3f1f0000, { RDSTE, ATSIGN, NUM16 } },
{ "ldb", LONG_L, 1, MU, SEQ, 0x38000000, 0x3f000000, { RDST, ATPAR, NUM16, RSRC } },
{ "ldb", SHORT_2, 1, MU, PAR|RMEM, 0x7000, 0x7e01, { RDST, ATSIGN, RSRC } },
{ "ldi", OPCODE_FAKE, 0, 0, 0, 0, 0, { 1, 4, 16, 0 } },
@ -276,6 +278,12 @@ const struct d10v_opcode d10v_opcodes[] = {
{ "not", SHORT_2, 1, EITHER, PAR, 0x4603, 0x7e1f, { RDST } },
{ "or", SHORT_2, 1, EITHER, PAR, 0x800, 0x7e01, { RDST, RSRC } },
{ "or3", LONG_L, 1, MU, SEQ, 0x4000000, 0x3f000000, { RDST, RSRC, NUM16 } },
/* Special case. sac&sachi must occur before rac&rachi because they have
intersecting masks! The masks for rac&rachi will match sac&sachi but
not the other way around.
*/
{ "sac", SHORT_2, 1, IU, PAR|RF0|WF0, 0x5209, 0x7e2f, { RDSTE, ASRC } },
{ "sachi", SHORT_2, 1, IU, PAR|RF0|WF0, 0x4209, 0x7e0f, { RDST, ASRC } },
{ "rac", SHORT_2, 1, IU, PAR|WF0, 0x5201, 0x7e21, { RDSTE, ASRC0ONLY, NUM3 } },
{ "rachi", SHORT_2, 1, IU, PAR|WF0, 0x4201, 0x7e01, { RDST, ASRC, NUM3 } },
{ "rep", LONG_L, 2, MU, SEQ, 0x27000000, 0x3ff00000, { RSRC, ANUM16 } },
@ -285,6 +293,7 @@ const struct d10v_opcode d10v_opcodes[] = {
{ "sadd", SHORT_2, 1, IU, PAR, 0x1223, 0x7eef, { ADST, ASRC } },
{ "setf0f", SHORT_2, 1, MU, PAR|RF0, 0x4611, 0x7e1f, { RDST } },
{ "setf0t", SHORT_2, 1, MU, PAR|RF0, 0x4613, 0x7e1f, { RDST } },
{ "slae", SHORT_2, 1, IU, PAR, 0x3220, 0x7ee1, { ADST, RSRC } },
{ "sleep", SHORT_2, 1, MU, PAR, 0x5fc0, 0x7fff, { 0 } },
{ "sll", SHORT_2, 1, IU, PAR, 0x2200, 0x7e01, { RDST, RSRC } },
{ "sll", SHORT_2, 1, IU, PAR, 0x3200, 0x7ee1, { ADST, RSRC } },
@ -305,11 +314,13 @@ const struct d10v_opcode d10v_opcodes[] = {
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c1f, 0x7e1f, { RSRC2, ATMINUS, RSRC } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6801, 0x7e01, { RSRC2, ATSIGN, RSRC, PLUS } },
{ "st", SHORT_2, 1, MU, PAR|WMEM, 0x6c01, 0x7e01, { RSRC2, ATSIGN, RSRC, MINUS } },
{ "st", LONG_L, 1, MU, SEQ, 0x36010000, 0x3f0f0000, { RSRC2, ATSIGN, NUM16 } },
{ "st2w", LONG_L, 1, MU, SEQ, 0x35000000, 0x3f100000, { RSRC2E, ATPAR, NUM16, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a00, 0x7e21, { RSRC2E, ATSIGN, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e1f, 0x7e3f, { RSRC2E, ATMINUS, RSRC } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6a01, 0x7e21, { RSRC2E, ATSIGN, RSRC, PLUS } },
{ "st2w", SHORT_2, 1, MU, PAR|WMEM, 0x6e01, 0x7e21, { RSRC2E, ATSIGN, RSRC, MINUS } },
{ "st2w", LONG_L, 1, MU, SEQ, 0x37010000, 0x3f1f0000, { RSRC2E, ATSIGN, NUM16 } },
{ "stb", LONG_L, 1, MU, SEQ, 0x3c000000, 0x3f000000, { RSRC2, ATPAR, NUM16, RSRC } },
{ "stb", SHORT_2, 1, MU, PAR|WMEM, 0x7800, 0x7e01, { RSRC2, ATSIGN, RSRC } },
{ "stop", SHORT_2, 1, MU, PAR, 0x5fe0, 0x7fff, { 0 } },