include/opcode/
* mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and OP_SAVE_RESTORE_LIST. (decode_mips16_operand): Declare. opcodes/ * mips16-opc.c: Include mips-formats.h. (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New static arrays. (decode_mips16_operand): New function. * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete. (print_insn_arg): Handle OP_ENTRY_EXIT list. Abort for OP_SAVE_RESTORE_LIST. (print_mips16_insn_arg): Change interface. Use mips_operand structures. Delete GET_OP_S. Move GET_OP definition to... (print_insn_mips16): ...here. Call init_print_arg_state. Update the call to print_mips16_insn_arg.
This commit is contained in:
Richard Sandiford
parent
ab90248154
commit
c3c0747817
5 changed files with 338 additions and 456 deletions
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@ -51,15 +51,6 @@ struct mips_cp0sel_name
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const char * const name;
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};
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/* The mips16 registers. */
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static const unsigned int mips16_to_32_reg_map[] =
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{
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16, 17, 2, 3, 4, 5, 6, 7
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};
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#define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
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static const char * const mips_gpr_names_numeric[32] =
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{
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"$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
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@ -1128,6 +1119,54 @@ print_insn_arg (struct disassemble_info *info,
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}
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break;
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case OP_ENTRY_EXIT_LIST:
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{
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const char *sep;
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unsigned int amask, smask;
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sep = "";
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amask = (uval >> 3) & 7;
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if (amask > 0 && amask < 5)
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{
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infprintf (is, "%s", mips_gpr_names[4]);
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if (amask > 1)
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infprintf (is, "-%s", mips_gpr_names[amask + 3]);
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sep = ",";
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}
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smask = (uval >> 1) & 3;
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if (smask == 3)
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{
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infprintf (is, "%s??", sep);
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sep = ",";
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}
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else if (smask > 0)
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{
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infprintf (is, "%s%s", sep, mips_gpr_names[16]);
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if (smask > 1)
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infprintf (is, "-%s", mips_gpr_names[smask + 15]);
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sep = ",";
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}
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if (uval & 1)
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{
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infprintf (is, "%s%s", sep, mips_gpr_names[31]);
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sep = ",";
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}
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if (amask == 5 || amask == 6)
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{
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infprintf (is, "%s%s", sep, mips_fpr_names[0]);
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if (amask == 6)
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infprintf (is, "-%s", mips_fpr_names[1]);
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}
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}
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break;
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case OP_SAVE_RESTORE_LIST:
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/* Should be handled by the caller due to extend behavior. */
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abort ();
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case OP_MDMX_IMM_REG:
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{
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unsigned int vsel;
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@ -1351,22 +1390,22 @@ print_insn_mips (bfd_vma memaddr,
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/* Disassemble an operand for a mips16 instruction. */
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static void
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print_mips16_insn_arg (char type,
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const struct mips_opcode *op,
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int l,
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bfd_boolean use_extend,
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int extend,
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bfd_vma memaddr,
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struct disassemble_info *info)
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print_mips16_insn_arg (struct disassemble_info *info,
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struct mips_print_arg_state *state,
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const struct mips_opcode *opcode,
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char type, bfd_vma memaddr,
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unsigned insn, bfd_boolean use_extend,
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unsigned extend, bfd_boolean is_offset)
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{
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const fprintf_ftype infprintf = info->fprintf_func;
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void *is = info->stream;
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const struct mips_operand *operand, *ext_operand;
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unsigned int uval;
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bfd_vma baseaddr;
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if (!use_extend)
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extend = 0;
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#define GET_OP(insn, field) \
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(((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
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#define GET_OP_S(insn, field) \
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((GET_OP (insn, field) ^ ((MIPS16OP_MASK_##field >> 1) + 1)) \
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- ((MIPS16OP_MASK_##field >> 1) + 1))
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switch (type)
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{
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case ',':
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@ -1375,457 +1414,159 @@ print_mips16_insn_arg (char type,
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infprintf (is, "%c", type);
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break;
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case 'y':
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case 'w':
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infprintf (is, "%s", mips16_reg_names (GET_OP (l, RY)));
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break;
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default:
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operand = decode_mips16_operand (type, FALSE);
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if (!operand)
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{
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/* xgettext:c-format */
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infprintf (is, _("# internal error, undefined operand in `%s %s'"),
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opcode->name, opcode->args);
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return;
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}
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case 'x':
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case 'v':
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infprintf (is, "%s", mips16_reg_names (GET_OP (l, RX)));
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break;
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if (operand->type == OP_SAVE_RESTORE_LIST)
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{
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/* Handle this case here because of the complex interation
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with the EXTEND opcode. */
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unsigned int amask, nargs, nstatics, nsreg, smask, frame_size, i, j;
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const char *sep;
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case 'z':
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infprintf (is, "%s", mips16_reg_names (GET_OP (l, RZ)));
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break;
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amask = extend & 0xf;
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if (amask == MIPS16_ALL_ARGS)
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{
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nargs = 4;
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nstatics = 0;
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}
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else if (amask == MIPS16_ALL_STATICS)
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{
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nargs = 0;
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nstatics = 4;
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}
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else
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{
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nargs = amask >> 2;
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nstatics = amask & 3;
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}
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case 'Z':
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infprintf (is, "%s", mips16_reg_names (GET_OP (l, MOVE32Z)));
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break;
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sep = "";
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if (nargs > 0)
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{
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infprintf (is, "%s", mips_gpr_names[4]);
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if (nargs > 1)
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infprintf (is, "-%s", mips_gpr_names[4 + nargs - 1]);
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sep = ",";
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}
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case '0':
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infprintf (is, "%s", mips_gpr_names[0]);
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break;
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frame_size = ((extend & 0xf0) | (insn & 0x0f)) * 8;
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if (frame_size == 0 && !use_extend)
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frame_size = 128;
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infprintf (is, "%s%d", sep, frame_size);
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case 'S':
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infprintf (is, "%s", mips_gpr_names[29]);
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break;
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if (insn & 0x40) /* $ra */
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infprintf (is, ",%s", mips_gpr_names[31]);
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case 'P':
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infprintf (is, "$pc");
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break;
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nsreg = (extend >> 8) & 0x7;
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smask = 0;
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if (insn & 0x20) /* $s0 */
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smask |= 1 << 0;
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if (insn & 0x10) /* $s1 */
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smask |= 1 << 1;
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if (nsreg > 0) /* $s2-$s8 */
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smask |= ((1 << nsreg) - 1) << 2;
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case 'R':
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infprintf (is, "%s", mips_gpr_names[31]);
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break;
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case 'X':
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infprintf (is, "%s", mips_gpr_names[GET_OP (l, REGR32)]);
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break;
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case 'Y':
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infprintf (is, "%s", mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
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break;
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case '<':
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case '>':
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case '[':
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case ']':
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case '4':
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case '5':
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case 'H':
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case 'W':
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case 'D':
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case 'j':
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case '6':
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case '8':
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case 'V':
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case 'C':
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case 'U':
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case 'k':
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case 'K':
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case 'p':
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case 'q':
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case 'A':
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case 'B':
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case 'E':
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{
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int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
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shift = 0;
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signedp = 0;
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extbits = 16;
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pcrel = 0;
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extu = 0;
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branch = 0;
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switch (type)
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{
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case '<':
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nbits = 3;
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immed = GET_OP (l, RZ);
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extbits = 5;
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extu = 1;
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break;
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case '>':
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nbits = 3;
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immed = GET_OP (l, RX);
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extbits = 5;
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extu = 1;
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break;
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case '[':
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nbits = 3;
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immed = GET_OP (l, RZ);
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extbits = 6;
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extu = 1;
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break;
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case ']':
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nbits = 3;
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immed = GET_OP (l, RX);
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extbits = 6;
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extu = 1;
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break;
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case '4':
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nbits = 4;
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immed = GET_OP (l, IMM4);
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signedp = 1;
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extbits = 15;
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break;
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case '5':
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nbits = 5;
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immed = GET_OP (l, IMM5);
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info->insn_type = dis_dref;
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info->data_size = 1;
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break;
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case 'H':
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nbits = 5;
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shift = 1;
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immed = GET_OP (l, IMM5);
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info->insn_type = dis_dref;
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info->data_size = 2;
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break;
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case 'W':
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nbits = 5;
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shift = 2;
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immed = GET_OP (l, IMM5);
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if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
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&& (op->pinfo & MIPS16_INSN_READ_SP) == 0)
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for (i = 0; i < 9; i++)
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if (smask & (1 << i))
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{
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info->insn_type = dis_dref;
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info->data_size = 4;
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infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
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/* Skip over string of set bits. */
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for (j = i; smask & (2 << j); j++)
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continue;
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if (j > i)
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infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
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i = j + 1;
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}
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break;
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case 'D':
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nbits = 5;
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shift = 3;
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immed = GET_OP (l, IMM5);
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info->insn_type = dis_dref;
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info->data_size = 8;
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break;
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case 'j':
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nbits = 5;
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immed = GET_OP (l, IMM5);
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signedp = 1;
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break;
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case '6':
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nbits = 6;
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immed = GET_OP (l, IMM6);
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break;
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case '8':
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nbits = 8;
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immed = GET_OP (l, IMM8);
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break;
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case 'V':
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nbits = 8;
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shift = 2;
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immed = GET_OP (l, IMM8);
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/* FIXME: This might be lw, or it might be addiu to $sp or
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$pc. We assume it's load. */
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info->insn_type = dis_dref;
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info->data_size = 4;
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break;
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case 'C':
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nbits = 8;
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shift = 3;
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immed = GET_OP (l, IMM8);
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info->insn_type = dis_dref;
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info->data_size = 8;
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break;
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case 'U':
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nbits = 8;
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immed = GET_OP (l, IMM8);
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extu = 1;
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break;
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case 'k':
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nbits = 8;
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immed = GET_OP (l, IMM8);
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signedp = 1;
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break;
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case 'K':
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nbits = 8;
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shift = 3;
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immed = GET_OP (l, IMM8);
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signedp = 1;
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break;
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case 'p':
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nbits = 8;
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immed = GET_OP (l, IMM8);
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signedp = 1;
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pcrel = 1;
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branch = 1;
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break;
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case 'q':
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nbits = 11;
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immed = GET_OP (l, IMM11);
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signedp = 1;
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pcrel = 1;
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branch = 1;
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break;
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case 'A':
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nbits = 8;
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shift = 2;
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immed = GET_OP (l, IMM8);
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pcrel = 1;
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/* FIXME: This can be lw or la. We assume it is lw. */
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info->insn_type = dis_dref;
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info->data_size = 4;
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break;
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case 'B':
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nbits = 5;
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shift = 3;
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immed = GET_OP (l, IMM5);
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pcrel = 1;
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info->insn_type = dis_dref;
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info->data_size = 8;
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break;
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case 'E':
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nbits = 5;
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shift = 2;
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immed = GET_OP (l, IMM5);
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pcrel = 1;
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break;
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default:
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abort ();
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}
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/* Statics $ax - $a3. */
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if (nstatics == 1)
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infprintf (is, ",%s", mips_gpr_names[7]);
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else if (nstatics > 0)
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infprintf (is, ",%s-%s",
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mips_gpr_names[7 - nstatics + 1],
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mips_gpr_names[7]);
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break;
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}
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if (! use_extend)
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{
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if (signedp && immed >= (1 << (nbits - 1)))
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immed -= 1 << nbits;
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immed <<= shift;
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if ((type == '<' || type == '>' || type == '[' || type == ']')
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&& immed == 0)
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immed = 8;
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}
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else
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{
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if (extbits == 16)
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immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
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else if (extbits == 15)
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immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
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else
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immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
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immed &= (1 << extbits) - 1;
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if (! extu && immed >= (1 << (extbits - 1)))
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immed -= 1 << extbits;
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}
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if (is_offset && operand->type == OP_INT)
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{
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const struct mips_int_operand *int_op;
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if (! pcrel)
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infprintf (is, "%d", immed);
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else
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{
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bfd_vma baseaddr;
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int_op = (const struct mips_int_operand *) operand;
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info->insn_type = dis_dref;
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info->data_size = 1 << int_op->shift;
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}
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if (branch)
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{
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immed *= 2;
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baseaddr = memaddr + 2;
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}
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else if (use_extend)
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baseaddr = memaddr - 2;
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else
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{
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int status;
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bfd_byte buffer[2];
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if (operand->size == 26)
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/* In this case INSN is the first two bytes of the instruction
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and EXTEND is the second two bytes. */
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uval = ((insn & 0x1f) << 21) | ((insn & 0x3e0) << 11) | extend;
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else
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{
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/* Calculate the full field value. */
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uval = mips_extract_operand (operand, insn);
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if (use_extend)
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{
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ext_operand = decode_mips16_operand (type, TRUE);
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if (ext_operand != operand)
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{
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operand = ext_operand;
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if (operand->size == 16)
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uval |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
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else if (operand->size == 15)
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uval |= ((extend & 0xf) << 11) | (extend & 0x7f0);
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else
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uval = ((extend >> 6) & 0x1f) | (extend & 0x20);
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}
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}
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}
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baseaddr = memaddr;
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baseaddr = memaddr + 2;
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if (operand->type == OP_PCREL)
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{
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const struct mips_pcrel_operand *pcrel_op;
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/* If this instruction is in the delay slot of a jr
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instruction, the base address is the address of the
|
||||
jr instruction. If it is in the delay slot of jalr
|
||||
instruction, the base address is the address of the
|
||||
jalr instruction. This test is unreliable: we have
|
||||
no way of knowing whether the previous word is
|
||||
instruction or data. */
|
||||
status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
|
||||
info);
|
||||
if (status == 0
|
||||
&& (((info->endian == BFD_ENDIAN_BIG
|
||||
? bfd_getb16 (buffer)
|
||||
: bfd_getl16 (buffer))
|
||||
& 0xf800) == 0x1800))
|
||||
baseaddr = memaddr - 4;
|
||||
else
|
||||
{
|
||||
status = (*info->read_memory_func) (memaddr - 2, buffer,
|
||||
2, info);
|
||||
if (status == 0
|
||||
pcrel_op = (const struct mips_pcrel_operand *) operand;
|
||||
if (!pcrel_op->include_isa_bit && use_extend)
|
||||
baseaddr = memaddr - 2;
|
||||
else if (!pcrel_op->include_isa_bit)
|
||||
{
|
||||
bfd_byte buffer[2];
|
||||
|
||||
/* If this instruction is in the delay slot of a JR
|
||||
instruction, the base address is the address of the
|
||||
JR instruction. If it is in the delay slot of a JALR
|
||||
instruction, the base address is the address of the
|
||||
JALR instruction. This test is unreliable: we have
|
||||
no way of knowing whether the previous word is
|
||||
instruction or data. */
|
||||
if (info->read_memory_func (memaddr - 4, buffer, 2, info) == 0
|
||||
&& (((info->endian == BFD_ENDIAN_BIG
|
||||
? bfd_getb16 (buffer)
|
||||
: bfd_getl16 (buffer))
|
||||
& 0xf800) == 0x1800))
|
||||
baseaddr = memaddr - 4;
|
||||
else if (info->read_memory_func (memaddr - 2, buffer, 2,
|
||||
info) == 0
|
||||
&& (((info->endian == BFD_ENDIAN_BIG
|
||||
? bfd_getb16 (buffer)
|
||||
: bfd_getl16 (buffer))
|
||||
& 0xf81f) == 0xe800))
|
||||
baseaddr = memaddr - 2;
|
||||
}
|
||||
}
|
||||
info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
|
||||
if (pcrel && branch
|
||||
&& info->flavour == bfd_target_unknown_flavour)
|
||||
/* For gdb disassembler, maintain odd address. */
|
||||
info->target |= 1;
|
||||
(*info->print_address_func) (info->target, info);
|
||||
}
|
||||
}
|
||||
baseaddr = memaddr - 2;
|
||||
else
|
||||
baseaddr = memaddr;
|
||||
}
|
||||
}
|
||||
|
||||
print_insn_arg (info, state, opcode, operand, baseaddr, uval);
|
||||
break;
|
||||
|
||||
case 'a':
|
||||
case 'i':
|
||||
{
|
||||
if (! use_extend)
|
||||
extend = 0;
|
||||
l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
|
||||
if (type == 'a' && info->flavour == bfd_target_unknown_flavour)
|
||||
/* For gdb disassembler, maintain odd address. */
|
||||
l |= 1;
|
||||
}
|
||||
info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
|
||||
(*info->print_address_func) (info->target, info);
|
||||
break;
|
||||
|
||||
case 'l':
|
||||
case 'L':
|
||||
{
|
||||
int need_comma, amask, smask;
|
||||
|
||||
need_comma = 0;
|
||||
|
||||
l = GET_OP (l, IMM6);
|
||||
|
||||
amask = (l >> 3) & 7;
|
||||
|
||||
if (amask > 0 && amask < 5)
|
||||
{
|
||||
infprintf (is, "%s", mips_gpr_names[4]);
|
||||
if (amask > 1)
|
||||
infprintf (is, "-%s", mips_gpr_names[amask + 3]);
|
||||
need_comma = 1;
|
||||
}
|
||||
|
||||
smask = (l >> 1) & 3;
|
||||
if (smask == 3)
|
||||
{
|
||||
infprintf (is, "%s??", need_comma ? "," : "");
|
||||
need_comma = 1;
|
||||
}
|
||||
else if (smask > 0)
|
||||
{
|
||||
infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[16]);
|
||||
if (smask > 1)
|
||||
infprintf (is, "-%s", mips_gpr_names[smask + 15]);
|
||||
need_comma = 1;
|
||||
}
|
||||
|
||||
if (l & 1)
|
||||
{
|
||||
infprintf (is, "%s%s", need_comma ? "," : "", mips_gpr_names[31]);
|
||||
need_comma = 1;
|
||||
}
|
||||
|
||||
if (amask == 5 || amask == 6)
|
||||
{
|
||||
infprintf (is, "%s$f0", need_comma ? "," : "");
|
||||
if (amask == 6)
|
||||
infprintf (is, "-$f1");
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 'm':
|
||||
case 'M':
|
||||
/* MIPS16e save/restore. */
|
||||
{
|
||||
int need_comma = 0;
|
||||
int amask, args, statics;
|
||||
int nsreg, smask;
|
||||
int framesz;
|
||||
int i, j;
|
||||
|
||||
l = l & 0x7f;
|
||||
if (use_extend)
|
||||
l |= extend << 16;
|
||||
|
||||
amask = (l >> 16) & 0xf;
|
||||
if (amask == MIPS16_ALL_ARGS)
|
||||
{
|
||||
args = 4;
|
||||
statics = 0;
|
||||
}
|
||||
else if (amask == MIPS16_ALL_STATICS)
|
||||
{
|
||||
args = 0;
|
||||
statics = 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
args = amask >> 2;
|
||||
statics = amask & 3;
|
||||
}
|
||||
|
||||
if (args > 0) {
|
||||
infprintf (is, "%s", mips_gpr_names[4]);
|
||||
if (args > 1)
|
||||
infprintf (is, "-%s", mips_gpr_names[4 + args - 1]);
|
||||
need_comma = 1;
|
||||
}
|
||||
|
||||
framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
|
||||
if (framesz == 0 && !use_extend)
|
||||
framesz = 128;
|
||||
|
||||
infprintf (is, "%s%d", need_comma ? "," : "", framesz);
|
||||
|
||||
if (l & 0x40) /* $ra */
|
||||
infprintf (is, ",%s", mips_gpr_names[31]);
|
||||
|
||||
nsreg = (l >> 24) & 0x7;
|
||||
smask = 0;
|
||||
if (l & 0x20) /* $s0 */
|
||||
smask |= 1 << 0;
|
||||
if (l & 0x10) /* $s1 */
|
||||
smask |= 1 << 1;
|
||||
if (nsreg > 0) /* $s2-$s8 */
|
||||
smask |= ((1 << nsreg) - 1) << 2;
|
||||
|
||||
/* Find first set static reg bit. */
|
||||
for (i = 0; i < 9; i++)
|
||||
{
|
||||
if (smask & (1 << i))
|
||||
{
|
||||
infprintf (is, ",%s", mips_gpr_names[i == 8 ? 30 : (16 + i)]);
|
||||
/* Skip over string of set bits. */
|
||||
for (j = i; smask & (2 << j); j++)
|
||||
continue;
|
||||
if (j > i)
|
||||
infprintf (is, "-%s", mips_gpr_names[j == 8 ? 30 : (16 + j)]);
|
||||
i = j + 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* Statics $ax - $a3. */
|
||||
if (statics == 1)
|
||||
infprintf (is, ",%s", mips_gpr_names[7]);
|
||||
else if (statics > 0)
|
||||
infprintf (is, ",%s-%s",
|
||||
mips_gpr_names[7 - statics + 1],
|
||||
mips_gpr_names[7]);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
/* xgettext:c-format */
|
||||
infprintf (is,
|
||||
_("# internal disassembler error, "
|
||||
"unrecognised modifier (%c)"),
|
||||
type);
|
||||
abort ();
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1859,6 +1600,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
bfd_boolean use_extend;
|
||||
int extend = 0;
|
||||
const struct mips_opcode *op, *opend;
|
||||
struct mips_print_arg_state state;
|
||||
void *is = info->stream;
|
||||
|
||||
info->bytes_per_chunk = 2;
|
||||
|
|
@ -1869,6 +1611,8 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
info->target = 0;
|
||||
info->target2 = 0;
|
||||
|
||||
#define GET_OP(insn, field) \
|
||||
(((insn) >> MIPS16OP_SH_##field) & MIPS16OP_MASK_##field)
|
||||
/* Decode PLT entry's GOT slot address word. */
|
||||
if (is_mips16_plt_tail (info, memaddr))
|
||||
{
|
||||
|
|
@ -1979,6 +1723,7 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
if (op->args[0] != '\0')
|
||||
infprintf (is, "\t");
|
||||
|
||||
init_print_arg_state (&state);
|
||||
for (s = op->args; *s != '\0'; s++)
|
||||
{
|
||||
if (*s == ','
|
||||
|
|
@ -1997,8 +1742,8 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
++s;
|
||||
continue;
|
||||
}
|
||||
print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
|
||||
info);
|
||||
print_mips16_insn_arg (info, &state, op, *s, memaddr, insn,
|
||||
use_extend, extend, s[1] == '(');
|
||||
}
|
||||
|
||||
/* Figure out branch instruction type and delay slot information. */
|
||||
|
|
@ -2018,7 +1763,6 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
|
|||
return length;
|
||||
}
|
||||
}
|
||||
#undef GET_OP_S
|
||||
#undef GET_OP
|
||||
|
||||
if (use_extend)
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue