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Fix RL78 disassembly of DE+offset addressing to always show the offset, even when zero.

Browse source 
PR binutils/19159
opcodes	* rl78-decode.opc (MOV): Added offset to DE register in index
	addressing mode.
	* rl78-decode.c: Regenerate.

test	* gas/rl78/pr19159.s: New test source file.
	* gas/rl78/pr19159.d: New test case.
	* gas/rl78/rl78.exp: Run the new test.
This commit is contained in:
Vinay Kumar 2015-10-27 15:24:40 +00:00 • committed by Nick Clifton
parent 709b551853
commit c2f2875869
8 changed files with 68 additions and 25 deletions
Download patch file Download diff file Expand all files Collapse all files

7
gas/testsuite/ChangeLog
View file

@ -1,3 +1,10 @@
2015-10-27 Nick Clifton <nickc@redhat.com>
PR binutils/19159
* gas/rl78/pr19159.s: New test source file.
* gas/rl78/pr19159.d: New test case.
* gas/rl78/rl78.exp: Run the new test.
2015-10-27 Nick Clifton <nickc@redhat.com>
PR binutils/19158

2
gas/testsuite/gas/rl78/pr19157.d
View file

@ -1,5 +1,5 @@
#objdump: -d --prefix-addresses --show-raw-insn
#name: PR19157: RL78: zero offset omitted
#name: PR19157: RL78: zero offset omitted in stack based addressing
.*: +file format .*rl78.*

15
gas/testsuite/gas/rl78/pr19159.d Normal file
View file

@ -0,0 +1,15 @@
#objdump: -d --prefix-addresses --show-raw-insn
#name: PR19159: RL78: zero offset omitted in DE based addressing
.*: +file format .*rl78.*
Disassembly of section .text:
0x0+000 89[ ]+mov[ ]+a, \[de\]
0x0+001 8a 00[ ]+mov[ ]+a, \[de\+0\]
0x0+003 8a 01[ ]+mov[ ]+a, \[de\+1\]
0x0+005 99[ ]+mov[ ]+\[de], a
0x0+006 9a 00[ ]+mov[ ]+\[de\+0\], a
0x0+008 9a 01[ ]+mov[ ]+\[de\+1\], a
0x0+00a a9[ ]+movw[ ]+ax, \[de\]
0x0+00b aa 00[ ]+movw[ ]+ax, \[de\+0\]
0x0+00d aa 01[ ]+movw[ ]+ax, \[de\+1\]

13
gas/testsuite/gas/rl78/pr19159.s Normal file
View file

@ -0,0 +1,13 @@
.text
mov a, [de]
mov a, [de + 0]
mov a, [de + 1]
mov [de], a
mov [de + 0], a
mov [de + 1], a
movw ax, [de]
movw ax, [de + 0]
movw ax, [de + 1]
.end

1
gas/testsuite/gas/rl78/rl78.exp
View file

@ -21,4 +21,5 @@
if [expr [istarget "rl78-*-*"]] then {
run_dump_test "pr19157"
run_dump_test "pr19158"
run_dump_test "pr19159"
}

7
opcodes/ChangeLog
View file

@ -1,3 +1,10 @@
2015-10-27 Vinay <Vinay.G@kpit.com>
PR binutils/19159
* rl78-decode.opc (MOV): Added offset to DE register in index
addressing mode.
* rl78-decode.c: Regenerate.
2015-10-27 Vinay Kumar <vinay.g@kpit.com>
PR binutils/19158

36
opcodes/rl78-decode.c
View file

@ -2537,14 +2537,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xaf:
{
/** 0110 0001 1010 1111 xch %0, %e1 */
/** 0110 0001 1010 1111 xch %0, %ea1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x %02x\n",
"/** 0110 0001 1010 1111 xch %0, %e1 */",
"/** 0110 0001 1010 1111 xch %0, %ea1 */",
op[0], op[1]);
}
SYNTAX("xch %0, %e1");
SYNTAX("xch %0, %ea1");
#line 1210 "rl78-decode.opc"
ID(xch); DR(A); SM(DE, IMMU(1));
@ -4361,14 +4361,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0x8a:
{
/** 1000 1010 mov %0, %e1 */
/** 1000 1010 mov %0, %ea1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1000 1010 mov %0, %e1 */",
"/** 1000 1010 mov %0, %ea1 */",
op[0]);
}
SYNTAX("mov %0, %e1");
SYNTAX("mov %0, %ea1");
#line 651 "rl78-decode.opc"
ID(mov); DR(A); SM(DE, IMMU(1));
@ -4506,14 +4506,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0x9a:
{
/** 1001 1010 mov %e0, %1 */
/** 1001 1010 mov %ea0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1001 1010 mov %e0, %1 */",
"/** 1001 1010 mov %ea0, %1 */",
op[0]);
}
SYNTAX("mov %e0, %1");
SYNTAX("mov %ea0, %1");
#line 621 "rl78-decode.opc"
ID(mov); DM(DE, IMMU(1)); SR(A);
@ -4713,14 +4713,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xaa:
{
/** 1010 1010 movw %0, %e1 */
/** 1010 1010 movw %0, %ea1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1010 1010 movw %0, %e1 */",
"/** 1010 1010 movw %0, %ea1 */",
op[0]);
}
SYNTAX("movw %0, %e1");
SYNTAX("movw %0, %ea1");
#line 841 "rl78-decode.opc"
ID(mov); W(); DR(AX); SM(DE, IMMU(1));
@ -4919,14 +4919,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xba:
{
/** 1011 1010 movw %e0, %1 */
/** 1011 1010 movw %ea0, %1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1011 1010 movw %e0, %1 */",
"/** 1011 1010 movw %ea0, %1 */",
op[0]);
}
SYNTAX("movw %e0, %1");
SYNTAX("movw %ea0, %1");
#line 822 "rl78-decode.opc"
ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
@ -5083,14 +5083,14 @@ rl78_decode_opcode (unsigned long pc AU,
break;
case 0xca:
{
/** 1100 1010 mov %e0, #%1 */
/** 1100 1010 mov %ea0, #%1 */
if (trace)
{
printf ("\033[33m%s\033[0m %02x\n",
"/** 1100 1010 mov %e0, #%1 */",
"/** 1100 1010 mov %ea0, #%1 */",
op[0]);
}
SYNTAX("mov %e0, #%1");
SYNTAX("mov %ea0, #%1");
#line 618 "rl78-decode.opc"
ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));

12
opcodes/rl78-decode.opc
View file

@ -614,10 +614,10 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1001 1001 mov %e0, %1 */
ID(mov); DM(DE, 0); SR(A);
/** 1100 1010 mov %e0, #%1 */
/** 1100 1010 mov %ea0, #%1 */
ID(mov); DM(DE, IMMU(1)); SC(IMMU(1));
/** 1001 1010 mov %e0, %1 */
/** 1001 1010 mov %ea0, %1 */
ID(mov); DM(DE, IMMU(1)); SR(A);
/** 1001 1011 mov %e0, %1 */
@ -647,7 +647,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1000 1001 mov %0, %e1 */
ID(mov); DR(A); SM(DE, 0);
/** 1000 1010 mov %0, %e1 */
/** 1000 1010 mov %0, %ea1 */
ID(mov); DR(A); SM(DE, IMMU(1));
/** 1000 1011 mov %0, %e1 */
@ -818,7 +818,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1011 1001 movw %e0, %1 */
ID(mov); W(); DM(DE, 0); SR(AX);
/** 1011 1010 movw %e0, %1 */
/** 1011 1010 movw %ea0, %1 */
ID(mov); W(); DM(DE, IMMU(1)); SR(AX);
/** 1011 1011 movw %e0, %1 */
@ -837,7 +837,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 1010 1001 movw %0, %e1 */
ID(mov); W(); DR(AX); SM(DE, 0);
/** 1010 1010 movw %0, %e1 */
/** 1010 1010 movw %0, %ea1 */
ID(mov); W(); DR(AX); SM(DE, IMMU(1));
/** 1010 1011 movw %0, %e1 */
@ -1206,7 +1206,7 @@ rl78_decode_opcode (unsigned long pc AU,
/** 0110 0001 1010 1110 xch %0, %e1 */
ID(xch); DR(A); SM(DE, 0);
/** 0110 0001 1010 1111 xch %0, %e1 */
/** 0110 0001 1010 1111 xch %0, %ea1 */
ID(xch); DR(A); SM(DE, IMMU(1));
/** 0110 0001 1010 1100 xch %0, %e1 */