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Fix the encoding of the MSP430's RRUX instruction.

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PR target/19561
opcdoe	* msp430-dis.c (print_insn_msp430): Add a special case for
	decoding an RRC instruction with the ZC bit set in the extension
	word.

include	* opcode/msp430.h (IGNORE_CARRY_BIT): New define.
	(RRUX): Synthesise using case 2 rather than 7.

gas	* config/tc-msp430.c (msp430_operands): Remove case 7.  Use case 2
	to handle encoding of RRUX instruction.
	* testsuite/gas/msp430/msp430x.s: Add more tests of the extended
	shift instructions.
	* testsuite/gas/msp430/msp430x.d: Update expected disassembly.
This commit is contained in:
Nick Clifton 2016-02-04 09:55:10 +00:00
parent 1b18aa1e79
commit c1d9289fef
8 changed files with 81 additions and 94 deletions
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9
opcodes/msp430-dis.c
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@ -1102,7 +1102,7 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
}
else if (extension_word)
{
if (extension_word & (1 << 6))
if (extension_word & BYTE_OPERATION)
bc = ".w";
else
{
@ -1181,7 +1181,12 @@ print_insn_msp430 (bfd_vma addr, disassemble_info *info)
prin (stream, "rpt #%d { ", (extension_word & 0xf) + 1);
}
if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
/* Special case: RRC with an extension word and the ZC bit set is actually RRU. */
if (extension_word
&& (extension_word & IGNORE_CARRY_BIT)
&& strcmp (opcode->name, "rrc") == 0)
(*prin) (stream, "rrux%s", bc);
else if (extension_word && opcode->name[strlen (opcode->name) - 1] != 'x')
(*prin) (stream, "%sx%s", opcode->name, bc);
else
(*prin) (stream, "%s%s", opcode->name, bc);