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Implement ARC NPS-400 Ultra Ip and Miscellaneous instructions.

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opcodes	* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
	* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, F_NPS_M, F_NPS_CORE, F_NPS_ALL.
	(insert_nps_misc_imm_offset): New function.
	(extract_nps_misc imm_offset): New function.
	(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
	(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.

include * opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.

gas     * testsuite/gas/arc/nps400-12.s: New file.
        * testsuite/gas/arc/nps400-12.d: New file.
This commit is contained in:
Rinat Zelig 2017-03-27 11:14:30 +01:00 • committed by Nick Clifton
parent cf31b44f3c
commit c0c31e91ad
8 changed files with 759 additions and 356 deletions
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5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2017-03-27 Rinat Zelig <rinat@mellanox.com>
* testsuite/gas/arc/nps400-12.s: New file.
* testsuite/gas/arc/nps400-12.d: New file.
2017-03-24 Thomas preud'homme <thomas.preudhomme@arm.com>
* config/tc-arm.: (md_begin): Set selected_cpu from *mcpu_cpu_opt when

59
gas/testsuite/gas/arc/nps400-12.d Normal file
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@ -0,0 +1,59 @@
#as: -mcpu=nps400
#objdump: -dr
.*: +file format .*arc.*
Disassembly of section .text:
[0-9a-f]+ <.*>:
0: 3815 0042 whash r2,\[cm:r0\],r1
4: 3b15 0385 whash r5,\[cm:r3\],r14
8: 3815 007e whash 0,\[cm:r0\],r1
c: 3b15 03be whash 0,\[cm:r3\],r14
10: 3855 01c2 whash r2,\[cm:r0\],0x7
14: 3855 01fe whash 0,\[cm:r0\],0x7
18: 3855 0002 whash r2,\[cm:r0\],0x40
1c: 3855 003e whash 0,\[cm:r0\],0x40
20: 4822 4000 mcmp r0,\[cm:r0\],\[cm:r1\],r1
24: 4822 6000 mcmp\.s r0,\[cm:r0\],\[cm:r1\],r1
28: 4822 4080 mcmp\.m r0,\[cm:r0\],\[cm:r1\],r1
2c: 4822 6080 mcmp\.s\.m r0,\[cm:r0\],\[cm:r1\],r1
30: 4822 0000 mcmp r0,\[cm:r0,r0\],\[cm:r1\],r1
34: 4822 2000 mcmp\.s r0,\[cm:r0,r0\],\[cm:r1\],r1
38: 4822 0080 mcmp\.m r0,\[cm:r0,r0\],\[cm:r1\],r1
3c: 4822 2080 mcmp\.s\.m r0,\[cm:r0,r0\],\[cm:r1\],r1
40: 4822 4100 mcmp r0,\[cm:r0,0x4\],\[cm:r1\],r1
44: 4822 6100 mcmp\.s r0,\[cm:r0,0x4\],\[cm:r1\],r1
48: 4822 4180 mcmp\.m r0,\[cm:r0,0x4\],\[cm:r1\],r1
4c: 4822 6180 mcmp\.s\.m r0,\[cm:r0,0x4\],\[cm:r1\],r1
50: 4822 4200 mcmp r0,\[cm:r0,0x8\],\[cm:r1\],r1
54: 4822 4300 mcmp r0,\[cm:r0,0xc\],\[cm:r1\],r1
58: 4822 c004 mcmp r0,\[cm:r0\],\[cm:r1\],0x4
5c: 4822 e004 mcmp\.s r0,\[cm:r0\],\[cm:r1\],0x4
60: 4822 c084 mcmp\.m r0,\[cm:r0\],\[cm:r1\],0x4
64: 4822 e088 mcmp\.s\.m r0,\[cm:r0\],\[cm:r1\],0x8
68: 4822 c07f mcmp r0,\[cm:r0\],\[cm:r1\],0x7f
6c: 4822 c204 mcmp r0,\[cm:r0,0x8\],\[cm:r1\],0x4
70: 4822 e204 mcmp\.s r0,\[cm:r0,0x8\],\[cm:r1\],0x4
74: 4822 c284 mcmp\.m r0,\[cm:r0,0x8\],\[cm:r1\],0x4
78: 4822 e284 mcmp\.s\.m r0,\[cm:r0,0x8\],\[cm:r1\],0x4
7c: 4822 802e mcmp r0,\[cm:r0,r0\],\[cm:r1\],0x2e
80: 4822 a046 mcmp\.s r0,\[cm:r0,r0\],\[cm:r1\],0x46
84: 4822 80c8 mcmp\.m r0,\[cm:r0,r0\],\[cm:r1\],0x48
88: 4822 a0fd mcmp\.s\.m r0,\[cm:r0,r0\],\[cm:r1\],0x7d
8c: 3856 003e asri 0,r0
90: 3856 007e asri\.core 0,r0
94: 3856 00be asri\.clsr 0,r0
98: 3856 00fe asri\.all 0,r0
9c: 3856 013e asri\.gic 0,r0
a0: 3856 017e rspi\.gic 0,r0
a4: 385b 003e wkup 0,r0
a8: 385b 013e wkup\.cl
ac: 3a2f 0024 getsti r2,\[cm:r0\]
b0: 3e2f 7024 getsti 0,\[cm:r0\]
000000b4 <label>:
b4: 3a2f 0025 getrtc r2,\[cm:r0\]
b8: 3e2f 7025 getrtc 0,\[cm:r0\]
bc: 07f8 ffd5 bnj -8
c0: 07f4 ffd7 bnm -12
c4: 07f0 ffd8 bnt -16

71
gas/testsuite/gas/arc/nps400-12.s Normal file
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@ -0,0 +1,71 @@
.text
; Miscellaneous
; whash
whash r2,[cm:r0],r1
whash r5,[cm:r3],r14
whash 0,[cm:r0],r1
whash 0,[cm:r3],r14
whash r2,[cm:r0],7
whash 0,[cm:r0],7
whash r2,[cm:r0],64
whash 0,[cm:r0],64
; mcmp
mcmp r0,[cm:r0],[cm:r1],r1
mcmp.s r0,[cm:r0],[cm:r1],r1
mcmp.m r0,[cm:r0],[cm:r1],r1
mcmp.s.m r0,[cm:r0],[cm:r1],r1
mcmp r0,[cm:r0,r0],[cm:r1],r1
mcmp.s r0,[cm:r0,r0],[cm:r1],r1
mcmp.m r0,[cm:r0,r0],[cm:r1],r1
mcmp.s.m r0,[cm:r0,r0],[cm:r1],r1
mcmp r0,[cm:r0,4],[cm:r1],r1
mcmp.s r0,[cm:r0,4],[cm:r1],r1
mcmp.m r0,[cm:r0,4],[cm:r1],r1
mcmp.s.m r0,[cm:r0,4],[cm:r1],r1
mcmp r0,[cm:r0,8],[cm:r1],r1
mcmp r0,[cm:r0,12],[cm:r1],r1
mcmp r0,[cm:r0],[cm:r1],4
mcmp.s r0,[cm:r0],[cm:r1],4
mcmp.m r0,[cm:r0],[cm:r1],4
mcmp.s.m r0,[cm:r0],[cm:r1],8
mcmp r0,[cm:r0],[cm:r1],127
mcmp r0,[cm:r0,8],[cm:r1],4
mcmp.s r0,[cm:r0,8],[cm:r1],4
mcmp.m r0,[cm:r0,8],[cm:r1],4
mcmp.s.m r0,[cm:r0,8],[cm:r1],4
mcmp r0,[cm:r0,r0],[cm:r1],46
mcmp.s r0,[cm:r0,r0],[cm:r1],70
mcmp.m r0,[cm:r0,r0],[cm:r1],72
mcmp.s.m r0,[cm:r0,r0],[cm:r1],125
;asri
asri 0, r0
asri.core 0, r0
asri.clsr 0,r0
asri.all 0,r0
asri.gic 0,r0
rspi.gic 0,r0
;wkup
wkup 0,r0
wkup.cl
;getsti
getsti r2,[cm:r0]
getsti 0,[cm:r0]
label:
;getrtc
getrtc r2,[cm:r0]
getrtc 0,[cm:r0]
;b<cc>
bnj label
bnm label
bnt label

4
include/ChangeLog
View file

@ -1,3 +1,7 @@
2017-03-27 Rinat Zelig <rinat@mellanox.com>
* opcode/arc.h (insn_class_t): Add ULTRAIP and MISC class.
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* opcode/s390.h (S390_INSTR_FLAG_VX2): Remove.

14
include/opcode/arc.h
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@ -68,6 +68,7 @@ typedef enum
LOGICAL,
LOOP,
MEMORY,
MISC,
MOVE,
MPY,
NET,
@ -77,6 +78,7 @@ typedef enum
PUSH,
STORE,
SUB,
ULTRAIP,
XY
} insn_class_t;
@ -141,7 +143,7 @@ typedef enum
struct arc_opcode
{
/* The opcode name. */
const char *name;
const char * name;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
@ -371,7 +373,7 @@ extern const unsigned arc_NToperand;
struct arc_flag_operand
{
/* The flag name. */
const char *name;
const char * name;
/* The flag code. */
unsigned code;
@ -453,13 +455,13 @@ struct arc_operand_operation
struct arc_pseudo_insn
{
/* Mnemonic for pseudo/alias insn. */
const char *mnemonic_p;
const char * mnemonic_p;
/* Mnemonic for real instruction. */
const char *mnemonic_r;
const char * mnemonic_r;
/* Flag that will have to be added (if any). */
const char *flag_r;
const char * flag_r;
/* Amount of operands. */
unsigned operand_cnt;
@ -486,7 +488,7 @@ struct arc_aux_reg
insn_subclass_t subclass;
/* Register name. */
const char *name;
const char * name;
/* Size of the string. */
size_t length;

10
opcodes/ChangeLog
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@ -1,3 +1,13 @@
2017-03-27 Rinat Zelig <rinat@mellanox.com>
* arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
* arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
F_NPS_M, F_NPS_CORE, F_NPS_ALL.
(insert_nps_misc_imm_offset): New function.
(extract_nps_misc imm_offset): New function.
(arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
(arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* s390-mkopc.c (main): Remove vx2 check.

72
opcodes/arc-nps400-tbl.h
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@ -905,6 +905,78 @@ XLDST_LIKE("xst", 0xe)
/* cp32<.na> [xd:src1,src2,src2,src2], [cm:src2] */
{ "cp32", 0x48078181, 0xf80ffdff, ARC_OPCODE_ARC700, DMA, NPS400, { BRAKET, NPS_XD, COLON, NPS_DPI_SRC1_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_NPS_NA }},
/* Ultra IP Instructions. */
/* uip<.na> dst, [cm:src2], [cm:src1] */
{ "uip", 0x480740a2, 0xf81fc1e3, ARC_OPCODE_ARC700, ULTRAIP, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup }, { C_NPS_NA }},
/* uip<.na> dst, [cm:src2], [cm:src1], src2 */
{ "uip", 0x480700a2, 0xf81fc1e3, ARC_OPCODE_ARC700, ULTRAIP, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_NA }},
/* Miscellaneous Instructions. */
/* whash dst,[cm:src1],src2 */
{ "whash", 0x38150000, 0xf8ff0000, ARC_OPCODE_ARC700, MISC, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RC }, { 0 }},
/* whash 0,[cm:src1],src2 */
{ "whash", 0x3815003e, 0xf8ff003f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, RC }, { 0 }},
/* whash dst,[cm:src1],size */
{ "whash", 0x38550000, 0xf8ff0000, ARC_OPCODE_ARC700, MISC, NPS400, { RA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, NPS_WHASH_SIZE }, { 0 }},
/* whash 0,[cm:src1],size */
{ "whash", 0x3855003e, 0xf8ff003f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RB, BRAKETdup, NPS_WHASH_SIZE }, { 0 }},
/* mcmp<.s><.m> dst,[cm:src1],[cm:src2],src2 */
{ "mcmp", 0x48024000, 0xf81fdf7f, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
/* mcmp<.s><.m> dst,[cm:src1,src1],[cm:src2],src2 */
{ "mcmp", 0x48020000, 0xf81fdf7f, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
/* mcmp.<s><.m> dst,[cm:src1,offset],[cm:src2],src2 */
{ "mcmp", 0x48024000, 0xf81fc000, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B,
NPS_MISC_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_R_SRC2_3B }, { C_NPS_SR, C_NPS_M }},
/* mcmp<.s><.m> dst,[cm:src1],[cm: src2],size */
{ "mcmp", 0x4802c000, 0xf81fcf00, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
/* mcmp<.s><.m> dst,[cm:src1,offset],[cm:src2],size */
{ "mcmp", 0x4802c000, 0xf81fc000, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B,
NPS_MISC_IMM_OFFSET, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
/* mcmp<.s><.m> dst,[cm:src1,src1],[cm:src2],size */
{ "mcmp", 0x48028000, 0xf81fdf00, ARC_OPCODE_ARC700, MISC, NPS400, { NPS_R_DST_3B, BRAKET, NPS_CM, COLON, NPS_DPI_SRC1_3B, NPS_DPI_SRC1_3B, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_R_SRC2_3B, BRAKETdup, NPS_MISC_IMM_SIZE }, { C_NPS_SR, C_NPS_M }},
#define ASRI_LIKE(SUBOP2, FLAG) \
{ "asri", (0x3856003e | (SUBOP2 << 6)), 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, RB }, { FLAG }},
ASRI_LIKE (0x0, 0)
ASRI_LIKE (0x1, C_NPS_CORE)
ASRI_LIKE (0x2, C_NPS_CLSR)
ASRI_LIKE (0x3, C_NPS_ALL)
ASRI_LIKE (0x4, C_NPS_GIC)
/* rspi.gic 0,src1 */
{ "rspi", 0x3856017e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, RB }, { C_NPS_RSPI_GIC }},
/* wkup.cl */
{ "wkup", 0x385b013e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { 0 }, { C_NPS_CL }},
/* wkup 0, src2 */
{ "wkup", 0x385b003e, 0xf8ff8fff, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, RC }, { 0 }},
/* getsti dst,[cm:src2] */
{ "getsti", 0x382f0024, 0xf8ff803f, ARC_OPCODE_ARC700, MISC, NPS400, { RB, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
/* getsti 0, [cm:src2] */
{ "getsti", 0x3e2f7024, 0xfffff03f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
/* getrtc dst,[cm:src2] */
{ "getrtc", 0x382f0025, 0xf8ff803f, ARC_OPCODE_ARC700, MISC, NPS400, { RB, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
/* getrtc 0, [cm:src2] */
{ "getrtc", 0x3e2f7025, 0xfffff03f, ARC_OPCODE_ARC700, MISC, NPS400, { ZA, BRAKET, NPS_CM, COLON, RC, BRAKETdup }, { 0 }},
/* Atomic Operations. */
/* exc<.di><.f> a,a,[xa:b] */

880
opcodes/arc-opc.c
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