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Namespace cleanup for the tic4x target. Replace s/c4x/tic4x/ and s/c3x/tic3x/. 2003 copyright update

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This commit is contained in:
Svein Seldal 2003-04-04 08:15:15 +00:00
parent 36018d2e5a
commit be33c5dd4d
19 changed files with 576 additions and 538 deletions
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8
bfd/ChangeLog
View file

@ -1,3 +1,11 @@
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
* archures.c: Namespace cleanup. Rename bfd_mach_c3x to
bfd_mach_tic3x and bfd_mach_c4x to bfd_mach_tic4x
* bfd-in2.h: Regenerate
* coff-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/
* cpu-tic4x.c: Ditto
2003-04-03 Nick Clifton <nickc@redhat.com> 2003-04-03 Nick Clifton <nickc@redhat.com>
* peXXigen.c (_bfd_XXi_swap_scnhdr_out): Compute ps and ss * peXXigen.c (_bfd_XXi_swap_scnhdr_out): Compute ps and ss

4
bfd/archures.c
View file

@ -241,8 +241,8 @@ DESCRIPTION
. bfd_arch_w65, {* WDC 65816 *} . bfd_arch_w65, {* WDC 65816 *}
. bfd_arch_tic30, {* Texas Instruments TMS320C30 *} . bfd_arch_tic30, {* Texas Instruments TMS320C30 *}
. bfd_arch_tic4x, {* Texas Instruments TMS320C3X/4X *} . bfd_arch_tic4x, {* Texas Instruments TMS320C3X/4X *}
.#define bfd_mach_c3x 30 .#define bfd_mach_tic3x 30
.#define bfd_mach_c4x 40 .#define bfd_mach_tic4x 40
. bfd_arch_tic54x, {* Texas Instruments TMS320C54X *} . bfd_arch_tic54x, {* Texas Instruments TMS320C54X *}
. bfd_arch_tic80, {* TI TMS320c80 (MVP) *} . bfd_arch_tic80, {* TI TMS320c80 (MVP) *}
. bfd_arch_v850, {* NEC V850 *} . bfd_arch_v850, {* NEC V850 *}

4
bfd/bfd-in2.h
View file

@ -1707,8 +1707,8 @@ enum bfd_architecture
bfd_arch_w65, /* WDC 65816 */ bfd_arch_w65, /* WDC 65816 */
bfd_arch_tic30, /* Texas Instruments TMS320C30 */ bfd_arch_tic30, /* Texas Instruments TMS320C30 */
bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */ bfd_arch_tic4x, /* Texas Instruments TMS320C3X/4X */
#define bfd_mach_c3x 30 #define bfd_mach_tic3x 30
#define bfd_mach_c4x 40 #define bfd_mach_tic4x 40
bfd_arch_tic54x, /* Texas Instruments TMS320C54X */ bfd_arch_tic54x, /* Texas Instruments TMS320C54X */
bfd_arch_tic80, /* TI TMS320c80 (MVP) */ bfd_arch_tic80, /* TI TMS320c80 (MVP) */
bfd_arch_v850, /* NEC V850 */ bfd_arch_v850, /* NEC V850 */

15
bfd/coff-tic4x.c
View file

@ -1,6 +1,7 @@
/* BFD back-end for TMS320C4X coff binaries. /* BFD back-end for TMS320C4X coff binaries.
Copyright 1996, 1997, 1998, 1999, 2000, 2002 Copyright 1996, 1997, 1998, 1999, 2000, 2002, 2003
Free Software Foundation, Inc. Free Software Foundation, Inc.
Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz) Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
This file is part of BFD, the Binary File Descriptor library. This file is part of BFD, the Binary File Descriptor library.
@ -365,7 +366,7 @@ static const bfd_coff_backend_data ticoff1_swap_table =
/* TI COFF v0, DOS tools (little-endian headers). */ /* TI COFF v0, DOS tools (little-endian headers). */
const bfd_target tic4x_coff0_vec = const bfd_target tic4x_coff0_vec =
{ {
"coff0-c4x", /* Name. */ "coff0-tic4x", /* Name. */
bfd_target_coff_flavour, bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */ BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */ BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
@ -409,7 +410,7 @@ const bfd_target tic4x_coff0_vec =
/* TI COFF v0, SPARC tools (big-endian headers). */ /* TI COFF v0, SPARC tools (big-endian headers). */
const bfd_target tic4x_coff0_beh_vec = const bfd_target tic4x_coff0_beh_vec =
{ {
"coff0-beh-c4x", /* Name. */ "coff0-beh-tic4x", /* Name. */
bfd_target_coff_flavour, bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */ BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */ BFD_ENDIAN_BIG, /* Header byte order is big. */
@ -454,7 +455,7 @@ const bfd_target tic4x_coff0_beh_vec =
/* TI COFF v1, DOS tools (little-endian headers). */ /* TI COFF v1, DOS tools (little-endian headers). */
const bfd_target tic4x_coff1_vec = const bfd_target tic4x_coff1_vec =
{ {
"coff1-c4x", /* Name. */ "coff1-tic4x", /* Name. */
bfd_target_coff_flavour, bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */ BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */ BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
@ -499,7 +500,7 @@ const bfd_target tic4x_coff1_vec =
/* TI COFF v1, SPARC tools (big-endian headers). */ /* TI COFF v1, SPARC tools (big-endian headers). */
const bfd_target tic4x_coff1_beh_vec = const bfd_target tic4x_coff1_beh_vec =
{ {
"coff1-beh-c4x", /* Name. */ "coff1-beh-tic4x", /* Name. */
bfd_target_coff_flavour, bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */ BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */ BFD_ENDIAN_BIG, /* Header byte order is big. */
@ -544,7 +545,7 @@ const bfd_target tic4x_coff1_beh_vec =
/* TI COFF v2, TI DOS tools output (little-endian headers). */ /* TI COFF v2, TI DOS tools output (little-endian headers). */
const bfd_target tic4x_coff2_vec = const bfd_target tic4x_coff2_vec =
{ {
"coff2-c4x", /* Name. */ "coff2-tic4x", /* Name. */
bfd_target_coff_flavour, bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */ BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */ BFD_ENDIAN_LITTLE, /* Header byte order is little (DOS tools). */
@ -589,7 +590,7 @@ const bfd_target tic4x_coff2_vec =
/* TI COFF v2, TI SPARC tools output (big-endian headers). */ /* TI COFF v2, TI SPARC tools output (big-endian headers). */
const bfd_target tic4x_coff2_beh_vec = const bfd_target tic4x_coff2_beh_vec =
{ {
"coff2-beh-c4x", /* Name. */ "coff2-beh-tic4x", /* Name. */
bfd_target_coff_flavour, bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* Data byte order is little. */ BFD_ENDIAN_LITTLE, /* Data byte order is little. */
BFD_ENDIAN_BIG, /* Header byte order is big. */ BFD_ENDIAN_BIG, /* Header byte order is big. */

22
bfd/cpu-tic4x.c
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@ -1,5 +1,5 @@
/* bfd back-end for TMS320C[34]x support /* bfd back-end for TMS320C[34]x support
Copyright 1996, 1997, 2002 Free Software Foundation, Inc. Copyright 1996, 1997, 2002, 2003 Free Software Foundation, Inc.
Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz) Contributed by Michael Hayes (m.hayes@elec.canterbury.ac.nz)
@ -23,12 +23,12 @@
#include "sysdep.h" #include "sysdep.h"
#include "libbfd.h" #include "libbfd.h"
static bfd_boolean c4x_scan static bfd_boolean tic4x_scan
PARAMS ((const struct bfd_arch_info *, const char * )); PARAMS ((const struct bfd_arch_info *, const char * ));
static bfd_boolean static bfd_boolean
c4x_scan (info, string) tic4x_scan (info, string)
const struct bfd_arch_info *info; const struct bfd_arch_info *info;
const char *string; const char *string;
{ {
@ -42,9 +42,9 @@ c4x_scan (info, string)
return FALSE; return FALSE;
if (*string == '3') if (*string == '3')
return (info->mach == bfd_mach_c3x); return (info->mach == bfd_mach_tic3x);
else if (*string == '4') else if (*string == '4')
return info->mach == bfd_mach_c4x; return info->mach == bfd_mach_tic4x;
return FALSE; return FALSE;
} }
@ -56,13 +56,13 @@ const bfd_arch_info_type bfd_tic3x_arch =
32, /* 32 bits in an address. */ 32, /* 32 bits in an address. */
32, /* 32 bits in a byte. */ 32, /* 32 bits in a byte. */
bfd_arch_tic4x, bfd_arch_tic4x,
bfd_mach_c3x, /* Machine number. */ bfd_mach_tic3x, /* Machine number. */
"c3x", /* Architecture name. */ "tic3x", /* Architecture name. */
"tms320c3x", /* Printable name. */ "tms320c3x", /* Printable name. */
0, /* Alignment power. */ 0, /* Alignment power. */
FALSE, /* Not the default architecture. */ FALSE, /* Not the default architecture. */
bfd_default_compatible, bfd_default_compatible,
c4x_scan, tic4x_scan,
0 0
}; };
@ -72,13 +72,13 @@ const bfd_arch_info_type bfd_tic4x_arch =
32, /* 32 bits in an address. */ 32, /* 32 bits in an address. */
32, /* 32 bits in a byte. */ 32, /* 32 bits in a byte. */
bfd_arch_tic4x, bfd_arch_tic4x,
bfd_mach_c4x, /* Machine number. */ bfd_mach_tic4x, /* Machine number. */
"c4x", /* Architecture name. */ "tic4x", /* Architecture name. */
"tms320c4x", /* Printable name. */ "tms320c4x", /* Printable name. */
0, /* Alignment power. */ 0, /* Alignment power. */
TRUE, /* The default architecture. */ TRUE, /* The default architecture. */
bfd_default_compatible, bfd_default_compatible,
c4x_scan, tic4x_scan,
&bfd_tic3x_arch, &bfd_tic3x_arch,
}; };

8
gas/ChangeLog
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@ -1,3 +1,11 @@
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
* config/obj-coff.h (TARGET_FORMAT): Namespace cleanup, changed
default tic4x target format to 'coff2-tic4x'.
* config/tc-tic4x.c: Namespace cleanup. Replace s/c4x/tic4x/ and
s/c3x/tic3x/
* config/tc-tic4x.h: Ditto
2003-04-03 Nick Clifton <nickc@redhat.com> 2003-04-03 Nick Clifton <nickc@redhat.com>
* NEWS: Mention support for Xtensa architecture. * NEWS: Mention support for Xtensa architecture.

2
gas/config/obj-coff.h
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@ -159,7 +159,7 @@
#ifdef TC_TIC4X #ifdef TC_TIC4X
#include "coff/tic4x.h" #include "coff/tic4x.h"
#define TARGET_FORMAT "coff2-c4x" #define TARGET_FORMAT "coff2-tic4x"
#endif #endif
#ifdef TC_TIC54X #ifdef TC_TIC54X

616
gas/config/tc-tic4x.c
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File diff suppressed because it is too large Load diff

24
gas/config/tc-tic4x.h
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@ -1,5 +1,5 @@
/* tc-tic4x.h -- Assemble for the Texas TMS320C[34]X. /* tc-tic4x.h -- Assemble for the Texas TMS320C[34]X.
Copyright (C) 1997, 2002 Free Software Foundation. Copyright (C) 1997, 2002, 2003 Free Software Foundation.
Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
@ -20,7 +20,7 @@
the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#define TC_TIC4X #define TC_TIC4X
#define C4X #define TIC4X
#ifndef BFD_ASSEMBLER #ifndef BFD_ASSEMBLER
#error TMS320C4x requires BFD_ASSEMBLER #error TMS320C4x requires BFD_ASSEMBLER
@ -80,21 +80,21 @@
/* Accept numbers with a suffix, e.g. 0ffffh, 1010b. */ /* Accept numbers with a suffix, e.g. 0ffffh, 1010b. */
#define NUMBERS_WITH_SUFFIX 1 #define NUMBERS_WITH_SUFFIX 1
extern int c4x_unrecognized_line PARAMS ((int)); extern int tic4x_unrecognized_line PARAMS ((int));
#define tc_unrecognized_line(c) c4x_unrecognized_line (c) #define tc_unrecognized_line(c) tic4x_unrecognized_line (c)
#define md_number_to_chars number_to_chars_littleendian #define md_number_to_chars number_to_chars_littleendian
extern int c4x_do_align PARAMS ((int, const char *, int, int)); extern int tic4x_do_align PARAMS ((int, const char *, int, int));
#define md_do_align(n,fill,len,max,label) if( c4x_do_align (n,fill,len,max) ) goto label; #define md_do_align(n,fill,len,max,label) if( tic4x_do_align (n,fill,len,max) ) goto label;
/* Start of line hook to remove parallel instruction operator || */ /* Start of line hook to remove parallel instruction operator || */
extern void c4x_start_line PARAMS ((void)); extern void tic4x_start_line PARAMS ((void));
#define md_start_line_hook() c4x_start_line() #define md_start_line_hook() tic4x_start_line()
extern void c4x_cleanup PARAMS ((void)); extern void tic4x_cleanup PARAMS ((void));
#define md_cleanup() c4x_cleanup() #define md_cleanup() tic4x_cleanup()
extern void c4x_end PARAMS ((void)); extern void tic4x_end PARAMS ((void));
#define md_end() c4x_end() #define md_end() tic4x_end()

7
include/ChangeLog
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@ -1,3 +1,10 @@
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
* coff/tic4x.h: Namespace cleanup. Replace s/c4x/tic4x
and s/c3x/tic3x/
* coff/tc-tic4x.h: Ditto
* opcode/tic4x.h: Ditto
2003-04-02 Bob Wilson <bob.wilson@acm.org> 2003-04-02 Bob Wilson <bob.wilson@acm.org>
* xtensa-config.h: Remove comment indicating that this is a * xtensa-config.h: Remove comment indicating that this is a

6
include/coff/tic4x.h
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@ -1,7 +1,7 @@
/* TI COFF information for Texas Instruments TMS320C4X/C3X. /* TI COFF information for Texas Instruments TMS320C4X/C3X.
This file customizes the settings in coff/ti.h. This file customizes the settings in coff/ti.h.
Copyright 2002 Free Software Foundation, Inc. Copyright 2002, 2003 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by
@ -31,12 +31,12 @@
#define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC #define TICOFF_DEFAULT_MAGIC TICOFF2MAGIC
#define TICOFF_TARGET_MACHINE_GET(FLAGS) \ #define TICOFF_TARGET_MACHINE_GET(FLAGS) \
(((FLAGS) & F_VERS) ? bfd_mach_c4x : bfd_mach_c3x) (((FLAGS) & F_VERS) ? bfd_mach_tic4x : bfd_mach_tic3x)
#define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \ #define TICOFF_TARGET_MACHINE_SET(FLAGSP, MACHINE) \
do \ do \
{ \ { \
if ((MACHINE) == bfd_mach_c4x) \ if ((MACHINE) == bfd_mach_tic4x) \
*(FLAGSP) |= F_VERS; \ *(FLAGSP) |= F_VERS; \
} \ } \
while (0) while (0)

58
include/opcode/tic4x.h
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@ -1,6 +1,6 @@
/* Table of opcodes for the Texas Instruments TMS320C[34]X family. /* Table of opcodes for the Texas Instruments TMS320C[34]X family.
Copyright (c) 2002 Free Software Foundation. Copyright (C) 2002, 2003 Free Software Foundation.
Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
@ -19,8 +19,8 @@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/ */
#define IS_CPU_C3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33) #define IS_CPU_TIC3X(v) ((v) == 30 || (v) == 31 || (v) == 32 || (v) == 33)
#define IS_CPU_C4X(v) ((v) == 0 || (v) == 40 || (v) == 44) #define IS_CPU_TIC4X(v) ((v) == 0 || (v) == 40 || (v) == 44)
/* Define some bitfield extraction/insertion macros. */ /* Define some bitfield extraction/insertion macros. */
#define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l)))) #define EXTR(inst, m, l) ((inst) << (31 - (m)) >> (31 - ((m) - (l))))
@ -50,22 +50,22 @@ c4x_reg_t;
#define REG_IF REG_IIE /* C3x only */ #define REG_IF REG_IIE /* C3x only */
#define REG_IOF REG_IIF /* C3x only */ #define REG_IOF REG_IIF /* C3x only */
#define C3X_REG_MAX REG_RC #define TIC3X_REG_MAX REG_RC
#define C4X_REG_MAX REG_TVTP #define TIC4X_REG_MAX REG_TVTP
/* Register table size including C4x expansion regs. */ /* Register table size including C4x expansion regs. */
#define REG_TABLE_SIZE (C4X_REG_MAX + 1) #define REG_TABLE_SIZE (TIC4X_REG_MAX + 1)
struct c4x_register struct tic4x_register
{ {
char * name; char * name;
unsigned long regno; unsigned long regno;
}; };
typedef struct c4x_register c4x_register_t; typedef struct tic4x_register tic4x_register_t;
/* We could store register synonyms here. */ /* We could store register synonyms here. */
static const c4x_register_t c3x_registers[] = static const tic4x_register_t tic3x_registers[] =
{ {
{"f0", REG_R0}, {"f0", REG_R0},
{"r0", REG_R0}, {"r0", REG_R0},
@ -106,10 +106,10 @@ static const c4x_register_t c3x_registers[] =
{"", 0} {"", 0}
}; };
const unsigned int c3x_num_registers = (((sizeof c3x_registers) / (sizeof c3x_registers[0])) - 1); const unsigned int tic3x_num_registers = (((sizeof tic3x_registers) / (sizeof tic3x_registers[0])) - 1);
/* Define C4x registers in addition to C3x registers. */ /* Define C4x registers in addition to C3x registers. */
static const c4x_register_t c4x_registers[] = static const tic4x_register_t tic4x_registers[] =
{ {
{"die", REG_DIE}, /* Clobbers C3x REG_IE */ {"die", REG_DIE}, /* Clobbers C3x REG_IE */
{"iie", REG_IIE}, /* Clobbers C3x REG_IF */ {"iie", REG_IIE}, /* Clobbers C3x REG_IF */
@ -127,19 +127,19 @@ static const c4x_register_t c4x_registers[] =
{"", 0} {"", 0}
}; };
const unsigned int c4x_num_registers = (((sizeof c4x_registers) / (sizeof c4x_registers[0])) - 1); const unsigned int tic4x_num_registers = (((sizeof tic4x_registers) / (sizeof tic4x_registers[0])) - 1);
struct c4x_cond struct tic4x_cond
{ {
char * name; char * name;
unsigned long cond; unsigned long cond;
}; };
typedef struct c4x_cond c4x_cond_t; typedef struct tic4x_cond tic4x_cond_t;
/* Define conditional branch/load suffixes. Put desired form for /* Define conditional branch/load suffixes. Put desired form for
disassembler last. */ disassembler last. */
static const c4x_cond_t c4x_conds[] = static const tic4x_cond_t tic4x_conds[] =
{ {
{ "u", 0x00 }, { "u", 0x00 },
{ "c", 0x01 }, { "lo", 0x01 }, { "c", 0x01 }, { "lo", 0x01 },
@ -167,22 +167,22 @@ static const c4x_cond_t c4x_conds[] =
{ "", 0x0} { "", 0x0}
}; };
const unsigned int num_conds = (((sizeof c4x_conds) / (sizeof c4x_conds[0])) - 1); const unsigned int tic4x_num_conds = (((sizeof tic4x_conds) / (sizeof tic4x_conds[0])) - 1);
struct c4x_indirect struct tic4x_indirect
{ {
char * name; char * name;
unsigned long modn; unsigned long modn;
}; };
typedef struct c4x_indirect c4x_indirect_t; typedef struct tic4x_indirect tic4x_indirect_t;
/* Define indirect addressing modes where: /* Define indirect addressing modes where:
d displacement (signed) d displacement (signed)
y ir0 y ir0
z ir1 */ z ir1 */
static const c4x_indirect_t c4x_indirects[] = static const tic4x_indirect_t tic4x_indirects[] =
{ {
{ "*+a(d)", 0x00 }, { "*+a(d)", 0x00 },
{ "*-a(d)", 0x01 }, { "*-a(d)", 0x01 },
@ -216,12 +216,12 @@ static const c4x_indirect_t c4x_indirects[] =
{ "", 0x0} { "", 0x0}
}; };
#define C3X_MODN_MAX 0x19 #define TIC3X_MODN_MAX 0x19
const unsigned int c4x_num_indirects = (((sizeof c4x_indirects) / (sizeof c4x_indirects[0])) - 1); const unsigned int tic4x_num_indirects = (((sizeof tic4x_indirects) / (sizeof tic4x_indirects[0])) - 1);
/* Instruction template. */ /* Instruction template. */
struct c4x_inst struct tic4x_inst
{ {
char * name; char * name;
unsigned long opcode; unsigned long opcode;
@ -230,7 +230,7 @@ struct c4x_inst
unsigned long oplevel; unsigned long oplevel;
}; };
typedef struct c4x_inst c4x_inst_t; typedef struct tic4x_inst tic4x_inst_t;
/* Opcode infix /* Opcode infix
B condition 16--20 U,C,Z,LO,HI, etc. B condition 16--20 U,C,Z,LO,HI, etc.
@ -278,8 +278,8 @@ typedef struct c4x_inst c4x_inst_t;
Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP Z expansion reg (C4x) 16--20 [Z] - IVTP, TVTP
*/ */
#define C4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */ #define TIC4X_OPERANDS_MAX 7 /* Max number of operands for an inst. */
#define C4X_NAME_MAX 16 /* Max number of chars in parallel name. */ #define TIC4X_NAME_MAX 16 /* Max number of chars in parallel name. */
/* Define the instruction level */ /* Define the instruction level */
#define OP_C3X 0x1 /* C30 support - supported by all */ #define OP_C3X 0x1 /* C30 support - supported by all */
@ -873,8 +873,8 @@ typedef struct c4x_inst c4x_inst_t;
*/ */
/* Define c3x opcodes for assembler and disassembler. */ /* Define tic4x opcodes for assembler and disassembler. */
static const c4x_inst_t c4x_insts[] = static const tic4x_inst_t tic4x_insts[] =
{ {
/* Put synonyms after the desired forms in table so that they get /* Put synonyms after the desired forms in table so that they get
overwritten in the lookup table. The disassembler will thus overwritten in the lookup table. The disassembler will thus
@ -1070,10 +1070,10 @@ static const c4x_inst_t c4x_insts[] =
TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ), TC_CLASS_INSN( "xor", 0x08000000, OP_C3X ),
QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ), QC_CLASS_INSN( "xor", "sti", 0xee000000, OP_C3X ),
/* Dummy entry, not included in c3x_num_insts. This /* Dummy entry, not included in tic4x_num_insts. This
lets code examine entry i + 1 without checking lets code examine entry i + 1 without checking
if we've run off the end of the table. */ if we've run off the end of the table. */
{ "", 0x0, 0x00, "", 0 } { "", 0x0, 0x00, "", 0 }
}; };
const unsigned int c4x_num_insts = (((sizeof c4x_insts) / (sizeof c4x_insts[0])) - 1); const unsigned int tic4x_num_insts = (((sizeof tic4x_insts) / (sizeof tic4x_insts[0])) - 1);

8
ld/ChangeLog
View file

@ -1,3 +1,11 @@
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
* emulparams/tic3xcoff.sh (SCRIPT_NAME): Namespace
cleanup. Replace s/c4x/tic4x and s/c3x/tic3x/
* emulparams/tic3xcoff_onchip.sh: Ditto
* emulparams/tic4xcoff.sh: Ditto
* scripttempl/tic4xcoff.sc: Ditto
2003-04-03 Nick Clifton <nickc@redhat.com> 2003-04-03 Nick Clifton <nickc@redhat.com>
* NEWS: Mention support for Xtensa architecture. * NEWS: Mention support for Xtensa architecture.

6
ld/emulparams/tic3xcoff.sh
View file

@ -1,6 +1,6 @@
SCRIPT_NAME=tic4xcoff SCRIPT_NAME=tic4xcoff
OUTPUT_FORMAT="coff2-c4x" OUTPUT_FORMAT="coff2-tic4x"
OUTPUT_ARCH="c3x" OUTPUT_ARCH="tic3x"
ARCH=c3x ARCH=tic3x
TEMPLATE_NAME=ticoff TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x OUTPUT_FORMAT_TEMPLATE=tic4x

6
ld/emulparams/tic3xcoff_onchip.sh
View file

@ -1,7 +1,7 @@
SCRIPT_NAME=tic4xcoff SCRIPT_NAME=tic4xcoff
OUTPUT_FORMAT="coff2-c4x" OUTPUT_FORMAT="coff2-tic4x"
OUTPUT_ARCH="c3x" OUTPUT_ARCH="tic3x"
ARCH=c3x ARCH=tic3x
TEMPLATE_NAME=ticoff TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x OUTPUT_FORMAT_TEMPLATE=tic4x
ONCHIP=yes ONCHIP=yes

6
ld/emulparams/tic4xcoff.sh
View file

@ -1,6 +1,6 @@
SCRIPT_NAME=tic4xcoff SCRIPT_NAME=tic4xcoff
OUTPUT_FORMAT="coff2-c4x" OUTPUT_FORMAT="coff2-tic4x"
OUTPUT_ARCH="c4x" OUTPUT_ARCH="tic4x"
ARCH=c4x ARCH=tic4x
TEMPLATE_NAME=ticoff TEMPLATE_NAME=ticoff
OUTPUT_FORMAT_TEMPLATE=tic4x OUTPUT_FORMAT_TEMPLATE=tic4x

4
ld/scripttempl/tic4xcoff.sc
View file

@ -31,8 +31,8 @@
# This emulation assumes config 7. # This emulation assumes config 7.
case $OUTPUT_ARCH in case $OUTPUT_ARCH in
c3x) OUTPUT_ARCHNAME="TMS320C3x" ;; tic3x) OUTPUT_ARCHNAME="TMS320C3x" ;;
c4x) OUTPUT_ARCHNAME="TMS320C4x" ;; tic4x) OUTPUT_ARCHNAME="TMS320C4x" ;;
esac esac
case $ONCHIP in case $ONCHIP in

5
opcodes/ChangeLog
View file

@ -1,3 +1,8 @@
2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com>
* tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and
s/c3x/tic3x/
2003-04-01 Nick Clifton <nickc@redhat.com> 2003-04-01 Nick Clifton <nickc@redhat.com>
* arm-dis.c: Remove presence of (r) and (tm) symbols. * arm-dis.c: Remove presence of (r) and (tm) symbols.

305
opcodes/tic4x-dis.c
View file

@ -1,6 +1,6 @@
/* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils. /* Print instructions for the Texas TMS320C[34]X, for GDB and GNU Binutils.
Copyright 2002 Free Software Foundation, Inc. Copyright 2002, 2003 Free Software Foundation, Inc.
Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz) Contributed by Michael P. Hayes (m.hayes@elec.canterbury.ac.nz)
@ -23,10 +23,10 @@
#include "dis-asm.h" #include "dis-asm.h"
#include "opcode/tic4x.h" #include "opcode/tic4x.h"
#define C4X_DEBUG 0 #define TIC4X_DEBUG 0
#define C4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */ #define TIC4X_HASH_SIZE 11 /* 11 (bits) and above should give unique entries. */
#define C4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */ #define TIC4X_SPESOP_SIZE 8 /* Max 8. ops for special instructions */
typedef enum typedef enum
{ {
@ -43,49 +43,49 @@ typedef enum
{ {
INDIRECT_SHORT, INDIRECT_SHORT,
INDIRECT_LONG, INDIRECT_LONG,
INDIRECT_C4X INDIRECT_TIC4X
} }
indirect_t; indirect_t;
static int c4x_version = 0; static int tic4x_version = 0;
static int c4x_dp = 0; static int tic4x_dp = 0;
static int c4x_pc_offset static int tic4x_pc_offset
PARAMS ((unsigned int)); PARAMS ((unsigned int));
static int c4x_print_char static int tic4x_print_char
PARAMS ((struct disassemble_info *, char)); PARAMS ((struct disassemble_info *, char));
static int c4x_print_str static int tic4x_print_str
PARAMS ((struct disassemble_info *, char *)); PARAMS ((struct disassemble_info *, char *));
static int c4x_print_register static int tic4x_print_register
PARAMS ((struct disassemble_info *, unsigned long)); PARAMS ((struct disassemble_info *, unsigned long));
static int c4x_print_addr static int tic4x_print_addr
PARAMS ((struct disassemble_info *, unsigned long)); PARAMS ((struct disassemble_info *, unsigned long));
static int c4x_print_relative static int tic4x_print_relative
PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long)); PARAMS ((struct disassemble_info *, unsigned long, long, unsigned long));
void c4x_print_ftoa void tic4x_print_ftoa
PARAMS ((unsigned int, FILE *, fprintf_ftype)); PARAMS ((unsigned int, FILE *, fprintf_ftype));
static int c4x_print_direct static int tic4x_print_direct
PARAMS ((struct disassemble_info *, unsigned long)); PARAMS ((struct disassemble_info *, unsigned long));
static int c4x_print_immed static int tic4x_print_immed
PARAMS ((struct disassemble_info *, immed_t, unsigned long)); PARAMS ((struct disassemble_info *, immed_t, unsigned long));
static int c4x_print_cond static int tic4x_print_cond
PARAMS ((struct disassemble_info *, unsigned int)); PARAMS ((struct disassemble_info *, unsigned int));
static int c4x_print_indirect static int tic4x_print_indirect
PARAMS ((struct disassemble_info *, indirect_t, unsigned long)); PARAMS ((struct disassemble_info *, indirect_t, unsigned long));
static int c4x_print_op static int tic4x_print_op
PARAMS ((struct disassemble_info *, unsigned long, c4x_inst_t *, unsigned long)); PARAMS ((struct disassemble_info *, unsigned long, tic4x_inst_t *, unsigned long));
static void c4x_hash_opcode_special static void tic4x_hash_opcode_special
PARAMS ((c4x_inst_t **, const c4x_inst_t *)); PARAMS ((tic4x_inst_t **, const tic4x_inst_t *));
static void c4x_hash_opcode static void tic4x_hash_opcode
PARAMS ((c4x_inst_t **, c4x_inst_t **, const c4x_inst_t *, unsigned long)); PARAMS ((tic4x_inst_t **, tic4x_inst_t **, const tic4x_inst_t *, unsigned long));
static int c4x_disassemble static int tic4x_disassemble
PARAMS ((unsigned long, unsigned long, struct disassemble_info *)); PARAMS ((unsigned long, unsigned long, struct disassemble_info *));
int print_insn_tic4x int print_insn_tic4x
PARAMS ((bfd_vma, struct disassemble_info *)); PARAMS ((bfd_vma, struct disassemble_info *));
static int static int
c4x_pc_offset (op) tic4x_pc_offset (op)
unsigned int op; unsigned int op;
{ {
/* Determine the PC offset for a C[34]x instruction. /* Determine the PC offset for a C[34]x instruction.
@ -143,7 +143,7 @@ c4x_pc_offset (op)
} }
static int static int
c4x_print_char (info, ch) tic4x_print_char (info, ch)
struct disassemble_info * info; struct disassemble_info * info;
char ch; char ch;
{ {
@ -153,7 +153,7 @@ c4x_print_char (info, ch)
} }
static int static int
c4x_print_str (info, str) tic4x_print_str (info, str)
struct disassemble_info *info; struct disassemble_info *info;
char *str; char *str;
{ {
@ -163,28 +163,28 @@ c4x_print_str (info, str)
} }
static int static int
c4x_print_register (info, regno) tic4x_print_register (info, regno)
struct disassemble_info *info; struct disassemble_info *info;
unsigned long regno; unsigned long regno;
{ {
static c4x_register_t **registertable = NULL; static tic4x_register_t **registertable = NULL;
unsigned int i; unsigned int i;
if (registertable == NULL) if (registertable == NULL)
{ {
registertable = (c4x_register_t **) registertable = (tic4x_register_t **)
xmalloc (sizeof (c4x_register_t *) * REG_TABLE_SIZE); xmalloc (sizeof (tic4x_register_t *) * REG_TABLE_SIZE);
for (i = 0; i < c3x_num_registers; i++) for (i = 0; i < tic3x_num_registers; i++)
registertable[c3x_registers[i].regno] = (void *)&c3x_registers[i]; registertable[tic3x_registers[i].regno] = (void *)&tic3x_registers[i];
if (IS_CPU_C4X (c4x_version)) if (IS_CPU_TIC4X (tic4x_version))
{ {
/* Add C4x additional registers, overwriting /* Add C4x additional registers, overwriting
any C3x registers if necessary. */ any C3x registers if necessary. */
for (i = 0; i < c4x_num_registers; i++) for (i = 0; i < tic4x_num_registers; i++)
registertable[c4x_registers[i].regno] = (void *)&c4x_registers[i]; registertable[tic4x_registers[i].regno] = (void *)&tic4x_registers[i];
} }
} }
if ((int) regno > (IS_CPU_C4X (c4x_version) ? C4X_REG_MAX : C3X_REG_MAX)) if ((int) regno > (IS_CPU_TIC4X (tic4x_version) ? TIC4X_REG_MAX : TIC3X_REG_MAX))
return 0; return 0;
if (info != NULL) if (info != NULL)
(*info->fprintf_func) (info->stream, "%s", registertable[regno]->name); (*info->fprintf_func) (info->stream, "%s", registertable[regno]->name);
@ -192,7 +192,7 @@ c4x_print_register (info, regno)
} }
static int static int
c4x_print_addr (info, addr) tic4x_print_addr (info, addr)
struct disassemble_info *info; struct disassemble_info *info;
unsigned long addr; unsigned long addr;
{ {
@ -202,24 +202,24 @@ c4x_print_addr (info, addr)
} }
static int static int
c4x_print_relative (info, pc, offset, opcode) tic4x_print_relative (info, pc, offset, opcode)
struct disassemble_info *info; struct disassemble_info *info;
unsigned long pc; unsigned long pc;
long offset; long offset;
unsigned long opcode; unsigned long opcode;
{ {
return c4x_print_addr (info, pc + offset + c4x_pc_offset (opcode)); return tic4x_print_addr (info, pc + offset + tic4x_pc_offset (opcode));
} }
static int static int
c4x_print_direct (info, arg) tic4x_print_direct (info, arg)
struct disassemble_info *info; struct disassemble_info *info;
unsigned long arg; unsigned long arg;
{ {
if (info != NULL) if (info != NULL)
{ {
(*info->fprintf_func) (info->stream, "@"); (*info->fprintf_func) (info->stream, "@");
c4x_print_addr (info, arg + (c4x_dp << 16)); tic4x_print_addr (info, arg + (tic4x_dp << 16));
} }
return 1; return 1;
} }
@ -227,7 +227,7 @@ c4x_print_direct (info, arg)
/* FIXME: make the floating point stuff not rely on host /* FIXME: make the floating point stuff not rely on host
floating point arithmetic. */ floating point arithmetic. */
void void
c4x_print_ftoa (val, stream, pfunc) tic4x_print_ftoa (val, stream, pfunc)
unsigned int val; unsigned int val;
FILE *stream; FILE *stream;
fprintf_ftype pfunc; fprintf_ftype pfunc;
@ -253,7 +253,7 @@ c4x_print_ftoa (val, stream, pfunc)
} }
static int static int
c4x_print_immed (info, type, arg) tic4x_print_immed (info, type, arg)
struct disassemble_info *info; struct disassemble_info *info;
immed_t type; immed_t type;
unsigned long arg; unsigned long arg;
@ -312,18 +312,18 @@ c4x_print_immed (info, type, arg)
} }
static int static int
c4x_print_cond (info, cond) tic4x_print_cond (info, cond)
struct disassemble_info *info; struct disassemble_info *info;
unsigned int cond; unsigned int cond;
{ {
static c4x_cond_t **condtable = NULL; static tic4x_cond_t **condtable = NULL;
unsigned int i; unsigned int i;
if (condtable == NULL) if (condtable == NULL)
{ {
condtable = (c4x_cond_t **)xmalloc (sizeof (c4x_cond_t *) * 32); condtable = (tic4x_cond_t **)xmalloc (sizeof (tic4x_cond_t *) * 32);
for (i = 0; i < num_conds; i++) for (i = 0; i < tic4x_num_conds; i++)
condtable[c4x_conds[i].cond] = (void *)&c4x_conds[i]; condtable[tic4x_conds[i].cond] = (void *)&tic4x_conds[i];
} }
if (cond > 31 || condtable[cond] == NULL) if (cond > 31 || condtable[cond] == NULL)
return 0; return 0;
@ -333,7 +333,7 @@ c4x_print_cond (info, cond)
} }
static int static int
c4x_print_indirect (info, type, arg) tic4x_print_indirect (info, type, arg)
struct disassemble_info *info; struct disassemble_info *info;
indirect_t type; indirect_t type;
unsigned long arg; unsigned long arg;
@ -348,7 +348,7 @@ c4x_print_indirect (info, type, arg)
disp = 1; disp = 1;
switch(type) switch(type)
{ {
case INDIRECT_C4X: /* *+ARn(disp) */ case INDIRECT_TIC4X: /* *+ARn(disp) */
disp = EXTRU (arg, 7, 3); disp = EXTRU (arg, 7, 3);
aregno = EXTRU (arg, 2, 0) + REG_AR0; aregno = EXTRU (arg, 2, 0) + REG_AR0;
modn = 0; modn = 0;
@ -366,29 +366,30 @@ c4x_print_indirect (info, type, arg)
return 0; return 0;
break; break;
default: default:
abort (); (*info->fprintf_func)(info->stream, "# internal error: Unknown indirect type %d", type);
return 0;
} }
if (modn > C3X_MODN_MAX) if (modn > TIC3X_MODN_MAX)
return 0; return 0;
a = c4x_indirects[modn].name; a = tic4x_indirects[modn].name;
while (*a) while (*a)
{ {
switch (*a) switch (*a)
{ {
case 'a': case 'a':
c4x_print_register (info, aregno); tic4x_print_register (info, aregno);
break; break;
case 'd': case 'd':
c4x_print_immed (info, IMMED_UINT, disp); tic4x_print_immed (info, IMMED_UINT, disp);
break; break;
case 'y': case 'y':
c4x_print_str (info, "ir0"); tic4x_print_str (info, "ir0");
break; break;
case 'z': case 'z':
c4x_print_str (info, "ir1"); tic4x_print_str (info, "ir1");
break; break;
default: default:
c4x_print_char (info, *a); tic4x_print_char (info, *a);
break; break;
} }
a++; a++;
@ -397,10 +398,10 @@ c4x_print_indirect (info, type, arg)
} }
static int static int
c4x_print_op (info, instruction, p, pc) tic4x_print_op (info, instruction, p, pc)
struct disassemble_info *info; struct disassemble_info *info;
unsigned long instruction; unsigned long instruction;
c4x_inst_t *p; tic4x_inst_t *p;
unsigned long pc; unsigned long pc;
{ {
int val; int val;
@ -414,18 +415,18 @@ c4x_print_op (info, instruction, p, pc)
switch (*s) switch (*s)
{ {
case 'B': case 'B':
if (! c4x_print_cond (info, EXTRU (instruction, 20, 16))) if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16)))
return 0; return 0;
break; break;
case 'C': case 'C':
if (! c4x_print_cond (info, EXTRU (instruction, 27, 23))) if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23)))
return 0; return 0;
break; break;
case '_': case '_':
parallel = s + 1; /* Skip past `_' in name */ parallel = s + 1; /* Skip past `_' in name */
break; break;
default: default:
c4x_print_char (info, *s); tic4x_print_char (info, *s);
break; break;
} }
s++; s++;
@ -434,45 +435,45 @@ c4x_print_op (info, instruction, p, pc)
/* Print arguments. */ /* Print arguments. */
s = p->args; s = p->args;
if (*s) if (*s)
c4x_print_char (info, ' '); tic4x_print_char (info, ' ');
while (*s) while (*s)
{ {
switch (*s) switch (*s)
{ {
case '*': /* indirect 0--15 */ case '*': /* indirect 0--15 */
if (! c4x_print_indirect (info, INDIRECT_LONG, if (! tic4x_print_indirect (info, INDIRECT_LONG,
EXTRU (instruction, 15, 0))) EXTRU (instruction, 15, 0)))
return 0; return 0;
break; break;
case '#': /* only used for ldp, ldpk */ case '#': /* only used for ldp, ldpk */
c4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0));
break; break;
case '@': /* direct 0--15 */ case '@': /* direct 0--15 */
c4x_print_direct (info, EXTRU (instruction, 15, 0)); tic4x_print_direct (info, EXTRU (instruction, 15, 0));
break; break;
case 'A': /* address register 24--22 */ case 'A': /* address register 24--22 */
if (! c4x_print_register (info, EXTRU (instruction, 24, 22) + if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) +
REG_AR0)) REG_AR0))
return 0; return 0;
break; break;
case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb case 'B': /* 24-bit unsigned int immediate br(d)/call/rptb
address 0--23. */ address 0--23. */
if (IS_CPU_C4X (c4x_version)) if (IS_CPU_TIC4X (tic4x_version))
c4x_print_relative (info, pc, EXTRS (instruction, 23, 0), tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0),
p->opcode); p->opcode);
else else
c4x_print_addr (info, EXTRU (instruction, 23, 0)); tic4x_print_addr (info, EXTRU (instruction, 23, 0));
break; break;
case 'C': /* indirect (short C4x) 0--7 */ case 'C': /* indirect (short C4x) 0--7 */
if (! IS_CPU_C4X (c4x_version)) if (! IS_CPU_TIC4X (tic4x_version))
return 0; return 0;
if (! c4x_print_indirect (info, INDIRECT_C4X, if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
EXTRU (instruction, 7, 0))) EXTRU (instruction, 7, 0)))
return 0; return 0;
break; break;
@ -483,26 +484,26 @@ c4x_print_op (info, instruction, p, pc)
case 'E': /* register 0--7 */ case 'E': /* register 0--7 */
case 'e': case 'e':
if (! c4x_print_register (info, EXTRU (instruction, 7, 0))) if (! tic4x_print_register (info, EXTRU (instruction, 7, 0)))
return 0; return 0;
break; break;
case 'F': /* 16-bit float immediate 0--15 */ case 'F': /* 16-bit float immediate 0--15 */
c4x_print_immed (info, IMMED_SFLOAT, tic4x_print_immed (info, IMMED_SFLOAT,
EXTRU (instruction, 15, 0)); EXTRU (instruction, 15, 0));
break; break;
case 'i': /* Extended indirect 0--7 */ case 'i': /* Extended indirect 0--7 */
if ( EXTRU (instruction, 7, 5) == 7 ) if ( EXTRU (instruction, 7, 5) == 7 )
{ {
if( !c4x_print_register (info, EXTRU (instruction, 4, 0)) ) if( !tic4x_print_register (info, EXTRU (instruction, 4, 0)) )
return 0; return 0;
break; break;
} }
/* Fallthrough */ /* Fallthrough */
case 'I': /* indirect (short) 0--7 */ case 'I': /* indirect (short) 0--7 */
if (! c4x_print_indirect (info, INDIRECT_SHORT, if (! tic4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 7, 0))) EXTRU (instruction, 7, 0)))
return 0; return 0;
break; break;
@ -510,106 +511,106 @@ c4x_print_op (info, instruction, p, pc)
case 'j': /* Extended indirect 8--15 */ case 'j': /* Extended indirect 8--15 */
if ( EXTRU (instruction, 15, 13) == 7 ) if ( EXTRU (instruction, 15, 13) == 7 )
{ {
if( !c4x_print_register (info, EXTRU (instruction, 12, 8)) ) if( !tic4x_print_register (info, EXTRU (instruction, 12, 8)) )
return 0; return 0;
break; break;
} }
case 'J': /* indirect (short) 8--15 */ case 'J': /* indirect (short) 8--15 */
if (! c4x_print_indirect (info, INDIRECT_SHORT, if (! tic4x_print_indirect (info, INDIRECT_SHORT,
EXTRU (instruction, 15, 8))) EXTRU (instruction, 15, 8)))
return 0; return 0;
break; break;
case 'G': /* register 8--15 */ case 'G': /* register 8--15 */
case 'g': case 'g':
if (! c4x_print_register (info, EXTRU (instruction, 15, 8))) if (! tic4x_print_register (info, EXTRU (instruction, 15, 8)))
return 0; return 0;
break; break;
case 'H': /* register 16--18 */ case 'H': /* register 16--18 */
if (! c4x_print_register (info, EXTRU (instruction, 18, 16))) if (! tic4x_print_register (info, EXTRU (instruction, 18, 16)))
return 0; return 0;
break; break;
case 'K': /* register 19--21 */ case 'K': /* register 19--21 */
if (! c4x_print_register (info, EXTRU (instruction, 21, 19))) if (! tic4x_print_register (info, EXTRU (instruction, 21, 19)))
return 0; return 0;
break; break;
case 'L': /* register 22--24 */ case 'L': /* register 22--24 */
if (! c4x_print_register (info, EXTRU (instruction, 24, 22))) if (! tic4x_print_register (info, EXTRU (instruction, 24, 22)))
return 0; return 0;
break; break;
case 'M': /* register 22--22 */ case 'M': /* register 22--22 */
c4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2); tic4x_print_register (info, EXTRU (instruction, 22, 22) + REG_R2);
break; break;
case 'N': /* register 23--23 */ case 'N': /* register 23--23 */
c4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0); tic4x_print_register (info, EXTRU (instruction, 23, 23) + REG_R0);
break; break;
case 'O': /* indirect (short C4x) 8--15 */ case 'O': /* indirect (short C4x) 8--15 */
if (! IS_CPU_C4X (c4x_version)) if (! IS_CPU_TIC4X (tic4x_version))
return 0; return 0;
if (! c4x_print_indirect (info, INDIRECT_C4X, if (! tic4x_print_indirect (info, INDIRECT_TIC4X,
EXTRU (instruction, 15, 8))) EXTRU (instruction, 15, 8)))
return 0; return 0;
break; break;
case 'P': /* displacement 0--15 (used by Bcond and BcondD) */ case 'P': /* displacement 0--15 (used by Bcond and BcondD) */
c4x_print_relative (info, pc, EXTRS (instruction, 15, 0), tic4x_print_relative (info, pc, EXTRS (instruction, 15, 0),
p->opcode); p->opcode);
break; break;
case 'Q': /* register 0--15 */ case 'Q': /* register 0--15 */
case 'q': case 'q':
if (! c4x_print_register (info, EXTRU (instruction, 15, 0))) if (! tic4x_print_register (info, EXTRU (instruction, 15, 0)))
return 0; return 0;
break; break;
case 'R': /* register 16--20 */ case 'R': /* register 16--20 */
case 'r': case 'r':
if (! c4x_print_register (info, EXTRU (instruction, 20, 16))) if (! tic4x_print_register (info, EXTRU (instruction, 20, 16)))
return 0; return 0;
break; break;
case 'S': /* 16-bit signed immediate 0--15 */ case 'S': /* 16-bit signed immediate 0--15 */
c4x_print_immed (info, IMMED_SINT, tic4x_print_immed (info, IMMED_SINT,
EXTRS (instruction, 15, 0)); EXTRS (instruction, 15, 0));
break; break;
case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */ case 'T': /* 5-bit signed immediate 16--20 (C4x stik) */
if (! IS_CPU_C4X (c4x_version)) if (! IS_CPU_TIC4X (tic4x_version))
return 0; return 0;
if (! c4x_print_immed (info, IMMED_SUINT, if (! tic4x_print_immed (info, IMMED_SUINT,
EXTRU (instruction, 20, 16))) EXTRU (instruction, 20, 16)))
return 0; return 0;
break; break;
case 'U': /* 16-bit unsigned int immediate 0--15 */ case 'U': /* 16-bit unsigned int immediate 0--15 */
c4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0)); tic4x_print_immed (info, IMMED_SUINT, EXTRU (instruction, 15, 0));
break; break;
case 'V': /* 5/9-bit unsigned vector 0--4/8 */ case 'V': /* 5/9-bit unsigned vector 0--4/8 */
c4x_print_immed (info, IMMED_SUINT, tic4x_print_immed (info, IMMED_SUINT,
IS_CPU_C4X (c4x_version) ? IS_CPU_TIC4X (tic4x_version) ?
EXTRU (instruction, 8, 0) : EXTRU (instruction, 8, 0) :
EXTRU (instruction, 4, 0) & ~0x20); EXTRU (instruction, 4, 0) & ~0x20);
break; break;
case 'W': /* 8-bit signed immediate 0--7 */ case 'W': /* 8-bit signed immediate 0--7 */
if (! IS_CPU_C4X (c4x_version)) if (! IS_CPU_TIC4X (tic4x_version))
return 0; return 0;
c4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0)); tic4x_print_immed (info, IMMED_SINT, EXTRS (instruction, 7, 0));
break; break;
case 'X': /* expansion register 4--0 */ case 'X': /* expansion register 4--0 */
val = EXTRU (instruction, 4, 0) + REG_IVTP; val = EXTRU (instruction, 4, 0) + REG_IVTP;
if (val < REG_IVTP || val > REG_TVTP) if (val < REG_IVTP || val > REG_TVTP)
return 0; return 0;
if (! c4x_print_register (info, val)) if (! tic4x_print_register (info, val))
return 0; return 0;
break; break;
@ -617,7 +618,7 @@ c4x_print_op (info, instruction, p, pc)
val = EXTRU (instruction, 20, 16); val = EXTRU (instruction, 20, 16);
if (val < REG_AR0 || val > REG_SP) if (val < REG_AR0 || val > REG_SP)
return 0; return 0;
if (! c4x_print_register (info, val)) if (! tic4x_print_register (info, val))
return 0; return 0;
break; break;
@ -625,22 +626,22 @@ c4x_print_op (info, instruction, p, pc)
val = EXTRU (instruction, 20, 16) + REG_IVTP; val = EXTRU (instruction, 20, 16) + REG_IVTP;
if (val < REG_IVTP || val > REG_TVTP) if (val < REG_IVTP || val > REG_TVTP)
return 0; return 0;
if (! c4x_print_register (info, val)) if (! tic4x_print_register (info, val))
return 0; return 0;
break; break;
case '|': /* Parallel instruction */ case '|': /* Parallel instruction */
c4x_print_str (info, " || "); tic4x_print_str (info, " || ");
c4x_print_str (info, parallel); tic4x_print_str (info, parallel);
c4x_print_char (info, ' '); tic4x_print_char (info, ' ');
break; break;
case ';': case ';':
c4x_print_char (info, ','); tic4x_print_char (info, ',');
break; break;
default: default:
c4x_print_char (info, *s); tic4x_print_char (info, *s);
break; break;
} }
s++; s++;
@ -649,13 +650,13 @@ c4x_print_op (info, instruction, p, pc)
} }
static void static void
c4x_hash_opcode_special (optable_special, inst) tic4x_hash_opcode_special (optable_special, inst)
c4x_inst_t **optable_special; tic4x_inst_t **optable_special;
const c4x_inst_t *inst; const tic4x_inst_t *inst;
{ {
int i; int i;
for( i=0; i<C4X_SPESOP_SIZE; i++ ) for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
if( optable_special[i] != NULL if( optable_special[i] != NULL
&& optable_special[i]->opcode == inst->opcode ) && optable_special[i]->opcode == inst->opcode )
{ {
@ -664,7 +665,7 @@ c4x_hash_opcode_special (optable_special, inst)
return; return;
} }
for( i=0; i<C4X_SPESOP_SIZE; i++ ) for( i=0; i<TIC4X_SPESOP_SIZE; i++ )
if( optable_special[i] == NULL ) if( optable_special[i] == NULL )
{ {
/* Add the new opcode */ /* Add the new opcode */
@ -673,32 +674,32 @@ c4x_hash_opcode_special (optable_special, inst)
} }
/* This should never occur. This happens if the number of special /* This should never occur. This happens if the number of special
instructions exceeds C4X_SPESOP_SIZE. Please increase the variable instructions exceeds TIC4X_SPESOP_SIZE. Please increase the variable
of this variable */ of this variable */
#if C4X_DEBUG #if TIC4X_DEBUG
printf("optable_special[] is full, please increase C4X_SPESOP_SIZE!\n"); printf("optable_special[] is full, please increase TIC4X_SPESOP_SIZE!\n");
#endif #endif
} }
static void static void
c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel) tic4x_hash_opcode (optable, optable_special, inst, tic4x_oplevel)
c4x_inst_t **optable; tic4x_inst_t **optable;
c4x_inst_t **optable_special; tic4x_inst_t **optable_special;
const c4x_inst_t *inst; const tic4x_inst_t *inst;
const unsigned long c4x_oplevel; const unsigned long tic4x_oplevel;
{ {
int j; int j;
int opcode = inst->opcode >> (32 - C4X_HASH_SIZE); int opcode = inst->opcode >> (32 - TIC4X_HASH_SIZE);
int opmask = inst->opmask >> (32 - C4X_HASH_SIZE); int opmask = inst->opmask >> (32 - TIC4X_HASH_SIZE);
/* Use a C4X_HASH_SIZE bit index as a hash index. We should /* Use a TIC4X_HASH_SIZE bit index as a hash index. We should
have unique entries so there's no point having a linked list have unique entries so there's no point having a linked list
for each entry? */ for each entry? */
for (j = opcode; j < opmask; j++) for (j = opcode; j < opmask; j++)
if ( (j & opmask) == opcode if ( (j & opmask) == opcode
&& inst->oplevel & c4x_oplevel ) && inst->oplevel & tic4x_oplevel )
{ {
#if C4X_DEBUG #if TIC4X_DEBUG
/* We should only have collisions for synonyms like /* We should only have collisions for synonyms like
ldp for ldi. */ ldp for ldi. */
if (optable[j] != NULL) if (optable[j] != NULL)
@ -710,13 +711,13 @@ c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
hash. Store them in a special-list, that will handle full hash. Store them in a special-list, that will handle full
32-bit INSN, not only the first 11-bit (or so). */ 32-bit INSN, not only the first 11-bit (or so). */
if ( optable[j] != NULL if ( optable[j] != NULL
&& inst->opmask & ~(opmask << (32 - C4X_HASH_SIZE)) ) && inst->opmask & ~(opmask << (32 - TIC4X_HASH_SIZE)) )
{ {
/* Add the instruction already on the list */ /* Add the instruction already on the list */
c4x_hash_opcode_special(optable_special, optable[j]); tic4x_hash_opcode_special(optable_special, optable[j]);
/* Add the new instruction */ /* Add the new instruction */
c4x_hash_opcode_special(optable_special, inst); tic4x_hash_opcode_special(optable_special, inst);
} }
optable[j] = (void *)inst; optable[j] = (void *)inst;
@ -730,67 +731,67 @@ c4x_hash_opcode (optable, optable_special, inst, c4x_oplevel)
The function returns the length of this instruction in words. */ The function returns the length of this instruction in words. */
static int static int
c4x_disassemble (pc, instruction, info) tic4x_disassemble (pc, instruction, info)
unsigned long pc; unsigned long pc;
unsigned long instruction; unsigned long instruction;
struct disassemble_info *info; struct disassemble_info *info;
{ {
static c4x_inst_t **optable = NULL; static tic4x_inst_t **optable = NULL;
static c4x_inst_t **optable_special = NULL; static tic4x_inst_t **optable_special = NULL;
c4x_inst_t *p; tic4x_inst_t *p;
int i; int i;
unsigned long c4x_oplevel; unsigned long tic4x_oplevel;
c4x_version = info->mach; tic4x_version = info->mach;
c4x_oplevel = (IS_CPU_C4X (c4x_version)) ? OP_C4X : 0; tic4x_oplevel = (IS_CPU_TIC4X (tic4x_version)) ? OP_C4X : 0;
c4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH; tic4x_oplevel |= OP_C3X|OP_LPWR|OP_IDLE2|OP_ENH;
if (optable == NULL) if (optable == NULL)
{ {
optable = (c4x_inst_t **) optable = (tic4x_inst_t **)
xcalloc (sizeof (c4x_inst_t *), (1 << C4X_HASH_SIZE)); xcalloc (sizeof (tic4x_inst_t *), (1 << TIC4X_HASH_SIZE));
optable_special = (c4x_inst_t **) optable_special = (tic4x_inst_t **)
xcalloc (sizeof (c4x_inst_t *), C4X_SPESOP_SIZE ); xcalloc (sizeof (tic4x_inst_t *), TIC4X_SPESOP_SIZE );
/* Install opcodes in reverse order so that preferred /* Install opcodes in reverse order so that preferred
forms overwrite synonyms. */ forms overwrite synonyms. */
for (i = c4x_num_insts - 1; i >= 0; i--) for (i = tic4x_num_insts - 1; i >= 0; i--)
c4x_hash_opcode (optable, optable_special, &c4x_insts[i], c4x_oplevel); tic4x_hash_opcode (optable, optable_special, &tic4x_insts[i], tic4x_oplevel);
/* We now need to remove the insn that are special from the /* We now need to remove the insn that are special from the
"normal" optable, to make the disasm search this extra list "normal" optable, to make the disasm search this extra list
for them. for them.
*/ */
for (i=0; i<C4X_SPESOP_SIZE; i++) for (i=0; i<TIC4X_SPESOP_SIZE; i++)
if ( optable_special[i] != NULL ) if ( optable_special[i] != NULL )
optable[optable_special[i]->opcode >> (32 - C4X_HASH_SIZE)] = NULL; optable[optable_special[i]->opcode >> (32 - TIC4X_HASH_SIZE)] = NULL;
} }
/* See if we can pick up any loading of the DP register... */ /* See if we can pick up any loading of the DP register... */
if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70) if ((instruction >> 16) == 0x5070 || (instruction >> 16) == 0x1f70)
c4x_dp = EXTRU (instruction, 15, 0); tic4x_dp = EXTRU (instruction, 15, 0);
p = optable[instruction >> (32 - C4X_HASH_SIZE)]; p = optable[instruction >> (32 - TIC4X_HASH_SIZE)];
if ( p != NULL ) if ( p != NULL )
{ {
if ( ((instruction & p->opmask) == p->opcode) if ( ((instruction & p->opmask) == p->opcode)
&& c4x_print_op (NULL, instruction, p, pc) ) && tic4x_print_op (NULL, instruction, p, pc) )
c4x_print_op (info, instruction, p, pc); tic4x_print_op (info, instruction, p, pc);
else else
(*info->fprintf_func) (info->stream, "%08x", instruction); (*info->fprintf_func) (info->stream, "%08x", instruction);
} }
else else
{ {
for (i = 0; i<C4X_SPESOP_SIZE; i++) for (i = 0; i<TIC4X_SPESOP_SIZE; i++)
if (optable_special[i] != NULL if (optable_special[i] != NULL
&& optable_special[i]->opcode == instruction ) && optable_special[i]->opcode == instruction )
{ {
(*info->fprintf_func)(info->stream, "%s", optable_special[i]->name); (*info->fprintf_func)(info->stream, "%s", optable_special[i]->name);
break; break;
} }
if (i==C4X_SPESOP_SIZE) if (i==TIC4X_SPESOP_SIZE)
(*info->fprintf_func) (info->stream, "%08x", instruction); (*info->fprintf_func) (info->stream, "%08x", instruction);
} }
@ -822,5 +823,5 @@ print_insn_tic4x (memaddr, info)
info->bytes_per_chunk = 4; info->bytes_per_chunk = 4;
info->octets_per_byte = 4; info->octets_per_byte = 4;
info->display_endian = BFD_ENDIAN_LITTLE; info->display_endian = BFD_ENDIAN_LITTLE;
return c4x_disassemble (pc, op, info) * 4; return tic4x_disassemble (pc, op, info) * 4;
} }