Fix cmov immed.
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1379884be1
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4 changed files with 77 additions and 34 deletions
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@ -1,10 +1,11 @@
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Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
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Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
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* simops.c (condition_met): Make global.
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* simops.c (condition_met): Make global.
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* sim-main.h (TRACE_ALU_INPUT3): Define.
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* sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0): Define.
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start-sanitize-v850e
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start-sanitize-v850e
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* simops.c (OP_32007E0): Move "cmov" to v850.igen, fix.
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* simops.c: Move "cmov", "cmov imm" to v850.igen, fix.
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end-sanitize-v850e
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end-sanitize-v850e
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Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
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Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
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@ -225,7 +225,7 @@ sim_core_write_unaligned_##LEN (STATE_CPU (simulator, 0), \
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/* compare cccc field against PSW */
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/* compare cccc field against PSW */
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unsigned int condition_met (unsigned code);
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int condition_met (unsigned code);
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/* Debug/tracing calls */
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/* Debug/tracing calls */
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@ -334,6 +334,17 @@ do { \
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} \
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} \
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} while (0)
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} while (0)
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#define TRACE_BRANCH0() \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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trace_module = "branch"; \
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trace_pc = cia; \
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trace_name = itable[MY_INDEX].name; \
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trace_num_values = 0; \
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trace_result (1, (nia)); \
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} \
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} while (0)
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#define TRACE_BRANCH1(IN1) \
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#define TRACE_BRANCH1(IN1) \
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do { \
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do { \
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if (TRACE_BRANCH_P (CPU)) { \
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if (TRACE_BRANCH_P (CPU)) { \
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@ -380,10 +391,13 @@ do { \
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#define trace_result(HAS_RESULT, RESULT)
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#define trace_result(HAS_RESULT, RESULT)
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#define TRACE_ALU_INPUT0()
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#define TRACE_ALU_INPUT0()
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#define TRACE_ALU_INPUT1(IN1)
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#define TRACE_ALU_INPUT1(IN0)
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#define TRACE_ALU_INPUT2(IN1, IN2)
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#define TRACE_ALU_INPUT2(IN0, IN1)
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#define TRACE_ALU_INPUT2(IN0, IN1)
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#define TRACE_ALU_INPUT2(IN0, IN1 INS2)
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#define TRACE_ALU_RESULT(RESULT)
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#define TRACE_ALU_RESULT(RESULT)
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#define TRACE_BRANCH0()
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#define TRACE_BRANCH1(IN1)
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#define TRACE_BRANCH1(IN1)
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#define TRACE_BRANCH2(IN1, IN2)
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#define TRACE_BRANCH2(IN1, IN2)
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#define TRACE_BRANCH2(IN1, IN2, IN3)
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#define TRACE_BRANCH2(IN1, IN2, IN3)
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@ -305,7 +305,7 @@ trace_output (result)
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/* Returns 1 if the specific condition is met, returns 0 otherwise. */
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/* Returns 1 if the specific condition is met, returns 0 otherwise. */
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unsigned int
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int
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condition_met (unsigned code)
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condition_met (unsigned code)
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{
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{
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unsigned int psw = PSW;
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unsigned int psw = PSW;
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@ -2709,22 +2709,6 @@ OP_24007E0 (void)
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return 4;
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return 4;
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}
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}
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/* end-sanitize-v850e */
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/* start-sanitize-v850e */
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/* cmov imm5, reg2, reg3 */
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int
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OP_30007E0 (void)
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{
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trace_input ("cmov", OP_IMM_REG_REG, 0);
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State.regs[ OP[2] >> 11 ] = condition_met (OP[0]) ? SEXT5( OP[0] ) : State.regs[ OP[1] ];
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trace_output (OP_IMM_REG_REG);
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return 4;
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}
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/* end-sanitize-v850e */
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/* end-sanitize-v850e */
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/* start-sanitize-v850e */
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/* start-sanitize-v850e */
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/* ld.hu */
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/* ld.hu */
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@ -121,9 +121,51 @@ rrrrr,110110,RRRRR + iiiiiiiiiiiiiiii:VI:::andi
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// Map condition code to a string
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:%s:::cccc:int cccc
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{
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switch (cccc)
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{
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case 0xf: return "gt";
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case 0xe: return "ge";
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case 0x6: return "lt";
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case 0x7: return "le";
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case 0xb: return "h";
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case 0x9: return "nl";
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case 0x1: return "l";
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case 0x3: return "nh";
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case 0x2: return "e";
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case 0xa: return "ne";
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case 0x0: return "v";
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case 0x8: return "nv";
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case 0x4: return "n";
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case 0xc: return "p";
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/* case 0x1: return "c"; */
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/* case 0x9: return "nc"; */
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/* case 0x2: return "z"; */
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/* case 0xa: return "nz"; */
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case 0x5: return "r"; /* always */
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case 0xd: return "sa";
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}
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return "(null)";
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}
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// Bcond
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// Bcond
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// ddddd,1011,ddd,cccc:III:::Bcond
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// ddddd,1011,ddd,cccc:III:::Bcond
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// "b<cond> disp9"
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// "b%s<cccc> <disp9>"
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// {
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// int cond = condition_met (cccc);
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// if (cond)
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// nia = cia + disp9;
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// TRACE_BRANCH1 (cond);
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// }
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ddddd,1011,ddd,0000:III:::bv
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ddddd,1011,ddd,0000:III:::bv
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"bv <disp9>"
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"bv <disp9>"
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@ -351,10 +393,11 @@ rrrrr,111111,RRRRR + wwwww,011001,cccc,0:XI:::cmov
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// start-sanitize-v850eq
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// start-sanitize-v850eq
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*v850eq
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*v850eq
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// end-sanitize-v850eq
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// end-sanitize-v850eq
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"cmov <cccc>, r<reg1>, r<reg2>, r<reg3>"
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"cmov %s<cccc>, r<reg1>, r<reg2>, r<reg3>"
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{
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{
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TRACE_ALU_INPUT3 (cccc, GR[reg1], GR[reg2]);
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int cond = condition_met (cccc);
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GR[reg3] = condition_met (cccc) ? GR[reg1] : GR[reg2];
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TRACE_ALU_INPUT3 (cond, GR[reg1], GR[reg2]);
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GR[reg3] = cond ? GR[reg1] : GR[reg2];
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TRACE_ALU_RESULT (GR[reg3]);
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TRACE_ALU_RESULT (GR[reg3]);
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}
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}
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@ -365,9 +408,12 @@ rrrrr,111111,iiiii + wwwww,011000,cccc,0:XII:::cmov
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// start-sanitize-v850eq
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// start-sanitize-v850eq
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*v850eq
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*v850eq
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// end-sanitize-v850eq
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// end-sanitize-v850eq
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"cmov <cccc>, <imm5>, r<reg2>, r<reg3>"
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"cmov %s<cccc>, <imm5>, r<reg2>, r<reg3>"
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{
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{
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COMPAT_2 (OP_30007E0 ());
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int cond = condition_met (cccc);
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TRACE_ALU_INPUT3 (cond, imm5, GR[reg2]);
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GR[reg3] = cond ? imm5 : GR[reg2];
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TRACE_ALU_RESULT (GR[reg3]);
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}
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}
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@ -552,10 +598,8 @@ rrrrr!0,11110,dddddd + ddddddddddddddd,0:V:::jarl
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00000000011,RRRRR:I:::jmp
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00000000011,RRRRR:I:::jmp
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"jmp [r<reg1>]"
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"jmp [r<reg1>]"
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{
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{
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SAVE_1;
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nia = GR[reg1];
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trace_input ("jmp", OP_REG, 0);
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TRACE_BRANCH0 ();
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nia = State.regs[ reg1 ];
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trace_output (OP_REG);
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}
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}
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@ -933,7 +977,7 @@ rrrrr,1111110,cccc + 0000001000000000:IX:::sasf
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// start-sanitize-v850eq
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// start-sanitize-v850eq
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*v850eq
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*v850eq
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// end-sanitize-v850eq
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// end-sanitize-v850eq
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"sasf <cccc>, r<reg2>"
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"sasf %s<cccc>, r<reg2>"
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{
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{
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COMPAT_2 (OP_20007E0 ());
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COMPAT_2 (OP_20007E0 ());
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}
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}
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@ -986,7 +1030,7 @@ rrrrr!0,000100,RRRRR:I:::satsubr
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// SETF
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// SETF
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rrrrr,1111110,cccc + 0000000000000000:IX:::setf
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rrrrr,1111110,cccc + 0000000000000000:IX:::setf
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"setf <cccc>, r<reg2>"
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"setf %s<cccc>, r<reg2>"
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{
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{
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COMPAT_2 (OP_7E0 ());
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COMPAT_2 (OP_7E0 ());
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}
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}
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