[AArch64] Add SVE condition codes
SVE defines new names for existing NZCV conditions, to reflect the
result of instructions like PTEST. This patch adds support for these
names.
The patch also adds comments to the disassembly output to show the
alternative names of a condition code. For example:
cinv x0, x1, cc
becomes:
cinv x0, x1, cc // cc = lo, ul, last
and:
b.cc f0 <...>
becomes:
b.cc f0 <...> // b.lo, b.ul, b.last
Doing this for the SVE names follows the practice recommended by the
SVE specification and is definitely useful when reading SVE code.
If the feeling is that it's too distracting elsewhere, we could add
an option to turn it off.
include/
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
opcodes/
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
(print_mnemonic_name): ...here.
(print_comment): New function.
(print_aarch64_insn): Call it.
* aarch64-opc.c (aarch64_conds): Add SVE names.
(aarch64_print_operand): Print alternative condition names in
a comment.
gas/
* config/tc-aarch64.c (opcode_lookup): Search for the end of
a condition name, rather than assuming that it will have exactly
2 characters.
(parse_operands): Likewise.
* testsuite/gas/aarch64/alias.d: Add new condition-code comments
to the expected output.
* testsuite/gas/aarch64/beq_1.d: Likewise.
* testsuite/gas/aarch64/float-fp16.d: Likewise.
* testsuite/gas/aarch64/int-insns.d: Likewise.
* testsuite/gas/aarch64/no-aliases.d: Likewise.
* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
* testsuite/gas/aarch64/reloc-insn.d: Likewise.
* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
New test.
ld/
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
This commit is contained in:
Richard Sandiford
parent
f2a5c4f5af
commit
bb7eff5206
19 changed files with 317 additions and 97 deletions
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@ -1,3 +1,20 @@
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* config/tc-aarch64.c (opcode_lookup): Search for the end of
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a condition name, rather than assuming that it will have exactly
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2 characters.
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(parse_operands): Likewise.
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* testsuite/gas/aarch64/alias.d: Add new condition-code comments
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to the expected output.
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* testsuite/gas/aarch64/beq_1.d: Likewise.
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* testsuite/gas/aarch64/float-fp16.d: Likewise.
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* testsuite/gas/aarch64/int-insns.d: Likewise.
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* testsuite/gas/aarch64/no-aliases.d: Likewise.
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* testsuite/gas/aarch64/programmer-friendly.d: Likewise.
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* testsuite/gas/aarch64/reloc-insn.d: Likewise.
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* testsuite/gas/aarch64/b_c_1.d, testsuite/gas/aarch64/b_c_1.s:
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New test.
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2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
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* testsuite/gas/aarch64/diagnostic.s,
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@ -4836,41 +4836,44 @@ lookup_mnemonic (const char *start, int len)
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static templates *
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opcode_lookup (char **str)
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{
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char *end, *base;
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char *end, *base, *dot;
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const aarch64_cond *cond;
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char condname[16];
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int len;
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/* Scan up to the end of the mnemonic, which must end in white space,
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'.', or end of string. */
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dot = 0;
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for (base = end = *str; is_part_of_name(*end); end++)
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if (*end == '.')
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break;
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if (*end == '.' && !dot)
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dot = end;
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if (end == base)
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if (end == base || dot == base)
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return 0;
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inst.cond = COND_ALWAYS;
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/* Handle a possible condition. */
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if (end[0] == '.')
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if (dot)
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{
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cond = hash_find_n (aarch64_cond_hsh, end + 1, 2);
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cond = hash_find_n (aarch64_cond_hsh, dot + 1, end - dot - 1);
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if (cond)
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{
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inst.cond = cond->value;
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*str = end + 3;
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*str = end;
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}
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else
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{
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*str = end;
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*str = dot;
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return 0;
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}
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len = dot - base;
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}
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else
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*str = end;
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len = end - base;
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{
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*str = end;
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len = end - base;
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}
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if (inst.cond == COND_ALWAYS)
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{
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@ -5826,20 +5829,25 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_COND:
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case AARCH64_OPND_COND1:
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info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
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str += 2;
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if (info->cond == NULL)
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{
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set_syntax_error (_("invalid condition"));
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goto failure;
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}
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else if (operands[i] == AARCH64_OPND_COND1
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&& (info->cond->value & 0xe) == 0xe)
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{
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/* Not allow AL or NV. */
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set_default_error ();
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goto failure;
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}
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{
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char *start = str;
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do
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str++;
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while (ISALPHA (*str));
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info->cond = hash_find_n (aarch64_cond_hsh, start, str - start);
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if (info->cond == NULL)
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{
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set_syntax_error (_("invalid condition"));
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goto failure;
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}
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else if (operands[i] == AARCH64_OPND_COND1
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&& (info->cond->value & 0xe) == 0xe)
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{
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/* Do not allow AL or NV. */
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set_default_error ();
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goto failure;
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}
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}
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break;
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case AARCH64_OPND_ADDR_ADRP:
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@ -29,19 +29,19 @@ Disassembly of section \.text:
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54: 9ba28c20 umsubl x0, w1, w2, x3
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58: 9ba2fc20 umnegl x0, w1, w2
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5c: 9ba2fc20 umnegl x0, w1, w2
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60: 1a9f0420 csinc w0, w1, wzr, eq
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64: 1a810420 cinc w0, w1, ne
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68: 1a810420 cinc w0, w1, ne
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6c: 1a9f37e0 cset w0, cs
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70: 1a9f37e0 cset w0, cs
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74: da9f2020 csinv x0, x1, xzr, cs
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78: da812020 cinv x0, x1, cc
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7c: da812020 cinv x0, x1, cc
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80: da9f43e0 csetm x0, pl
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84: da9f43e0 csetm x0, pl
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88: da9eb7e0 csneg x0, xzr, x30, lt
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8c: da9eb7c0 cneg x0, x30, ge
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90: da9eb7c0 cneg x0, x30, ge
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60: 1a9f0420 csinc w0, w1, wzr, eq // eq = none
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64: 1a810420 cinc w0, w1, ne // ne = any
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68: 1a810420 cinc w0, w1, ne // ne = any
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6c: 1a9f37e0 cset w0, cs // cs = hs, nlast
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70: 1a9f37e0 cset w0, cs // cs = hs, nlast
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74: da9f2020 csinv x0, x1, xzr, cs // cs = hs, nlast
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78: da812020 cinv x0, x1, cc // cc = lo, ul, last
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7c: da812020 cinv x0, x1, cc // cc = lo, ul, last
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80: da9f43e0 csetm x0, pl // pl = nfrst
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84: da9f43e0 csetm x0, pl // pl = nfrst
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88: da9eb7e0 csneg x0, xzr, x30, lt // lt = tstop
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8c: da9eb7c0 cneg x0, x30, ge // ge = tcont
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90: da9eb7c0 cneg x0, x30, ge // ge = tcont
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94: ea020020 ands x0, x1, x2
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98: ea02003f tst x1, x2
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9c: ea02003f tst x1, x2
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58
gas/testsuite/gas/aarch64/b_c_1.d
Normal file
58
gas/testsuite/gas/aarch64/b_c_1.d
Normal file
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@ -0,0 +1,58 @@
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# objdump: -d
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.*: .*
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Disassembly of section \.text:
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0+0 <\.text>:
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.*: 54.....0 b\.eq 0 <\.text> // b\.none
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.*: 54.....0 b\.eq 0 <\.text> // b\.none
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.*: 54.....2 b\.cs 0 <\.text> // b\.hs, b\.nlast
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.*: 54.....2 b\.cs 0 <\.text> // b\.hs, b\.nlast
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.*: 54.....2 b\.cs 0 <\.text> // b\.hs, b\.nlast
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.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
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.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
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.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
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.*: 54.....3 b\.cc 0 <\.text> // b\.lo, b\.ul, b\.last
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.*: 54.....4 b\.mi 0 <\.text> // b\.first
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.*: 54.....4 b\.mi 0 <\.text> // b\.first
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.*: 54.....5 b\.pl 0 <\.text> // b\.nfrst
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.*: 54.....5 b\.pl 0 <\.text> // b\.nfrst
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.*: 54.....6 b\.vs 0 <\.text>
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.*: 54.....7 b\.vc 0 <\.text>
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.*: 54.....8 b\.hi 0 <\.text> // b\.pmore
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.*: 54.....8 b\.hi 0 <\.text> // b\.pmore
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.*: 54.....9 b\.ls 0 <\.text> // b\.plast
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.*: 54.....9 b\.ls 0 <\.text> // b\.plast
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.*: 54.....a b\.ge 0 <\.text> // b\.tcont
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.*: 54.....a b\.ge 0 <\.text> // b\.tcont
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.*: 54.....b b\.lt 0 <\.text> // b\.tstop
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.*: 54.....b b\.lt 0 <\.text> // b\.tstop
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.*: 54.....c b\.gt 0 <\.text>
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.*: 54.....d b\.le 0 <\.text>
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.*: 9a830041 csel x1, x2, x3, eq // eq = none
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.*: 9a830041 csel x1, x2, x3, eq // eq = none
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.*: 9a832041 csel x1, x2, x3, cs // cs = hs, nlast
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.*: 9a832041 csel x1, x2, x3, cs // cs = hs, nlast
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.*: 9a832041 csel x1, x2, x3, cs // cs = hs, nlast
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.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
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.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
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.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
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.*: 9a833041 csel x1, x2, x3, cc // cc = lo, ul, last
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.*: 9a834041 csel x1, x2, x3, mi // mi = first
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.*: 9a834041 csel x1, x2, x3, mi // mi = first
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.*: 9a835041 csel x1, x2, x3, pl // pl = nfrst
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.*: 9a835041 csel x1, x2, x3, pl // pl = nfrst
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.*: 9a836041 csel x1, x2, x3, vs
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.*: 9a837041 csel x1, x2, x3, vc
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.*: 9a838041 csel x1, x2, x3, hi // hi = pmore
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.*: 9a838041 csel x1, x2, x3, hi // hi = pmore
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.*: 9a839041 csel x1, x2, x3, ls // ls = plast
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.*: 9a839041 csel x1, x2, x3, ls // ls = plast
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.*: 9a83a041 csel x1, x2, x3, ge // ge = tcont
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.*: 9a83a041 csel x1, x2, x3, ge // ge = tcont
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.*: 9a83b041 csel x1, x2, x3, lt // lt = tstop
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.*: 9a83b041 csel x1, x2, x3, lt // lt = tstop
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.*: 9a83c041 csel x1, x2, x3, gt
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.*: 9a83d041 csel x1, x2, x3, le
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76
gas/testsuite/gas/aarch64/b_c_1.s
Normal file
76
gas/testsuite/gas/aarch64/b_c_1.s
Normal file
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@ -0,0 +1,76 @@
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1:
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b.eq 1b
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b.none 1b
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b.cs 1b
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b.hs 1b
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b.nlast 1b
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b.cc 1b
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b.lo 1b
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b.ul 1b
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b.last 1b
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b.mi 1b
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b.first 1b
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b.pl 1b
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b.nfrst 1b
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b.vs 1b
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b.vc 1b
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b.hi 1b
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b.pmore 1b
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b.ls 1b
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b.plast 1b
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b.ge 1b
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b.tcont 1b
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b.lt 1b
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b.tstop 1b
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b.gt 1b
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b.le 1b
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csel x1, x2, x3, eq
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csel x1, x2, x3, none
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csel x1, x2, x3, cs
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csel x1, x2, x3, hs
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csel x1, x2, x3, nlast
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csel x1, x2, x3, cc
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csel x1, x2, x3, lo
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csel x1, x2, x3, ul
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csel x1, x2, x3, last
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csel x1, x2, x3, mi
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csel x1, x2, x3, first
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csel x1, x2, x3, pl
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csel x1, x2, x3, nfrst
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csel x1, x2, x3, vs
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csel x1, x2, x3, vc
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csel x1, x2, x3, hi
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csel x1, x2, x3, pmore
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csel x1, x2, x3, ls
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csel x1, x2, x3, plast
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csel x1, x2, x3, ge
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csel x1, x2, x3, tcont
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csel x1, x2, x3, lt
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csel x1, x2, x3, tstop
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csel x1, x2, x3, gt
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csel x1, x2, x3, le
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@ -5,5 +5,5 @@
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Disassembly of section \.text:
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0000000000000000 <.*>:
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0: 54000000 b.eq 0 <bar>
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0: 54000000 b\.eq 0 <bar> // b\.none
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0: R_AARCH64_CONDBR19 bar\+0x100000
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@ -6,12 +6,12 @@
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Disassembly of section \.text:
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0000000000000000 <.*>:
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[0-9a-f]+: 1e200400 fccmp s0, s0, #0x0, eq
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[0-9a-f]+: 1ee00400 fccmp h0, h0, #0x0, eq
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[0-9a-f]+: 1e200400 fccmp s0, s0, #0x0, eq // eq = none
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[0-9a-f]+: 1ee00400 fccmp h0, h0, #0x0, eq // eq = none
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[0-9a-f]+: 1e22d420 fccmp s1, s2, #0x0, le
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[0-9a-f]+: 1ee2d420 fccmp h1, h2, #0x0, le
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[0-9a-f]+: 1e200410 fccmpe s0, s0, #0x0, eq
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[0-9a-f]+: 1ee00410 fccmpe h0, h0, #0x0, eq
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[0-9a-f]+: 1e200410 fccmpe s0, s0, #0x0, eq // eq = none
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[0-9a-f]+: 1ee00410 fccmpe h0, h0, #0x0, eq // eq = none
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[0-9a-f]+: 1e22d430 fccmpe s1, s2, #0x0, le
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[0-9a-f]+: 1ee2d430 fccmpe h1, h2, #0x0, le
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[0-9a-f]+: 1e202000 fcmp s0, s0
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@ -26,8 +26,8 @@ Disassembly of section \.text:
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[0-9a-f]+: 1ee02008 fcmp h0, #0\.0
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[0-9a-f]+: 1e202018 fcmpe s0, #0\.0
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[0-9a-f]+: 1ee02018 fcmpe h0, #0\.0
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[0-9a-f]+: 1e210c00 fcsel s0, s0, s1, eq
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[0-9a-f]+: 1ee10c00 fcsel h0, h0, h1, eq
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[0-9a-f]+: 1e210c00 fcsel s0, s0, s1, eq // eq = none
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[0-9a-f]+: 1ee10c00 fcsel h0, h0, h1, eq // eq = none
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[0-9a-f]+: 9ee60000 fmov x0, h0
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[0-9a-f]+: 1ee60000 fmov w0, h0
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[0-9a-f]+: 9ee70001 fmov h1, x0
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@ -13,8 +13,8 @@ Disassembly of section .text:
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10: 93c3fc41 extr x1, x2, x3, #63
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14: 93c30041 extr x1, x2, x3, #0
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18: 13837c41 extr w1, w2, w3, #31
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1c: 9a9f17e1 cset x1, eq
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20: da9f13e1 csetm x1, eq
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1c: 9a9f17e1 cset x1, eq // eq = none
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20: da9f13e1 csetm x1, eq // eq = none
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24: 71000021 subs w1, w1, #0x0
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28: 7100003f cmp w1, #0x0
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2c: 4b0203e1 neg w1, w2
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@ -64,17 +64,17 @@ Disassembly of section .text:
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d4: 92400c85 and x5, x4, #0xf
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d8: 0a230041 bic w1, w2, w3
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dc: 8a230041 bic x1, x2, x3
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e0: 54000001 b.ne e0 <sp\+0x90>
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e0: 54000001 b\.ne e0 <sp\+0x90> // b\.any
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e4: 17ffffff b e0 <sp\+0x90>
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e8: 14000001 b ec <sp\+0x9c>
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ec: 54ffffa0 b.eq e0 <sp\+0x90>
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f0: 54000001 b.ne f0 <sp\+0xa0>
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ec: 54ffffa0 b\.eq e0 <sp\+0x90> // b\.none
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f0: 54000001 b\.ne f0 <sp\+0xa0> // b\.any
|
||||
f4: 17ffffff b f0 <sp\+0xa0>
|
||||
f8: 14000001 b fc <sp\+0xac>
|
||||
fc: 54ffffa0 b.eq f0 <sp\+0xa0>
|
||||
fc: 54ffffa0 b\.eq f0 <sp\+0xa0> // b\.none
|
||||
100: d61f0040 br x2
|
||||
104: 54ffffc2 b.cs fc <sp\+0xac>
|
||||
108: 54ffffa3 b.cc fc <sp\+0xac>
|
||||
104: 54ffffc2 b\.cs fc <sp\+0xac> // b\.hs, b\.nlast
|
||||
108: 54ffffa3 b\.cc fc <sp\+0xac> // b\.lo, b\.ul, b\.last
|
||||
...
|
||||
10c: R_AARCH64_ABS32 .text\+0x50
|
||||
110: R_AARCH64_ABS64 .text\+0x50
|
||||
|
|
|
|||
|
|
@ -30,19 +30,19 @@ Disassembly of section \.text:
|
|||
54: 9ba28c20 umsubl x0, w1, w2, x3
|
||||
58: 9ba2fc20 umsubl x0, w1, w2, xzr
|
||||
5c: 9ba2fc20 umsubl x0, w1, w2, xzr
|
||||
60: 1a9f0420 csinc w0, w1, wzr, eq
|
||||
64: 1a810420 csinc w0, w1, w1, eq
|
||||
68: 1a810420 csinc w0, w1, w1, eq
|
||||
6c: 1a9f37e0 csinc w0, wzr, wzr, cc
|
||||
70: 1a9f37e0 csinc w0, wzr, wzr, cc
|
||||
74: da9f2020 csinv x0, x1, xzr, cs
|
||||
78: da812020 csinv x0, x1, x1, cs
|
||||
7c: da812020 csinv x0, x1, x1, cs
|
||||
80: da9f43e0 csinv x0, xzr, xzr, mi
|
||||
84: da9f43e0 csinv x0, xzr, xzr, mi
|
||||
88: da9eb7e0 csneg x0, xzr, x30, lt
|
||||
8c: da9eb7c0 csneg x0, x30, x30, lt
|
||||
90: da9eb7c0 csneg x0, x30, x30, lt
|
||||
60: 1a9f0420 csinc w0, w1, wzr, eq // eq = none
|
||||
64: 1a810420 csinc w0, w1, w1, eq // eq = none
|
||||
68: 1a810420 csinc w0, w1, w1, eq // eq = none
|
||||
6c: 1a9f37e0 csinc w0, wzr, wzr, cc // cc = lo, ul, last
|
||||
70: 1a9f37e0 csinc w0, wzr, wzr, cc // cc = lo, ul, last
|
||||
74: da9f2020 csinv x0, x1, xzr, cs // cs = hs, nlast
|
||||
78: da812020 csinv x0, x1, x1, cs // cs = hs, nlast
|
||||
7c: da812020 csinv x0, x1, x1, cs // cs = hs, nlast
|
||||
80: da9f43e0 csinv x0, xzr, xzr, mi // mi = first
|
||||
84: da9f43e0 csinv x0, xzr, xzr, mi // mi = first
|
||||
88: da9eb7e0 csneg x0, xzr, x30, lt // lt = tstop
|
||||
8c: da9eb7c0 csneg x0, x30, x30, lt // lt = tstop
|
||||
90: da9eb7c0 csneg x0, x30, x30, lt // lt = tstop
|
||||
94: ea020020 ands x0, x1, x2
|
||||
98: ea02003f ands xzr, x1, x2
|
||||
9c: ea02003f ands xzr, x1, x2
|
||||
|
|
|
|||
|
|
@ -9,7 +9,7 @@ Disassembly of section \.text:
|
|||
4: 98000241 ldrsw x1, 4c <\.text\+0x4c>
|
||||
8: 98000007 ldrsw x7, 0 <\.text>
|
||||
8: R_AARCH64_LD_PREL_LO19 \.data\+0x4
|
||||
c: fa42a02a ccmp x1, x2, #0xa, ge
|
||||
c: fa42a02a ccmp x1, x2, #0xa, ge // ge = tcont
|
||||
10: 53001eaf uxtb w15, w21
|
||||
14: 53003f67 uxth w7, w27
|
||||
18: 2a1f03e8 mov w8, wzr
|
||||
|
|
|
|||
|
|
@ -109,8 +109,8 @@ Disassembly of section \.text:
|
|||
fc: 37400522 tbnz w2, #8, 1a0 <lab>
|
||||
100: b7780002 tbnz x2, #47, 0 <xlab>
|
||||
100: R_AARCH64_TSTBR14 xlab
|
||||
104: 540004e0 b\.eq 1a0 <lab>
|
||||
108: 54000000 b\.eq 0 <xlab>
|
||||
104: 540004e0 b\.eq 1a0 <lab> // b\.none
|
||||
108: 54000000 b\.eq 0 <xlab> // b\.none
|
||||
108: R_AARCH64_CONDBR19 xlab
|
||||
10c: b40004a0 cbz x0, 1a0 <lab>
|
||||
110: b500001e cbnz x30, 0 <xlab>
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* opcode/aarch64.h (aarch64_cond): Bump array size to 4.
|
||||
|
||||
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* opcode/aarch64.h (AARCH64_FEATURE_SVE): New macro.
|
||||
|
|
|
|||
|
|
@ -859,7 +859,7 @@ typedef struct
|
|||
{
|
||||
/* A list of names with the first one as the disassembly preference;
|
||||
terminated by NULL if fewer than 3. */
|
||||
const char *names[3];
|
||||
const char *names[4];
|
||||
aarch64_insn value;
|
||||
} aarch64_cond;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* testsuite/ld-aarch64/emit-relocs-280.d: Match branch comments.
|
||||
* testsuite/ld-aarch64/weak-undefined.d: Likewise.
|
||||
|
||||
2016-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
|
||||
|
||||
* ld.texinfo (Input Section Basics): Expand the description of
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@
|
|||
+10004: 8a000000 and .*
|
||||
+10008: 8a000000 and .*
|
||||
+1000c: 8a000000 and .*
|
||||
+10010: 54fdff80 b.eq c000 <target>
|
||||
+10010: 54fdff80 b.eq c000 <target> // .*
|
||||
+10010: R_AARCH64_CONDBR19 target
|
||||
+10014: 54fdffe0 b.eq c010 <target\+0x10>
|
||||
+10014: 54fdffe0 b.eq c010 <target\+0x10> // .*
|
||||
+10014: R_AARCH64_CONDBR19 target\+0x10
|
||||
|
|
|
|||
|
|
@ -2,13 +2,13 @@
|
|||
#ld: -Ttext 0xF0000000 -T relocs.ld -e0 --emit-relocs
|
||||
#objdump: -d
|
||||
#...
|
||||
+f0000000: 54000001 b\.ne f0000000 <main>
|
||||
+f0000004: 54000000 b\.eq f0000004 <main\+0x4>
|
||||
+f0000008: 54000002 b\.cs f0000008 <main\+0x8>
|
||||
+f000000c: 54000003 b\.cc f000000c <main\+0xc>
|
||||
+f0000000: 54000001 b\.ne f0000000 <main> // .*
|
||||
+f0000004: 54000000 b\.eq f0000004 <main\+0x4> // .*
|
||||
+f0000008: 54000002 b\.cs f0000008 <main\+0x8> // .*
|
||||
+f000000c: 54000003 b\.cc f000000c <main\+0xc> // .*
|
||||
+f0000010: 5400000c b\.gt f0000010 <main\+0x10>
|
||||
+f0000014: 5400000a b\.ge f0000014 <main\+0x14>
|
||||
+f0000018: 5400000b b\.lt f0000018 <main\+0x18>
|
||||
+f0000014: 5400000a b\.ge f0000014 <main\+0x14> // .*
|
||||
+f0000018: 5400000b b\.lt f0000018 <main\+0x18> // .*
|
||||
+f000001c: 5400000d b\.le f000001c <main\+0x1c>
|
||||
+f0000020: d503201f nop
|
||||
+f0000024: d503201f nop
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* aarch64-dis.c (remove_dot_suffix): New function, split out from...
|
||||
(print_mnemonic_name): ...here.
|
||||
(print_comment): New function.
|
||||
(print_aarch64_insn): Call it.
|
||||
* aarch64-opc.c (aarch64_conds): Add SVE names.
|
||||
(aarch64_print_operand): Print alternative condition names in
|
||||
a comment.
|
||||
|
||||
2016-09-21 Richard Sandiford <richard.sandiford@arm.com>
|
||||
|
||||
* aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
|
||||
|
|
|
|||
|
|
@ -2787,6 +2787,22 @@ print_operands (bfd_vma pc, const aarch64_opcode *opcode,
|
|||
}
|
||||
}
|
||||
|
||||
/* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
|
||||
|
||||
static void
|
||||
remove_dot_suffix (char *name, const aarch64_inst *inst)
|
||||
{
|
||||
char *ptr;
|
||||
size_t len;
|
||||
|
||||
ptr = strchr (inst->opcode->name, '.');
|
||||
assert (ptr && inst->cond);
|
||||
len = ptr - inst->opcode->name;
|
||||
assert (len < 8);
|
||||
strncpy (name, inst->opcode->name, len);
|
||||
name[len] = '\0';
|
||||
}
|
||||
|
||||
/* Print the instruction mnemonic name. */
|
||||
|
||||
static void
|
||||
|
|
@ -2797,21 +2813,35 @@ print_mnemonic_name (const aarch64_inst *inst, struct disassemble_info *info)
|
|||
/* For instructions that are truly conditionally executed, e.g. b.cond,
|
||||
prepare the full mnemonic name with the corresponding condition
|
||||
suffix. */
|
||||
char name[8], *ptr;
|
||||
size_t len;
|
||||
char name[8];
|
||||
|
||||
ptr = strchr (inst->opcode->name, '.');
|
||||
assert (ptr && inst->cond);
|
||||
len = ptr - inst->opcode->name;
|
||||
assert (len < 8);
|
||||
strncpy (name, inst->opcode->name, len);
|
||||
name [len] = '\0';
|
||||
remove_dot_suffix (name, inst);
|
||||
(*info->fprintf_func) (info->stream, "%s.%s", name, inst->cond->names[0]);
|
||||
}
|
||||
else
|
||||
(*info->fprintf_func) (info->stream, "%s", inst->opcode->name);
|
||||
}
|
||||
|
||||
/* Decide whether we need to print a comment after the operands of
|
||||
instruction INST. */
|
||||
|
||||
static void
|
||||
print_comment (const aarch64_inst *inst, struct disassemble_info *info)
|
||||
{
|
||||
if (inst->opcode->flags & F_COND)
|
||||
{
|
||||
char name[8];
|
||||
unsigned int i, num_conds;
|
||||
|
||||
remove_dot_suffix (name, inst);
|
||||
num_conds = ARRAY_SIZE (inst->cond->names);
|
||||
for (i = 1; i < num_conds && inst->cond->names[i]; ++i)
|
||||
(*info->fprintf_func) (info->stream, "%s %s.%s",
|
||||
i == 1 ? " //" : ",",
|
||||
name, inst->cond->names[i]);
|
||||
}
|
||||
}
|
||||
|
||||
/* Print the instruction according to *INST. */
|
||||
|
||||
static void
|
||||
|
|
@ -2820,6 +2850,7 @@ print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
|
|||
{
|
||||
print_mnemonic_name (inst, info);
|
||||
print_operands (pc, inst->opcode, inst->operands, info);
|
||||
print_comment (inst, info);
|
||||
}
|
||||
|
||||
/* Entry-point of the instruction disassembler and printer. */
|
||||
|
|
|
|||
|
|
@ -334,18 +334,18 @@ aarch64_get_operand_desc (enum aarch64_opnd type)
|
|||
/* Table of all conditional affixes. */
|
||||
const aarch64_cond aarch64_conds[16] =
|
||||
{
|
||||
{{"eq"}, 0x0},
|
||||
{{"ne"}, 0x1},
|
||||
{{"cs", "hs"}, 0x2},
|
||||
{{"cc", "lo", "ul"}, 0x3},
|
||||
{{"mi"}, 0x4},
|
||||
{{"pl"}, 0x5},
|
||||
{{"eq", "none"}, 0x0},
|
||||
{{"ne", "any"}, 0x1},
|
||||
{{"cs", "hs", "nlast"}, 0x2},
|
||||
{{"cc", "lo", "ul", "last"}, 0x3},
|
||||
{{"mi", "first"}, 0x4},
|
||||
{{"pl", "nfrst"}, 0x5},
|
||||
{{"vs"}, 0x6},
|
||||
{{"vc"}, 0x7},
|
||||
{{"hi"}, 0x8},
|
||||
{{"ls"}, 0x9},
|
||||
{{"ge"}, 0xa},
|
||||
{{"lt"}, 0xb},
|
||||
{{"hi", "pmore"}, 0x8},
|
||||
{{"ls", "plast"}, 0x9},
|
||||
{{"ge", "tcont"}, 0xa},
|
||||
{{"lt", "tstop"}, 0xb},
|
||||
{{"gt"}, 0xc},
|
||||
{{"le"}, 0xd},
|
||||
{{"al"}, 0xe},
|
||||
|
|
@ -2940,7 +2940,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
|
||||
bfd_vma *address)
|
||||
{
|
||||
int i;
|
||||
unsigned int i, num_conds;
|
||||
const char *name = NULL;
|
||||
const aarch64_opnd_info *opnd = opnds + idx;
|
||||
enum aarch64_modifier_kind kind;
|
||||
|
|
@ -3306,6 +3306,17 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
case AARCH64_OPND_COND:
|
||||
case AARCH64_OPND_COND1:
|
||||
snprintf (buf, size, "%s", opnd->cond->names[0]);
|
||||
num_conds = ARRAY_SIZE (opnd->cond->names);
|
||||
for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
|
||||
{
|
||||
size_t len = strlen (buf);
|
||||
if (i == 1)
|
||||
snprintf (buf + len, size - len, " // %s = %s",
|
||||
opnd->cond->names[0], opnd->cond->names[i]);
|
||||
else
|
||||
snprintf (buf + len, size - len, ", %s",
|
||||
opnd->cond->names[i]);
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_ADDR_ADRP:
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue