FreeChainXenon/binutils-gdb
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Don't touch r11 in __tls_get_addr stub

Browse source 
This modifies the special __tls_get_addr stub that checks for a
tlsdesc style __tls_index entry and returns early.  Not using r11
isn't much benefit at the moment but a followup patch will preserve
regs around the first call to __tls_get_addr when the __tls_index
entry isn't yet set up for an early return.

bfd/
	* elf64-ppc.c (LD_R11_0R3, CMPDI_R11_0, STD_R11_0R1, LD_R11_0R1),
	(MTLR_R11): Don't define.
	(LD_R0_0R3, CMPDI_R0_0): Define.
	(build_tls_get_addr_stub): Don't use r11 in stub.
ld/
	* testsuite/ld-powerpc/tlsexe.d: Match new __tls_get_addr stub.
	* testsuite/ld-powerpc/tlsexeno.d: Likewise.
	* testsuite/ld-powerpc/tlsexetoc.d: Likewise.
	* testsuite/ld-powerpc/tlsexetocno.d: Likewise.
	* testsuite/ld-powerpc/tlsopt5.d: Likewise.
This commit is contained in:
Alan Modra 2020-01-20 12:33:29 +10:30
parent ed7007c18a
commit b9ca1af69e
8 changed files with 56 additions and 44 deletions
Download patch file Download diff file Expand all files Collapse all files

7
bfd/ChangeLog
View file

@ -1,3 +1,10 @@
2020-01-20 Alan Modra <amodra@gmail.com>
* elf64-ppc.c (LD_R11_0R3, CMPDI_R11_0, STD_R11_0R1, LD_R11_0R1),
(MTLR_R11): Don't define.
(LD_R0_0R3, CMPDI_R0_0): Define.
(build_tls_get_addr_stub): Don't use r11 in stub.
2020-01-20 Alan Modra <amodra@gmail.com>
* elf64-ppc.c (ppc_elf_hash_entry): New function, use throughout file.

19
bfd/elf64-ppc.c
View file

@ -10885,17 +10885,14 @@ build_plt_stub (struct ppc_link_hash_table *htab,
/* Build a special .plt call stub for __tls_get_addr. */
#define LD_R11_0R3 0xe9630000
#define LD_R0_0R3 0xe8030000
#define LD_R12_0R3 0xe9830000
#define MR_R0_R3 0x7c601b78
#define CMPDI_R11_0 0x2c2b0000
#define CMPDI_R0_0 0x2c200000
#define ADD_R3_R12_R13 0x7c6c6a14
#define BEQLR 0x4d820020
#define MR_R3_R0 0x7c030378
#define STD_R11_0R1 0xf9610000
#define BCTRL 0x4e800421
#define LD_R11_0R1 0xe9610000
#define MTLR_R11 0x7d6803a6
static inline bfd_byte *
build_tls_get_addr_stub (struct ppc_link_hash_table *htab,
@ -10905,10 +10902,10 @@ build_tls_get_addr_stub (struct ppc_link_hash_table *htab,
bfd *obfd = htab->params->stub_bfd;
bfd_byte *loc = p;
bfd_put_32 (obfd, LD_R11_0R3 + 0, p), p += 4;
bfd_put_32 (obfd, LD_R0_0R3 + 0, p), p += 4;
bfd_put_32 (obfd, LD_R12_0R3 + 8, p), p += 4;
bfd_put_32 (obfd, CMPDI_R0_0, p), p += 4;
bfd_put_32 (obfd, MR_R0_R3, p), p += 4;
bfd_put_32 (obfd, CMPDI_R11_0, p), p += 4;
bfd_put_32 (obfd, ADD_R3_R12_R13, p), p += 4;
bfd_put_32 (obfd, BEQLR, p), p += 4;
bfd_put_32 (obfd, MR_R3_R0, p), p += 4;
@ -10917,8 +10914,8 @@ build_tls_get_addr_stub (struct ppc_link_hash_table *htab,
if (stub_entry->stub_type != ppc_stub_plt_call_r2save)
return build_plt_stub (htab, stub_entry, p, offset, r);
bfd_put_32 (obfd, MFLR_R11, p), p += 4;
bfd_put_32 (obfd, STD_R11_0R1 + STK_LINKER (htab), p), p += 4;
bfd_put_32 (obfd, MFLR_R0, p), p += 4;
bfd_put_32 (obfd, STD_R0_0R1 + STK_LINKER (htab), p), p += 4;
if (r != NULL)
r[0].r_offset += 2 * 4;
@ -10926,8 +10923,8 @@ build_tls_get_addr_stub (struct ppc_link_hash_table *htab,
bfd_put_32 (obfd, BCTRL, p - 4);
bfd_put_32 (obfd, LD_R2_0R1 + STK_TOC (htab), p), p += 4;
bfd_put_32 (obfd, LD_R11_0R1 + STK_LINKER (htab), p), p += 4;
bfd_put_32 (obfd, MTLR_R11, p), p += 4;
bfd_put_32 (obfd, LD_R0_0R1 + STK_LINKER (htab), p), p += 4;
bfd_put_32 (obfd, MTLR_R0, p), p += 4;
bfd_put_32 (obfd, BLR, p), p += 4;
if (htab->glink_eh_frame != NULL

8
ld/ChangeLog
View file

@ -1,3 +1,11 @@
2020-01-20 Alan Modra <amodra@gmail.com>
* testsuite/ld-powerpc/tlsexe.d: Match new __tls_get_addr stub.
* testsuite/ld-powerpc/tlsexeno.d: Likewise.
* testsuite/ld-powerpc/tlsexetoc.d: Likewise.
* testsuite/ld-powerpc/tlsexetocno.d: Likewise.
* testsuite/ld-powerpc/tlsopt5.d: Likewise.
2020-01-18 Roland McGrath <mcgrathr@google.com>
* testsuite/ld-x86-64/align-branch-1.d: Loosen instruction regexps

12
ld/testsuite/ld-powerpc/tlsexe.d
View file

@ -9,23 +9,23 @@
Disassembly of section \.text:
.* <.*plt_call\.__tls_get_addr(|_opt)>:
.* (e9 63 00 00|00 00 63 e9) ld r11,0\(r3\)
.* (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
.* (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
.* (2c 20 00 00|00 00 20 2c) cmpdi r0,0
.* (7c 60 1b 78|78 1b 60 7c) mr r0,r3
.* (2c 2b 00 00|00 00 2b 2c) cmpdi r11,0
.* (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
.* (4d 82 00 20|20 00 82 4d) beqlr *
.* (7c 03 03 78|78 03 03 7c) mr r3,r0
.* (7d 68 02 a6|a6 02 68 7d) mflr r11
.* (f9 61 00 20|20 00 61 f9) std r11,32\(r1\)
.* (7c 08 02 a6|a6 02 08 7c) mflr r0
.* (f8 01 00 20|20 00 01 f8) std r0,32\(r1\)
.* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
.* (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\)
.* (7d 89 03 a6|a6 03 89 7d) mtctr r12
.* (e8 42 80 50|50 80 42 e8) ld r2,-32688\(r2\)
.* (4e 80 04 21|21 04 80 4e) bctrl
.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
.* (e9 61 00 20|20 00 61 e9) ld r11,32\(r1\)
.* (7d 68 03 a6|a6 03 68 7d) mtlr r11
.* (e8 01 00 20|20 00 01 e8) ld r0,32\(r1\)
.* (7c 08 03 a6|a6 03 08 7c) mtlr r0
.* (4e 80 00 20|20 00 80 4e) blr
.* <._start>:

14
ld/testsuite/ld-powerpc/tlsexeno.d
View file

@ -9,23 +9,23 @@
Disassembly of section \.text:
.* <.*plt_call\.__tls_get_addr(|_opt)>:
.*: (e9 63 00 00|00 00 63 e9) ld r11,0\(r3\)
.*: (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
.*: (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
.*: (2c 20 00 00|00 00 20 2c) cmpdi r0,0
.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
.*: (2c 2b 00 00|00 00 2b 2c) cmpdi r11,0
.*: (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
.*: (4d 82 00 20|20 00 82 4d) beqlr
.*: (4d 82 00 20|20 00 82 4d) beqlr *
.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
.*: (f9 61 00 20|20 00 61 f9) std r11,32\(r1\)
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (f8 01 00 20|20 00 01 f8) std r0,32\(r1\)
.*: (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
.*: (e9 82 80 88|88 80 82 e9) ld r12,-32632\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (e8 42 80 90|90 80 42 e8) ld r2,-32624\(r2\)
.*: (4e 80 04 21|21 04 80 4e) bctrl
.*: (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
.*: (e9 61 00 20|20 00 61 e9) ld r11,32\(r1\)
.*: (7d 68 03 a6|a6 03 68 7d) mtlr r11
.*: (e8 01 00 20|20 00 01 e8) ld r0,32\(r1\)
.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
.*: (4e 80 00 20|20 00 80 4e) blr
.* <\._start>:

12
ld/testsuite/ld-powerpc/tlsexetoc.d
View file

@ -9,23 +9,23 @@
Disassembly of section \.text:
.* <.*plt_call\.__tls_get_addr(|_opt)>:
.* (e9 63 00 00|00 00 63 e9) ld r11,0\(r3\)
.* (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
.* (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
.* (2c 20 00 00|00 00 20 2c) cmpdi r0,0
.* (7c 60 1b 78|78 1b 60 7c) mr r0,r3
.* (2c 2b 00 00|00 00 2b 2c) cmpdi r11,0
.* (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
.* (4d 82 00 20|20 00 82 4d) beqlr *
.* (7c 03 03 78|78 03 03 7c) mr r3,r0
.* (7d 68 02 a6|a6 02 68 7d) mflr r11
.* (f9 61 00 20|20 00 61 f9) std r11,32\(r1\)
.* (7c 08 02 a6|a6 02 08 7c) mflr r0
.* (f8 01 00 20|20 00 01 f8) std r0,32\(r1\)
.* (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
.* (e9 82 80 70|70 80 82 e9) ld r12,-32656\(r2\)
.* (7d 89 03 a6|a6 03 89 7d) mtctr r12
.* (e8 42 80 78|78 80 42 e8) ld r2,-32648\(r2\)
.* (4e 80 04 21|21 04 80 4e) bctrl
.* (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
.* (e9 61 00 20|20 00 61 e9) ld r11,32\(r1\)
.* (7d 68 03 a6|a6 03 68 7d) mtlr r11
.* (e8 01 00 20|20 00 01 e8) ld r0,32\(r1\)
.* (7c 08 03 a6|a6 03 08 7c) mtlr r0
.* (4e 80 00 20|20 00 80 4e) blr
.* <\._start>:

14
ld/testsuite/ld-powerpc/tlsexetocno.d
View file

@ -9,23 +9,23 @@
Disassembly of section \.text:
.* <.*plt_call\.__tls_get_addr(|_opt)>:
.*: (e9 63 00 00|00 00 63 e9) ld r11,0\(r3\)
.*: (e8 03 00 00|00 00 03 e8) ld r0,0\(r3\)
.*: (e9 83 00 08|08 00 83 e9) ld r12,8\(r3\)
.*: (2c 20 00 00|00 00 20 2c) cmpdi r0,0
.*: (7c 60 1b 78|78 1b 60 7c) mr r0,r3
.*: (2c 2b 00 00|00 00 2b 2c) cmpdi r11,0
.*: (7c 6c 6a 14|14 6a 6c 7c) add r3,r12,r13
.*: (4d 82 00 20|20 00 82 4d) beqlr
.*: (4d 82 00 20|20 00 82 4d) beqlr *
.*: (7c 03 03 78|78 03 03 7c) mr r3,r0
.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
.*: (f9 61 00 20|20 00 61 f9) std r11,32\(r1\)
.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
.*: (f8 01 00 20|20 00 01 f8) std r0,32\(r1\)
.*: (f8 41 00 28|28 00 41 f8) std r2,40\(r1\)
.*: (e9 82 80 70|70 80 82 e9) ld r12,-32656\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (e8 42 80 78|78 80 42 e8) ld r2,-32648\(r2\)
.*: (4e 80 04 21|21 04 80 4e) bctrl
.*: (e8 41 00 28|28 00 41 e8) ld r2,40\(r1\)
.*: (e9 61 00 20|20 00 61 e9) ld r11,32\(r1\)
.*: (7d 68 03 a6|a6 03 68 7d) mtlr r11
.*: (e8 01 00 20|20 00 01 e8) ld r0,32\(r1\)
.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
.*: (4e 80 00 20|20 00 80 4e) blr
.* <\._start>:

14
ld/testsuite/ld-powerpc/tlsopt5.d
View file

@ -16,22 +16,22 @@ Disassembly of section \.text:
\.\.\.
.* <.*\.plt_call\.__tls_get_addr_opt@@GLIBC_2\.22>:
.*: (00 00 63 e9|e9 63 00 00) ld r11,0\(r3\)
.*: (00 00 03 e8|e8 03 00 00) ld r0,0\(r3\)
.*: (08 00 83 e9|e9 83 00 08) ld r12,8\(r3\)
.*: (00 00 20 2c|2c 20 00 00) cmpdi r0,0
.*: (78 1b 60 7c|7c 60 1b 78) mr r0,r3
.*: (00 00 2b 2c|2c 2b 00 00) cmpdi r11,0
.*: (14 6a 6c 7c|7c 6c 6a 14) add r3,r12,r13
.*: (20 00 82 4d|4d 82 00 20) beqlr
.*: (20 00 82 4d|4d 82 00 20) beqlr *
.*: (78 03 03 7c|7c 03 03 78) mr r3,r0
.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
.*: (08 00 61 f9|f9 61 00 08) std r11,8\(r1\)
.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
.*: (08 00 01 f8|f8 01 00 08) std r0,8\(r1\)
.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
.*: (30 80 82 e9|e9 82 80 30) ld r12,-32720\(r2\)
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
.*: (21 04 80 4e|4e 80 04 21) bctrl
.*: (18 00 41 e8|e8 41 00 18) ld r2,24\(r1\)
.*: (08 00 61 e9|e9 61 00 08) ld r11,8\(r1\)
.*: (a6 03 68 7d|7d 68 03 a6) mtlr r11
.*: (08 00 01 e8|e8 01 00 08) ld r0,8\(r1\)
.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
.*: (20 00 80 4e|4e 80 00 20) blr
\.\.\.