gas/
2008-12-20 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (_i386_insn): Add swap_operand. (parse_insn): Handle ".s". (match_template): Handle swap_operand. * doc/c-i386.texi: Document .s suffix. gas/testsuite/ 2008-12-20 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts, sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel, x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel. * gas/i386/opts.d: New. * gas/i386/opts-intel.d: Likewise. * gas/i386/opts.s: Likewise. * gas/i386/sse2avx-opts.d: Likewise. * gas/i386/sse2avx-opts-intel.d: Likewise. * gas/i386/x86-64-opts.d: Likewise. * gas/i386/x86-64-opts-intel.d: Likewise. * gas/i386/x86-64-opts.s: Likewise. * gas/i386/x86-64-sse2avx-opts.d: Likewise. * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise. opcodes/ 2008-12-20 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (EbS): New. (EvS): Likewise. (EMS): Likewise. (EXqS): Likewise. (EXxS): Likewise. (b_swap_mode): Likewise. (v_swap_mode): Likewise. (q_swap_mode): Likewise. (x_swap_mode): Likewise. (v_mode): Updated. (w_mode): Likewise. (t_mode): Likewise. (xmm_mode): Likewise. (swap_operand): Likewise. (dis386): Use EbS on movB. Use EvS on moveS. (dis386_twobyte): Use EXxS on movapX. (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa, vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq. (vex_table): Use EXxS on vmovapX. (vex_len_table): Use EXqS on vmovq. (intel_operand_size): Handle b_swap_mode, v_swap_mode, q_swap_mode and x_swap_mode. (OP_E_register): Handle b_swap_mode and v_swap_mode. (OP_EM): Handle v_swap_mode. (OP_EX): x_swap_mode and q_swap_mode. * i386-gen.c (opcode_modifiers): Add S. * i386-opc.h (S): New. (Modrm): Updated. (i386_opcode_modifier): Add s. * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq, movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq. * i386-tbl.h: Regenerated.
This commit is contained in:
H.J. Lu
parent
257385246e
commit
b6169b206a
21 changed files with 8819 additions and 7477 deletions
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@ -1,3 +1,11 @@
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2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (_i386_insn): Add swap_operand.
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(parse_insn): Handle ".s".
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(match_template): Handle swap_operand.
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* doc/c-i386.texi: Document .s suffix.
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2008-12-20 Hans-Peter Nilsson <hp@axis.com>
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* config/tc-cris.c (cris_process_instruction): Handle
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@ -279,6 +279,9 @@ struct _i386_insn
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sib_byte sib;
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drex_byte drex;
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vex_prefix vex;
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/* Swap operand in encoding. */
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unsigned int swap_operand : 1;
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};
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typedef struct _i386_insn i386_insn;
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@ -2908,6 +2911,7 @@ parse_insn (char *line, char *mnemonic)
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char *mnem_p;
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int supported;
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const template *t;
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char *dot_p = NULL;
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/* Non-zero if we found a prefix only acceptable with string insns. */
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const char *expecting_string_instruction = NULL;
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@ -2917,6 +2921,8 @@ parse_insn (char *line, char *mnemonic)
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mnem_p = mnemonic;
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while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
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{
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if (*mnem_p == '.')
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dot_p = mnem_p;
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mnem_p++;
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if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
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{
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@ -2988,8 +2994,24 @@ parse_insn (char *line, char *mnemonic)
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break;
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}
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if (!current_templates && dot_p)
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{
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if (mnem_p - 2 == dot_p)
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{
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/* Check if we should swap operand in encoding. */
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if (dot_p[1] == 's')
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i.swap_operand = 1;
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else
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goto check_suffix;
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mnem_p = dot_p;
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*dot_p = '\0';
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current_templates = hash_find (op_hash, mnemonic);
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}
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}
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if (!current_templates)
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{
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check_suffix:
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/* See if we can get a match by trimming off a suffix. */
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switch (mnem_p[-1])
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{
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@ -3712,6 +3734,16 @@ match_template (void)
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&& operand_type_equal (&i.types [0], &acc32)
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&& operand_type_equal (&i.types [1], &acc32))
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continue;
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if (i.swap_operand)
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{
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/* If we swap operand in encoding, we either match
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the next one or reverse direction of operands. */
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if (t->opcode_modifier.s)
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continue;
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else if (t->opcode_modifier.d)
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goto check_reverse;
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}
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case 3:
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case 4:
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case 5:
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@ -3728,6 +3760,7 @@ match_template (void)
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if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
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continue;
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check_reverse:
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/* Try reversing direction of operands. */
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overlap0 = operand_type_and (i.types[0], operand_types[1]);
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overlap1 = operand_type_and (i.types[1], operand_types[0]);
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@ -14,7 +14,7 @@
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@end ifclear
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@cindex i386 support
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@cindex i80306 support
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@cindex i80386 support
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@cindex x86-64 support
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The i386 version @code{@value{AS}} supports both the original Intel 386
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@ -353,6 +353,13 @@ thus, are @samp{bl} (from byte to long), @samp{bw} (from byte to word),
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@samp{wq} (from word to quadruple word), and @samp{lq} (from long to
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quadruple word).
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@cindex encoding options, i386
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@cindex encoding options, x86-64
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Different encoding options can be specified via optional mnemonic
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suffix. @samp{.s} suffix swaps 2 register operands in encoding when
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moving from one register to another.
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@cindex conversion instructions, i386
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@cindex i386 conversion instructions
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@cindex conversion instructions, x86-64
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@ -1,3 +1,20 @@
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2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts,
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sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel,
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x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel.
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* gas/i386/opts.d: New.
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* gas/i386/opts-intel.d: Likewise.
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* gas/i386/opts.s: Likewise.
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* gas/i386/sse2avx-opts.d: Likewise.
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* gas/i386/sse2avx-opts-intel.d: Likewise.
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* gas/i386/x86-64-opts.d: Likewise.
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* gas/i386/x86-64-opts-intel.d: Likewise.
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* gas/i386/x86-64-opts.s: Likewise.
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* gas/i386/x86-64-sse2avx-opts.d: Likewise.
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* gas/i386/x86-64-sse2avx-opts-intel.d: Likewise.
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2008-12-20 Hans-Peter Nilsson <hp@axis.com>
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* gas/cris/rd-tls-1.s, gas/cris/rd-tls-1.d: Test :IE and
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@ -140,6 +140,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "arch-avx-1"
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run_list_test "arch-avx-1-1" "-march=generic32+avx -I${srcdir}/$subdir -al"
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run_list_test "arch-avx-1-2" "-march=generic32+aes -I${srcdir}/$subdir -al"
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run_dump_test "opts"
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run_dump_test "opts-intel"
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run_dump_test "sse2avx-opts"
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run_dump_test "sse2avx-opts-intel"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -293,6 +297,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-ept"
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run_dump_test "x86-64-ept-intel"
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run_list_test "x86-64-inval-ept" "-al"
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run_dump_test "x86-64-opts"
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run_dump_test "x86-64-opts-intel"
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run_dump_test "x86-64-sse2avx-opts"
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run_dump_test "x86-64-sse2avx-opts-intel"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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113
gas/testsuite/gas/i386/opts-intel.d
Normal file
113
gas/testsuite/gas/i386/opts-intel.d
Normal file
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@ -0,0 +1,113 @@
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#objdump: -drwMintel,suffix
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#name: encoding option (Intel mode)
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#source: opts.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 88 d1 mov cl,dl
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[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
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[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
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[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
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[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
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[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
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[ ]*[a-f0-9]+: 88 d1 mov cl,dl
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[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
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[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
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[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
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[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
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[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
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[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
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[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
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[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
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[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
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[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
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[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
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[ ]*[a-f0-9]+: 88 d1 mov cl,dl
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[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
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[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
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[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
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[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
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[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
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[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
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[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
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[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
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[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
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[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
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[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
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[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
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[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
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[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
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[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
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[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
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[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
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[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
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[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
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[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
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[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
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[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
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[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
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#pass
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112
gas/testsuite/gas/i386/opts.d
Normal file
112
gas/testsuite/gas/i386/opts.d
Normal file
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@ -0,0 +1,112 @@
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#objdump: -drwMsuffix
|
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#name: encoding option
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.*: +file format .*
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Disassembly of section .text:
|
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|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
#pass
|
||||
125
gas/testsuite/gas/i386/opts.s
Normal file
125
gas/testsuite/gas/i386/opts.s
Normal file
|
|
@ -0,0 +1,125 @@
|
|||
# Check instructions with encoding options
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
# Tests for op reg, reg
|
||||
mov %dl,%cl
|
||||
mov.s %dl,%cl
|
||||
mov %dx,%cx
|
||||
mov.s %dx,%cx
|
||||
mov %edx,%ecx
|
||||
mov.s %edx,%ecx
|
||||
movb %dl,%cl
|
||||
movb.s %dl,%cl
|
||||
movw %dx,%cx
|
||||
movw.s %dx,%cx
|
||||
movl %edx,%ecx
|
||||
movl.s %edx,%ecx
|
||||
|
||||
# Tests for op ymm, ymm
|
||||
vmovapd %ymm4,%ymm6
|
||||
vmovapd.s %ymm4,%ymm6
|
||||
vmovaps %ymm4,%ymm6
|
||||
vmovaps.s %ymm4,%ymm6
|
||||
vmovdqa %ymm4,%ymm6
|
||||
vmovdqa.s %ymm4,%ymm6
|
||||
vmovdqu %ymm4,%ymm6
|
||||
vmovdqu.s %ymm4,%ymm6
|
||||
vmovupd %ymm4,%ymm6
|
||||
vmovupd.s %ymm4,%ymm6
|
||||
vmovups %ymm4,%ymm6
|
||||
vmovups.s %ymm4,%ymm6
|
||||
|
||||
# Tests for op xmm, xmm
|
||||
movapd %xmm4,%xmm6
|
||||
movapd.s %xmm4,%xmm6
|
||||
movaps %xmm4,%xmm6
|
||||
movaps.s %xmm4,%xmm6
|
||||
movdqa %xmm4,%xmm6
|
||||
movdqa.s %xmm4,%xmm6
|
||||
movdqu %xmm4,%xmm6
|
||||
movdqu.s %xmm4,%xmm6
|
||||
movq %xmm4,%xmm6
|
||||
movq.s %xmm4,%xmm6
|
||||
movupd %xmm4,%xmm6
|
||||
movupd.s %xmm4,%xmm6
|
||||
movups %xmm4,%xmm6
|
||||
movups.s %xmm4,%xmm6
|
||||
vmovapd %xmm4,%xmm6
|
||||
vmovapd.s %xmm4,%xmm6
|
||||
vmovaps %xmm4,%xmm6
|
||||
vmovaps.s %xmm4,%xmm6
|
||||
vmovdqa %xmm4,%xmm6
|
||||
vmovdqa.s %xmm4,%xmm6
|
||||
vmovdqu %xmm4,%xmm6
|
||||
vmovdqu.s %xmm4,%xmm6
|
||||
vmovq %xmm4,%xmm6
|
||||
vmovq.s %xmm4,%xmm6
|
||||
vmovupd %xmm4,%xmm6
|
||||
vmovupd.s %xmm4,%xmm6
|
||||
vmovups %xmm4,%xmm6
|
||||
vmovups.s %xmm4,%xmm6
|
||||
|
||||
# Tests for op mm, mm
|
||||
movq %mm0,%mm4
|
||||
movq.s %mm0,%mm4
|
||||
|
||||
.intel_syntax noprefix
|
||||
|
||||
# Tests for op reg, reg
|
||||
mov cl,dl
|
||||
mov.s cl,dl
|
||||
mov cx,dx
|
||||
mov.s cx,dx
|
||||
mov ecx,edx
|
||||
mov.s ecx,edx
|
||||
|
||||
# Tests for op ymm, ymm
|
||||
vmovapd ymm6,ymm4
|
||||
vmovapd.s ymm6,ymm4
|
||||
vmovaps ymm6,ymm4
|
||||
vmovaps.s ymm6,ymm4
|
||||
vmovdqa ymm6,ymm4
|
||||
vmovdqa.s ymm6,ymm4
|
||||
vmovdqu ymm6,ymm4
|
||||
vmovdqu.s ymm6,ymm4
|
||||
vmovupd ymm6,ymm4
|
||||
vmovupd.s ymm6,ymm4
|
||||
vmovups ymm6,ymm4
|
||||
vmovups.s ymm6,ymm4
|
||||
|
||||
# Tests for op xmm, xmm
|
||||
movapd xmm6,xmm4
|
||||
movapd.s xmm6,xmm4
|
||||
movaps xmm6,xmm4
|
||||
movaps.s xmm6,xmm4
|
||||
movdqa xmm6,xmm4
|
||||
movdqa.s xmm6,xmm4
|
||||
movdqu xmm6,xmm4
|
||||
movdqu.s xmm6,xmm4
|
||||
movq xmm6,xmm4
|
||||
movq.s xmm6,xmm4
|
||||
movupd xmm6,xmm4
|
||||
movupd.s xmm6,xmm4
|
||||
movups xmm6,xmm4
|
||||
movups.s xmm6,xmm4
|
||||
vmovapd xmm6,xmm4
|
||||
vmovapd.s xmm6,xmm4
|
||||
vmovaps xmm6,xmm4
|
||||
vmovaps.s xmm6,xmm4
|
||||
vmovdqa xmm6,xmm4
|
||||
vmovdqa.s xmm6,xmm4
|
||||
vmovdqu xmm6,xmm4
|
||||
vmovdqu.s xmm6,xmm4
|
||||
vmovq xmm6,xmm4
|
||||
vmovq.s xmm6,xmm4
|
||||
vmovupd xmm6,xmm4
|
||||
vmovupd.s xmm6,xmm4
|
||||
vmovups xmm6,xmm4
|
||||
vmovups.s xmm6,xmm4
|
||||
|
||||
# Tests for op mm, mm
|
||||
movq mm4,mm0
|
||||
movq.s mm4,mm0
|
||||
114
gas/testsuite/gas/i386/sse2avx-opts-intel.d
Normal file
114
gas/testsuite/gas/i386/sse2avx-opts-intel.d
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
#as: -msse2avx
|
||||
#objdump: -drwMintel,suffix
|
||||
#name: encoding option with -msse2avx (Intel mode)
|
||||
#source: opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
|
||||
#pass
|
||||
114
gas/testsuite/gas/i386/sse2avx-opts.d
Normal file
114
gas/testsuite/gas/i386/sse2avx-opts.d
Normal file
|
|
@ -0,0 +1,114 @@
|
|||
#as: -msse2avx
|
||||
#objdump: -drwMsuffix
|
||||
#name: encoding option with -msse2avx
|
||||
#source: opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
#pass
|
||||
119
gas/testsuite/gas/i386/x86-64-opts-intel.d
Normal file
119
gas/testsuite/gas/i386/x86-64-opts-intel.d
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
#objdump: -drwMintel,suffix
|
||||
#name: x86-64 encoding option (Intel mode)
|
||||
#source: x86-64-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: 66 0f 28 f4 movapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 28 f4 movaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 29 e6 movaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f4 movq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 10 f4 movupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 10 f4 movups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 11 e6 movups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
|
||||
#pass
|
||||
118
gas/testsuite/gas/i386/x86-64-opts.d
Normal file
118
gas/testsuite/gas/i386/x86-64-opts.d
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
#objdump: -drwMsuffix
|
||||
#name: x86-64 encoding option
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: 66 0f 28 f4 movapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 29 e6 movapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 28 f4 movaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 29 e6 movaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 6f f4 movdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 7f e6 movdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 6f f4 movdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7f e6 movdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: f3 0f 7e f4 movq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f d6 e6 movq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 10 f4 movupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 66 0f 11 e6 movupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 10 f4 movups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 11 e6 movups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
#pass
|
||||
131
gas/testsuite/gas/i386/x86-64-opts.s
Normal file
131
gas/testsuite/gas/i386/x86-64-opts.s
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
# Check 64bit instructions with encoding options
|
||||
|
||||
.allow_index_reg
|
||||
.text
|
||||
_start:
|
||||
|
||||
# Tests for op reg, reg
|
||||
mov %dl,%cl
|
||||
mov.s %dl,%cl
|
||||
mov %dx,%cx
|
||||
mov.s %dx,%cx
|
||||
mov %edx,%ecx
|
||||
mov.s %edx,%ecx
|
||||
movb %dl,%cl
|
||||
movb.s %dl,%cl
|
||||
movw %dx,%cx
|
||||
movw.s %dx,%cx
|
||||
movl %edx,%ecx
|
||||
movl.s %edx,%ecx
|
||||
mov %rdx,%rcx
|
||||
mov.s %rdx,%rcx
|
||||
movq %rdx,%rcx
|
||||
movq.s %rdx,%rcx
|
||||
|
||||
# Tests for op ymm, ymm
|
||||
vmovapd %ymm4,%ymm6
|
||||
vmovapd.s %ymm4,%ymm6
|
||||
vmovaps %ymm4,%ymm6
|
||||
vmovaps.s %ymm4,%ymm6
|
||||
vmovdqa %ymm4,%ymm6
|
||||
vmovdqa.s %ymm4,%ymm6
|
||||
vmovdqu %ymm4,%ymm6
|
||||
vmovdqu.s %ymm4,%ymm6
|
||||
vmovupd %ymm4,%ymm6
|
||||
vmovupd.s %ymm4,%ymm6
|
||||
vmovups %ymm4,%ymm6
|
||||
vmovups.s %ymm4,%ymm6
|
||||
|
||||
# Tests for op xmm, xmm
|
||||
movapd %xmm4,%xmm6
|
||||
movapd.s %xmm4,%xmm6
|
||||
movaps %xmm4,%xmm6
|
||||
movaps.s %xmm4,%xmm6
|
||||
movdqa %xmm4,%xmm6
|
||||
movdqa.s %xmm4,%xmm6
|
||||
movdqu %xmm4,%xmm6
|
||||
movdqu.s %xmm4,%xmm6
|
||||
movq %xmm4,%xmm6
|
||||
movq.s %xmm4,%xmm6
|
||||
movupd %xmm4,%xmm6
|
||||
movupd.s %xmm4,%xmm6
|
||||
movups %xmm4,%xmm6
|
||||
movups.s %xmm4,%xmm6
|
||||
vmovapd %xmm4,%xmm6
|
||||
vmovapd.s %xmm4,%xmm6
|
||||
vmovaps %xmm4,%xmm6
|
||||
vmovaps.s %xmm4,%xmm6
|
||||
vmovdqa %xmm4,%xmm6
|
||||
vmovdqa.s %xmm4,%xmm6
|
||||
vmovdqu %xmm4,%xmm6
|
||||
vmovdqu.s %xmm4,%xmm6
|
||||
vmovq %xmm4,%xmm6
|
||||
vmovq.s %xmm4,%xmm6
|
||||
vmovupd %xmm4,%xmm6
|
||||
vmovupd.s %xmm4,%xmm6
|
||||
vmovups %xmm4,%xmm6
|
||||
vmovups.s %xmm4,%xmm6
|
||||
|
||||
# Tests for op mm, mm
|
||||
movq %mm0,%mm4
|
||||
movq.s %mm0,%mm4
|
||||
|
||||
.intel_syntax noprefix
|
||||
|
||||
# Tests for op reg, reg
|
||||
mov cl,dl
|
||||
mov.s cl,dl
|
||||
mov cx,dx
|
||||
mov.s cx,dx
|
||||
mov ecx,edx
|
||||
mov.s ecx,edx
|
||||
mov rcx,rdx
|
||||
mov.s rcx,rdx
|
||||
|
||||
# Tests for op ymm, ymm
|
||||
vmovapd ymm6,ymm4
|
||||
vmovapd.s ymm6,ymm4
|
||||
vmovaps ymm6,ymm4
|
||||
vmovaps.s ymm6,ymm4
|
||||
vmovdqa ymm6,ymm4
|
||||
vmovdqa.s ymm6,ymm4
|
||||
vmovdqu ymm6,ymm4
|
||||
vmovdqu.s ymm6,ymm4
|
||||
vmovupd ymm6,ymm4
|
||||
vmovupd.s ymm6,ymm4
|
||||
vmovups ymm6,ymm4
|
||||
vmovups.s ymm6,ymm4
|
||||
|
||||
# Tests for op xmm, xmm
|
||||
movapd xmm6,xmm4
|
||||
movapd.s xmm6,xmm4
|
||||
movaps xmm6,xmm4
|
||||
movaps.s xmm6,xmm4
|
||||
movdqa xmm6,xmm4
|
||||
movdqa.s xmm6,xmm4
|
||||
movdqu xmm6,xmm4
|
||||
movdqu.s xmm6,xmm4
|
||||
movq xmm6,xmm4
|
||||
movq.s xmm6,xmm4
|
||||
movupd xmm6,xmm4
|
||||
movupd.s xmm6,xmm4
|
||||
movups xmm6,xmm4
|
||||
movups.s xmm6,xmm4
|
||||
vmovapd xmm6,xmm4
|
||||
vmovapd.s xmm6,xmm4
|
||||
vmovaps xmm6,xmm4
|
||||
vmovaps.s xmm6,xmm4
|
||||
vmovdqa xmm6,xmm4
|
||||
vmovdqa.s xmm6,xmm4
|
||||
vmovdqu xmm6,xmm4
|
||||
vmovdqu.s xmm6,xmm4
|
||||
vmovq xmm6,xmm4
|
||||
vmovq.s xmm6,xmm4
|
||||
vmovupd xmm6,xmm4
|
||||
vmovupd.s xmm6,xmm4
|
||||
vmovups xmm6,xmm4
|
||||
vmovups.s xmm6,xmm4
|
||||
|
||||
# Tests for op mm, mm
|
||||
movq mm4,mm0
|
||||
movq.s mm4,mm0
|
||||
120
gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
Normal file
120
gas/testsuite/gas/i386/x86-64-sse2avx-opts-intel.d
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
#as: -msse2avx
|
||||
#objdump: -drwMintel,suffix
|
||||
#name: x86-64 encoding option with -msse2avx (Intel mode)
|
||||
#source: x86-64-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
|
||||
[ ]*[a-f0-9]+: 88 d1 mov cl,dl
|
||||
[ ]*[a-f0-9]+: 8a ca mov.s cl,dl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 mov cx,dx
|
||||
[ ]*[a-f0-9]+: 66 8b ca mov.s cx,dx
|
||||
[ ]*[a-f0-9]+: 89 d1 mov ecx,edx
|
||||
[ ]*[a-f0-9]+: 8b ca mov.s ecx,edx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 mov rcx,rdx
|
||||
[ ]*[a-f0-9]+: 48 8b ca mov.s rcx,rdx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s ymm6,ymm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s xmm6,xmm4
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq mm4,mm0
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s mm4,mm0
|
||||
#pass
|
||||
120
gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
Normal file
120
gas/testsuite/gas/i386/x86-64-sse2avx-opts.d
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
#as: -msse2avx
|
||||
#objdump: -drwMsuffix
|
||||
#name: x86-64 encoding option with -msse2avx
|
||||
#source: x86-64-opts.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
|
||||
0+ <_start>:
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 88 d1 movb %dl,%cl
|
||||
[ ]*[a-f0-9]+: 8a ca movb.s %dl,%cl
|
||||
[ ]*[a-f0-9]+: 66 89 d1 movw %dx,%cx
|
||||
[ ]*[a-f0-9]+: 66 8b ca movw.s %dx,%cx
|
||||
[ ]*[a-f0-9]+: 89 d1 movl %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 8b ca movl.s %edx,%ecx
|
||||
[ ]*[a-f0-9]+: 48 89 d1 movq %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: 48 8b ca movq.s %rdx,%rcx
|
||||
[ ]*[a-f0-9]+: c5 fd 28 f4 vmovapd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 29 e6 vmovapd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 28 f4 vmovaps %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 29 e6 vmovaps.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 6f f4 vmovdqa %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 7f e6 vmovdqa.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 6f f4 vmovdqu %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fe 7f e6 vmovdqu.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 10 f4 vmovupd %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fd 11 e6 vmovupd.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 10 f4 vmovups %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 fc 11 e6 vmovups.s %ymm4,%ymm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 28 f4 vmovapd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 29 e6 vmovapd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 28 f4 vmovaps %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 29 e6 vmovaps.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 6f f4 vmovdqa %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 7f e6 vmovdqa.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 6f f4 vmovdqu %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7f e6 vmovdqu.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 fa 7e f4 vmovq %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 d6 e6 vmovq.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 10 f4 vmovupd %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f9 11 e6 vmovupd.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 10 f4 vmovups %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: c5 f8 11 e6 vmovups.s %xmm4,%xmm6
|
||||
[ ]*[a-f0-9]+: 0f 6f e0 movq %mm0,%mm4
|
||||
[ ]*[a-f0-9]+: 0f 7f c4 movq.s %mm0,%mm4
|
||||
#pass
|
||||
|
|
@ -1,3 +1,41 @@
|
|||
2008-12-20 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (EbS): New.
|
||||
(EvS): Likewise.
|
||||
(EMS): Likewise.
|
||||
(EXqS): Likewise.
|
||||
(EXxS): Likewise.
|
||||
(b_swap_mode): Likewise.
|
||||
(v_swap_mode): Likewise.
|
||||
(q_swap_mode): Likewise.
|
||||
(x_swap_mode): Likewise.
|
||||
(v_mode): Updated.
|
||||
(w_mode): Likewise.
|
||||
(t_mode): Likewise.
|
||||
(xmm_mode): Likewise.
|
||||
(swap_operand): Likewise.
|
||||
(dis386): Use EbS on movB. Use EvS on moveS.
|
||||
(dis386_twobyte): Use EXxS on movapX.
|
||||
(prefix_table): Use EXxS on movups, movupd, movdqu, movdqa,
|
||||
vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq.
|
||||
(vex_table): Use EXxS on vmovapX.
|
||||
(vex_len_table): Use EXqS on vmovq.
|
||||
(intel_operand_size): Handle b_swap_mode, v_swap_mode,
|
||||
q_swap_mode and x_swap_mode.
|
||||
(OP_E_register): Handle b_swap_mode and v_swap_mode.
|
||||
(OP_EM): Handle v_swap_mode.
|
||||
(OP_EX): x_swap_mode and q_swap_mode.
|
||||
|
||||
* i386-gen.c (opcode_modifiers): Add S.
|
||||
|
||||
* i386-opc.h (S): New.
|
||||
(Modrm): Updated.
|
||||
(i386_opcode_modifier): Add s.
|
||||
|
||||
* i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq,
|
||||
movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq.
|
||||
* i386-tbl.h: Regenerated.
|
||||
|
||||
2008-12-18 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* i386-dis.c (mnemonicendp): New.
|
||||
|
|
|
|||
|
|
@ -240,7 +240,9 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define XX { NULL, 0 }
|
||||
|
||||
#define Eb { OP_E, b_mode }
|
||||
#define EbS { OP_E, b_swap_mode }
|
||||
#define Ev { OP_E, v_mode }
|
||||
#define EvS { OP_E, v_swap_mode }
|
||||
#define Ed { OP_E, d_mode }
|
||||
#define Edq { OP_E, dq_mode }
|
||||
#define Edqw { OP_E, dqw_mode }
|
||||
|
|
@ -355,12 +357,15 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
#define XM { OP_XMM, 0 }
|
||||
#define XMM { OP_XMM, xmm_mode }
|
||||
#define EM { OP_EM, v_mode }
|
||||
#define EMS { OP_EM, v_swap_mode }
|
||||
#define EMd { OP_EM, d_mode }
|
||||
#define EMx { OP_EM, x_mode }
|
||||
#define EXw { OP_EX, w_mode }
|
||||
#define EXd { OP_EX, d_mode }
|
||||
#define EXq { OP_EX, q_mode }
|
||||
#define EXqS { OP_EX, q_swap_mode }
|
||||
#define EXx { OP_EX, x_mode }
|
||||
#define EXxS { OP_EX, x_swap_mode }
|
||||
#define EXxmm { OP_EX, xmm_mode }
|
||||
#define EXxmmq { OP_EX, xmmq_mode }
|
||||
#define EXymmq { OP_EX, ymmq_mode }
|
||||
|
|
@ -412,20 +417,28 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
|
|||
|
||||
/* byte operand */
|
||||
#define b_mode 1
|
||||
/* byte operand with operand swapped */
|
||||
#define b_swap_mode (b_mode + 1)
|
||||
/* operand size depends on prefixes */
|
||||
#define v_mode (b_mode + 1)
|
||||
#define v_mode (b_swap_mode + 1)
|
||||
/* operand size depends on prefixes with operand swapped */
|
||||
#define v_swap_mode (v_mode + 1)
|
||||
/* word operand */
|
||||
#define w_mode (v_mode + 1)
|
||||
#define w_mode (v_swap_mode + 1)
|
||||
/* double word operand */
|
||||
#define d_mode (w_mode + 1)
|
||||
/* quad word operand */
|
||||
#define q_mode (d_mode + 1)
|
||||
/* quad word operand with operand swapped */
|
||||
#define q_swap_mode (q_mode + 1)
|
||||
/* ten-byte operand */
|
||||
#define t_mode (q_mode + 1)
|
||||
#define t_mode (q_swap_mode + 1)
|
||||
/* 16-byte XMM or 32-byte YMM operand */
|
||||
#define x_mode (t_mode + 1)
|
||||
/* 16-byte XMM or 32-byte YMM operand with operand swapped */
|
||||
#define x_swap_mode (x_mode + 1)
|
||||
/* 16-byte XMM operand */
|
||||
#define xmm_mode (x_mode + 1)
|
||||
#define xmm_mode (x_swap_mode + 1)
|
||||
/* 16-byte XMM or quad word operand */
|
||||
#define xmmq_mode (xmm_mode + 1)
|
||||
/* 32-byte YMM or quad word operand */
|
||||
|
|
@ -1458,8 +1471,8 @@ static const struct dis386 dis386[] = {
|
|||
/* 88 */
|
||||
{ "movB", { Eb, Gb } },
|
||||
{ "movS", { Ev, Gv } },
|
||||
{ "movB", { Gb, Eb } },
|
||||
{ "movS", { Gv, Ev } },
|
||||
{ "movB", { Gb, EbS } },
|
||||
{ "movS", { Gv, EvS } },
|
||||
{ "movD", { Sv, Sw } },
|
||||
{ MOD_TABLE (MOD_8D) },
|
||||
{ "movD", { Sw, Sv } },
|
||||
|
|
@ -1640,7 +1653,7 @@ static const struct dis386 dis386_twobyte[] = {
|
|||
{ "(bad)", { XX } },
|
||||
/* 28 */
|
||||
{ "movapX", { XM, EXx } },
|
||||
{ "movapX", { EXx, XM } },
|
||||
{ "movapX", { EXxS, XM } },
|
||||
{ PREFIX_TABLE (PREFIX_0F2A) },
|
||||
{ PREFIX_TABLE (PREFIX_0F2B) },
|
||||
{ PREFIX_TABLE (PREFIX_0F2C) },
|
||||
|
|
@ -2413,9 +2426,9 @@ static const struct dis386 prefix_table[][4] = {
|
|||
|
||||
/* PREFIX_0F11 */
|
||||
{
|
||||
{ "movups", { EXx, XM } },
|
||||
{ "movups", { EXxS, XM } },
|
||||
{ "movss", { EXd, XM } },
|
||||
{ "movupd", { EXx, XM } },
|
||||
{ "movupd", { EXxS, XM } },
|
||||
{ "movsd", { EXq, XM } },
|
||||
},
|
||||
|
||||
|
|
@ -2685,9 +2698,9 @@ static const struct dis386 prefix_table[][4] = {
|
|||
|
||||
/* PREFIX_0F7F */
|
||||
{
|
||||
{ "movq", { EM, MX } },
|
||||
{ "movdqu", { EXx, XM } },
|
||||
{ "movdqa", { EXx, XM } },
|
||||
{ "movq", { EMS, MX } },
|
||||
{ "movdqu", { EXxS, XM } },
|
||||
{ "movdqa", { EXxS, XM } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
|
|
@ -2743,7 +2756,7 @@ static const struct dis386 prefix_table[][4] = {
|
|||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "movq2dq",{ XM, MS } },
|
||||
{ "movq", { EXq, XM } },
|
||||
{ "movq", { EXqS, XM } },
|
||||
{ "movdq2q",{ MX, XS } },
|
||||
},
|
||||
|
||||
|
|
@ -3293,9 +3306,9 @@ static const struct dis386 prefix_table[][4] = {
|
|||
|
||||
/* PREFIX_VEX_11 */
|
||||
{
|
||||
{ "vmovups", { EXx, XM } },
|
||||
{ "vmovups", { EXxS, XM } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_11_P_1) },
|
||||
{ "vmovupd", { EXx, XM } },
|
||||
{ "vmovupd", { EXxS, XM } },
|
||||
{ VEX_LEN_TABLE (VEX_LEN_11_P_3) },
|
||||
},
|
||||
|
||||
|
|
@ -3718,8 +3731,8 @@ static const struct dis386 prefix_table[][4] = {
|
|||
/* PREFIX_VEX_7F */
|
||||
{
|
||||
{ "(bad)", { XX } },
|
||||
{ "vmovdqu", { EXx, XM } },
|
||||
{ "vmovdqa", { EXx, XM } },
|
||||
{ "vmovdqu", { EXxS, XM } },
|
||||
{ "vmovdqa", { EXxS, XM } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
|
|
@ -6989,7 +7002,7 @@ static const struct dis386 vex_table[][256] = {
|
|||
{ "(bad)", { XX } },
|
||||
/* 28 */
|
||||
{ "vmovapX", { XM, EXx } },
|
||||
{ "vmovapX", { EXx, XM } },
|
||||
{ "vmovapX", { EXxS, XM } },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_2A) },
|
||||
{ MOD_TABLE (MOD_VEX_2B) },
|
||||
{ PREFIX_TABLE (PREFIX_VEX_2C) },
|
||||
|
|
@ -8328,7 +8341,7 @@ static const struct dis386 vex_len_table[][2] = {
|
|||
|
||||
/* VEX_LEN_D6_P_2 */
|
||||
{
|
||||
{ "vmovq", { EXq, XM } },
|
||||
{ "vmovq", { EXqS, XM } },
|
||||
{ "(bad)", { XX } },
|
||||
},
|
||||
|
||||
|
|
@ -10723,6 +10736,14 @@ static char *fgrps[][8] = {
|
|||
},
|
||||
};
|
||||
|
||||
static void
|
||||
swap_operand (void)
|
||||
{
|
||||
mnemonicendp[0] = '.';
|
||||
mnemonicendp[1] = 's';
|
||||
mnemonicendp += 2;
|
||||
}
|
||||
|
||||
static void
|
||||
OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED,
|
||||
int sizeflag ATTRIBUTE_UNUSED)
|
||||
|
|
@ -11351,6 +11372,7 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
switch (bytemode)
|
||||
{
|
||||
case b_mode:
|
||||
case b_swap_mode:
|
||||
case dqb_mode:
|
||||
oappend ("BYTE PTR ");
|
||||
break;
|
||||
|
|
@ -11367,6 +11389,7 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
}
|
||||
/* FALLTHRU */
|
||||
case v_mode:
|
||||
case v_swap_mode:
|
||||
case dq_mode:
|
||||
USED_REX (REX_W);
|
||||
if (rex & REX_W)
|
||||
|
|
@ -11396,6 +11419,7 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
oappend ("DWORD PTR ");
|
||||
break;
|
||||
case q_mode:
|
||||
case q_swap_mode:
|
||||
oappend ("QWORD PTR ");
|
||||
break;
|
||||
case m_mode:
|
||||
|
|
@ -11415,6 +11439,7 @@ intel_operand_size (int bytemode, int sizeflag)
|
|||
oappend ("TBYTE PTR ");
|
||||
break;
|
||||
case x_mode:
|
||||
case x_swap_mode:
|
||||
if (need_vex)
|
||||
{
|
||||
switch (vex.length)
|
||||
|
|
@ -11485,9 +11510,14 @@ OP_E_register (int bytemode, int sizeflag)
|
|||
if ((rex & REX_B))
|
||||
reg += 8;
|
||||
|
||||
if ((sizeflag & SUFFIX_ALWAYS)
|
||||
&& (bytemode == b_swap_mode || bytemode == v_swap_mode))
|
||||
swap_operand ();
|
||||
|
||||
switch (bytemode)
|
||||
{
|
||||
case b_mode:
|
||||
case b_swap_mode:
|
||||
USED_REX (0);
|
||||
if (rex)
|
||||
names = names8rex;
|
||||
|
|
@ -11516,6 +11546,7 @@ OP_E_register (int bytemode, int sizeflag)
|
|||
bytemode = v_mode;
|
||||
/* FALLTHRU */
|
||||
case v_mode:
|
||||
case v_swap_mode:
|
||||
case dq_mode:
|
||||
case dqb_mode:
|
||||
case dqd_mode:
|
||||
|
|
@ -11523,7 +11554,9 @@ OP_E_register (int bytemode, int sizeflag)
|
|||
USED_REX (REX_W);
|
||||
if (rex & REX_W)
|
||||
names = names64;
|
||||
else if ((sizeflag & DFLAG) || bytemode != v_mode)
|
||||
else if ((sizeflag & DFLAG)
|
||||
|| (bytemode != v_mode
|
||||
&& bytemode != v_swap_mode))
|
||||
names = names32;
|
||||
else
|
||||
names = names16;
|
||||
|
|
@ -12535,7 +12568,8 @@ OP_EM (int bytemode, int sizeflag)
|
|||
{
|
||||
if (modrm.mod != 3)
|
||||
{
|
||||
if (intel_syntax && bytemode == v_mode)
|
||||
if (intel_syntax
|
||||
&& (bytemode == v_mode || bytemode == v_swap_mode))
|
||||
{
|
||||
bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
|
||||
used_prefixes |= (prefixes & PREFIX_DATA);
|
||||
|
|
@ -12544,6 +12578,9 @@ OP_EM (int bytemode, int sizeflag)
|
|||
return;
|
||||
}
|
||||
|
||||
if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
|
||||
swap_operand ();
|
||||
|
||||
/* Skip mod/rm byte. */
|
||||
MODRM_CHECK;
|
||||
codep++;
|
||||
|
|
@ -12614,6 +12651,10 @@ OP_EX (int bytemode, int sizeflag)
|
|||
else
|
||||
add = 0;
|
||||
|
||||
if ((sizeflag & SUFFIX_ALWAYS)
|
||||
&& (bytemode == x_swap_mode || bytemode == q_swap_mode))
|
||||
swap_operand ();
|
||||
|
||||
/* Skip mod/rm byte. */
|
||||
MODRM_CHECK;
|
||||
codep++;
|
||||
|
|
|
|||
|
|
@ -284,6 +284,7 @@ static bitfield opcode_modifiers[] =
|
|||
{
|
||||
BITFIELD (D),
|
||||
BITFIELD (W),
|
||||
BITFIELD (S),
|
||||
BITFIELD (Modrm),
|
||||
BITFIELD (ShortForm),
|
||||
BITFIELD (Jump),
|
||||
|
|
|
|||
|
|
@ -166,8 +166,10 @@ typedef union i386_cpu_flags
|
|||
#define D 0
|
||||
/* set if operands can be words or dwords encoded the canonical way */
|
||||
#define W (D + 1)
|
||||
/* Swap operand in encoding. */
|
||||
#define S (W + 1)
|
||||
/* insn has a modrm byte. */
|
||||
#define Modrm (W + 1)
|
||||
#define Modrm (S + 1)
|
||||
/* register is in low 3 bits of opcode */
|
||||
#define ShortForm (Modrm + 1)
|
||||
/* special case for jump insns. */
|
||||
|
|
@ -284,6 +286,7 @@ typedef struct i386_opcode_modifier
|
|||
{
|
||||
unsigned int d:1;
|
||||
unsigned int w:1;
|
||||
unsigned int s:1;
|
||||
unsigned int modrm:1;
|
||||
unsigned int shortform:1;
|
||||
unsigned int jump:1;
|
||||
|
|
|
|||
|
|
@ -941,15 +941,15 @@ movq, 2, 0xa0, None, 1, Cpu64, D|W|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSu
|
|||
movq, 2, 0x88, None, 1, Cpu64, D|W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
movq, 2, 0xc6, 0x0, 1, Cpu64, W|Modrm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm32S, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
movq, 2, 0xb0, None, 1, Cpu64, W|ShortForm|Size64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm64, Reg64 }
|
||||
movq, 2, 0xf37e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movq, 2, 0xf37e, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM }
|
||||
movq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
movq, 2, 0xf30f7e, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movq, 2, 0xf30f7e, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movq, 2, 0x660fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movq, 2, 0x660f6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegXMM }
|
||||
movq, 2, 0x660f7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
movq, 2, 0xf6f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
movq, 2, 0xf6f, None, 2, CpuMMX, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX, RegMMX }
|
||||
movq, 2, 0xf7f, None, 2, CpuMMX, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegMMX, Unspecified|Qword|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegMMX }
|
||||
movq, 2, 0xf6e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S, RegMMX }
|
||||
movq, 2, 0xf7e, None, 2, Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMMX, Reg64|Unspecified|Qword|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
|
|
@ -1199,9 +1199,9 @@ minps, 2, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wS
|
|||
minps, 2, 0xf5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
minss, 2, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
minss, 2, 0xf30f5d, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movaps, 2, 0xf28, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movaps, 2, 0xf28, None, 2, CpuSSE, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movaps, 2, 0xf29, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movhlps, 2, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
|
||||
movhlps, 2, 0xf12, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
|
||||
|
|
@ -1227,9 +1227,9 @@ movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No
|
|||
movss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
|
||||
movss, 2, 0xf30f10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movss, 2, 0xf30f11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movups, 2, 0xf10, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movups, 2, 0xf10, None, 2, CpuSSE, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movups, 2, 0xf11, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
mulps, 2, 0x59, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
mulps, 2, 0xf59, None, 2, CpuSSE, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
|
|
@ -1375,9 +1375,9 @@ minpd, 2, 0x665d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_
|
|||
minpd, 2, 0x660f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
minsd, 2, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
minsd, 2, 0xf20f5d, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movapd, 2, 0x660f28, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movapd, 2, 0x660f28, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movapd, 2, 0x660f29, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movhpd, 2, 0x6616, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
|
||||
movhpd, 2, 0x6617, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
|
|
@ -1399,9 +1399,9 @@ movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No
|
|||
movsd, 2, 0xf210, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
|
||||
movsd, 2, 0xf20f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movsd, 2, 0xf20f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movupd, 2, 0x660f10, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movupd, 2, 0x660f10, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movupd, 2, 0x660f11, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
mulpd, 2, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
mulpd, 2, 0x660f59, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
|
|
@ -1455,13 +1455,13 @@ cvttps2dq, 2, 0xf35b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSu
|
|||
cvttps2dq, 2, 0xf30f5b, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
maskmovdqu, 2, 0x66f7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, RegXMM }
|
||||
maskmovdqu, 2, 0x660ff7, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM }
|
||||
movdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movdqa, 2, 0x660f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqa, 2, 0x660f6f, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqa, 2, 0x660f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqu, 2, 0xf30f6f, None, 2, CpuSSE2, S|Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
movdqu, 2, 0xf30f7f, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
movdq2q, 2, 0xf20fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegXMM, RegMMX }
|
||||
movq2dq, 2, 0xf30fd6, None, 2, CpuSSE2, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoAVX, { RegMMX, RegXMM }
|
||||
|
|
@ -2075,12 +2075,12 @@ vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_w
|
|||
vminps, 3, 0x5d, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM, RegYMM }
|
||||
vminsd, 3, 0xf25d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vminss, 3, 0xf35d, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vmovapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovapd, 2, 0x6628, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovapd, 2, 0x6628, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovapd, 2, 0x6629, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
|
||||
vmovaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovaps, 2, 0x28, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovaps, 2, 0x28, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovaps, 2, 0x29, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
|
||||
// vmovd really shouldn't allow for 64bit operand (vmovq is the right
|
||||
|
|
@ -2094,12 +2094,12 @@ vmovd, 2, 0x667e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No
|
|||
vmovd, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { RegXMM, Qword|Reg64|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovddup, 2, 0xf212, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovdqa, 2, 0x666f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovdqa, 2, 0x666f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovdqa, 2, 0x667f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
|
||||
vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovdqu, 2, 0xf36f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovdqu, 2, 0xf36f, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovdqu, 2, 0xf37f, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
|
||||
vmovhlps, 3, 0x12, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
|
||||
|
|
@ -2120,7 +2120,7 @@ vmovntdq, 2, 0x66e7, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf
|
|||
vmovntdqa, 2, 0x662a, None, 1, CpuAVX, Modrm|Vex|Vex0F38|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
|
||||
vmovntpd, 2, 0x662b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
vmovntps, 2, 0x2b, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
vmovq, 2, 0xf37e, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovq, 2, 0xf37e, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovq, 2, 0x66d6, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|NoRex64, { RegXMM, Qword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovq, 2, 0x666e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S, RegXMM }
|
||||
vmovq, 2, 0x667e, None, 1, CpuAVX|Cpu64, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg64|Qword|Unspecified|BaseIndex|Disp8|Disp32|Disp32S }
|
||||
|
|
@ -2134,13 +2134,13 @@ vmovsldup, 2, 0xf312, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf
|
|||
vmovss, 2, 0xf311, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S }
|
||||
vmovss, 2, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S, RegXMM }
|
||||
vmovss, 3, 0xf310, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM }
|
||||
vmovupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovupd, 2, 0x6610, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovupd, 2, 0x6610, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovupd, 2, 0x6611, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
|
||||
vmovups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM }
|
||||
vmovups, 2, 0x10, None, 1, CpuAVX, S|Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM }
|
||||
vmovups, 2, 0x10, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM, RegYMM }
|
||||
vmovups, 2, 0x11, None, 1, CpuAVX, Modrm|Vex|Vex0F|Vex256|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Ymmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegYMM }
|
||||
vmpsadbw, 4, 0x6642, None, 1, CpuAVX, Modrm|Vex|Vex0F3A|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
vmulpd, 3, 0x6659, None, 1, CpuAVX, Modrm|Vex|Vex0F|VexNDS|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex|Disp8|Disp16|Disp32|Disp32S|RegXMM, RegXMM, RegXMM }
|
||||
|
|
|
|||
14852
opcodes/i386-tbl.h
14852
opcodes/i386-tbl.h
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Load diff
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Add table
Reference in a new issue