arc/nps400: Validate address type operands correctly
When we match against an address type operand within an instruction it is important that we match exactly the right address type operand early on, during the opcode selection phase. If we wait until the operand insertion phase to check that we have the correct address operand, then it is too late to select an alternative opcode. This becomes important only when we have multiple opcodes with the same mnemonic, and operand lists that differ only in the type of the address operands. This commit fixes this issue, and adds some example instructions that require this issue to be fixed (the instructions are identical except for the address type operand). gas/ChangeLog: * config/tc-arc.c (find_opcode_match): Use insert function to validate matching address type operands. * testsuite/gas/arc/nps400-10.d: New file. * testsuite/gas/arc/nps400-10.s: New file. opcodes/ChangeLog: * arc-opc.c (arc_flag_operands): Add F_DI14. (arc_flag_classes): Add C_DI14. * arc-nps400-tbl.h: Add new exc instructions.
This commit is contained in:
Andrew Burgess
parent
848ac65968
commit
b437d035dd
7 changed files with 95 additions and 5 deletions
|
|
@ -1,3 +1,10 @@
|
|||
2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
|
||||
|
||||
* config/tc-arc.c (find_opcode_match): Use insert function to
|
||||
validate matching address type operands.
|
||||
* testsuite/gas/arc/nps400-10.d: New file.
|
||||
* testsuite/gas/arc/nps400-10.s: New file.
|
||||
|
||||
2016-11-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
|
||||
|
||||
* config/tc-arm.c (cortex-m33): Declare new processor.
|
||||
|
|
|
|||
|
|
@ -1720,9 +1720,22 @@ find_opcode_match (const struct arc_opcode_hash_entry *entry,
|
|||
switch (operand->flags & ARC_OPERAND_TYPECHECK_MASK)
|
||||
{
|
||||
case ARC_OPERAND_ADDRTYPE:
|
||||
/* Check to be an address type. */
|
||||
if (tok[tokidx].X_op != O_addrtype)
|
||||
goto match_failed;
|
||||
{
|
||||
const char *errmsg = NULL;
|
||||
|
||||
/* Check to be an address type. */
|
||||
if (tok[tokidx].X_op != O_addrtype)
|
||||
goto match_failed;
|
||||
|
||||
/* All address type operands need to have an insert
|
||||
method in order to check that we have the correct
|
||||
address type. */
|
||||
gas_assert (operand->insert != NULL);
|
||||
(*operand->insert) (0, tok[tokidx].X_add_number,
|
||||
&errmsg);
|
||||
if (errmsg != NULL)
|
||||
goto match_failed;
|
||||
}
|
||||
break;
|
||||
|
||||
case ARC_OPERAND_IR:
|
||||
|
|
|
|||
24
gas/testsuite/gas/arc/nps400-10.d
Normal file
24
gas/testsuite/gas/arc/nps400-10.d
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
#as: -mcpu=arc700 -mnps400
|
||||
#objdump: -dr
|
||||
|
||||
.*: +file format .*arc.*
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
[0-9a-f]+ <.*>:
|
||||
0: 4846 0c21 exc r0,r0,\[xa:r2\]
|
||||
4: 4926 0c61 exc r1,r1,\[sd:r1\]
|
||||
8: 4a66 0c81 exc r2,r2,\[xd:r3\]
|
||||
c: 4b26 0c01 exc r3,r3,\[r1\]
|
||||
10: 4c96 4c21 exc\.di\.f r12,r12,\[xa:r12\]
|
||||
14: 4eb6 4c61 exc\.di\.f r14,r14,\[sd:r13\]
|
||||
18: 4dd6 4c81 exc\.di\.f r13,r13,\[xd:r14\]
|
||||
1c: 4ff6 4c01 exc\.di\.f r15,r15,\[r15\]
|
||||
20: 4c16 0c21 exc\.f r12,r12,\[xa:r0\]
|
||||
24: 4e36 0c61 exc\.f r14,r14,\[sd:r1\]
|
||||
28: 4d16 0c81 exc\.f r13,r13,\[xd:r0\]
|
||||
2c: 4f56 0c01 exc\.f r15,r15,\[r2\]
|
||||
30: 4c86 4c21 exc\.di r12,r12,\[xa:r12\]
|
||||
34: 4ec6 4c61 exc\.di r14,r14,\[sd:r14\]
|
||||
38: 4da6 4c81 exc\.di r13,r13,\[xd:r13\]
|
||||
3c: 4fe6 4c01 exc\.di r15,r15,\[r15\]
|
||||
22
gas/testsuite/gas/arc/nps400-10.s
Normal file
22
gas/testsuite/gas/arc/nps400-10.s
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
.text
|
||||
|
||||
;; Atomic Operations: exc
|
||||
exc r0,r0,[xa:r2]
|
||||
exc r1,r1,[sd:r1]
|
||||
exc r2,r2,[xd:r3]
|
||||
exc r3,r3,[r1]
|
||||
|
||||
exc.di.f r12,r12,[xa:r12]
|
||||
exc.di.f r14,r14,[sd:r13]
|
||||
exc.di.f r13,r13,[xd:r14]
|
||||
exc.di.f r15,r15,[r15]
|
||||
|
||||
exc.f r12,r12,[xa:r0]
|
||||
exc.f r14,r14,[sd:r1]
|
||||
exc.f r13,r13,[xd:r0]
|
||||
exc.f r15,r15,[r2]
|
||||
|
||||
exc.di r12,r12,[xa:r12]
|
||||
exc.di r14,r14,[sd:r14]
|
||||
exc.di r13,r13,[xd:r13]
|
||||
exc.di r15,r15,[r15]
|
||||
|
|
@ -1,3 +1,9 @@
|
|||
2016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
|
||||
|
||||
* arc-opc.c (arc_flag_operands): Add F_DI14.
|
||||
(arc_flag_classes): Add C_DI14.
|
||||
* arc-nps400-tbl.h: Add new exc instructions.
|
||||
|
||||
2016-11-03 Graham Markall <graham.markall@embecosm.com>
|
||||
|
||||
* arc-dis.c (arc_insn_length): Return length 8 for instructions with
|
||||
|
|
|
|||
|
|
@ -713,3 +713,17 @@ XLDST_LIKE("xst", 0xe)
|
|||
|
||||
/* dcmac a,[cm:A],[cm:b],size */
|
||||
{ "dcmac", 0x500007c023000000, 0xf80007ffffc00000, ARC_OPCODE_ARC700, PROTOCOL_DECODE, NPS400, { NPS_RA_64, BRAKET, NPS_CM, COLON, NPS_UIMM16_0_64, BRAKETdup, BRAKET, NPS_CM, COLON, NPS_RBdouble_64, BRAKETdup, NPS_PROTO_SIZE }, { 0 }},
|
||||
|
||||
/* Atomic Operations. */
|
||||
|
||||
/* exc<.di><.f> a,a,[xa:b] */
|
||||
{ "exc", 0x48060c21, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XA, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
|
||||
|
||||
/* exc<.di><.f> a,a,[sd:b] */
|
||||
{ "exc", 0x48060c61, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_SD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
|
||||
|
||||
/* exc<.di><.f> a,a,[xd:b] */
|
||||
{ "exc", 0x48060c81, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_XD, COLON, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
|
||||
|
||||
/* exc<.di><.f> a,a,[b] */
|
||||
{ "exc", 0x48060c01, 0xf80fbfff, ARC_OPCODE_ARC700, NONE, NPS400, { NPS_R_DST_3B, NPS_R_SRC1_3B, BRAKET, NPS_R_SRC2_3B, BRAKETdup }, { C_DI14, C_NPS_F }},
|
||||
|
|
|
|||
|
|
@ -1249,7 +1249,9 @@ const struct arc_flag_operand arc_flag_operands[] =
|
|||
{ "di", 1, 1, 5, 1 },
|
||||
#define F_DI11 (F_DI5 + 1)
|
||||
{ "di", 1, 1, 11, 1 },
|
||||
#define F_DI15 (F_DI11 + 1)
|
||||
#define F_DI14 (F_DI11 + 1)
|
||||
{ "di", 1, 1, 14, 1 },
|
||||
#define F_DI15 (F_DI14 + 1)
|
||||
{ "di", 1, 1, 15, 1 },
|
||||
|
||||
/* ARCv2 specific. */
|
||||
|
|
@ -1407,7 +1409,9 @@ const struct arc_flag_class arc_flag_classes[] =
|
|||
|
||||
#define C_DI20 (C_DHARD + 1)
|
||||
{ F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
|
||||
#define C_DI16 (C_DI20 + 1)
|
||||
#define C_DI14 (C_DI20 + 1)
|
||||
{ F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
|
||||
#define C_DI16 (C_DI14 + 1)
|
||||
{ F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
|
||||
#define C_DI26 (C_DI16 + 1)
|
||||
{ F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue