Add Intel Itanium Series 9500 support

bfd/

2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>

	* cpu-ia64-opc.c (ins_cnt6a): New function.
	(ext_cnt6a): Ditto.
	(ins_strd5b): Ditto.
	(ext_strd5b): Ditto.
	(elf64_ia64_operands): Add new operand types.

gas/

2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>

	* config/tc-ia64.c (reg_symbol): Add a new register.
	(indirect_reg): Ditto.
	(pseudo_func): Add new symbolic constants.
	(operand_match): Add new operand types recognition.
	(operand_insn): Add new register recognition.
	(md_begin): Add new register definition.
	(specify_resource): Add new register recognition.

gas/testsuite/

2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>

	* gas/testsuite/gas/ia64/psn.d: New file.
	* gas/testsuite/gas/ia64/psn.s: New file.
	* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
	* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
	* gas/testsuite/gas/ia64/opc-m.d: Ditto.

include/opcode/

2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>

	* ia64.h (ia64_opnd): Add new operand types.

opcodes/

2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>

	* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
	* ia64-gen.c: Promote completer index type to longlong.
	(irf_operand): Add new register recognition.
	(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
	(lookup_specifier): Add new resource recognition.
	(insert_bit_table_ent): Relax abort condition according to the
	changed completer index type.
	(print_dis_table): Fix printf format for completer index.
	* ia64-ic.tbl: Add a new instruction class.
	* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
	* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
	* ia64-opc.h: Define short names for new operand types.
	* ia64-raw.tbl: Add new RAW resource for DAHR register.
	* ia64-waw.tbl: Add new WAW resource for DAHR register.
	* ia64-asmtab.c: Regenerate.

bfd/ChangeLog

@@ -1,3 +1,11 @@
+2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+	* cpu-ia64-opc.c (ins_cnt6a): New function.
+	(ext_cnt6a): Ditto.
+	(ins_strd5b): Ditto.
+	(ext_strd5b): Ditto.
+	(elf64_ia64_operands): Add new operand types.
+
 2012-09-04  H.J. Lu  <hongjiu.lu@intel.com>
 
 	PR binutils/14493

bfd/cpu-ia64-opc.c

@@ -379,6 +379,46 @@ ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
   return 0;
 }
 
+static const char*
+ins_cnt6a (const struct ia64_operand *self, ia64_insn value,
+	    ia64_insn *code)
+{
+  if (value < 1 || value > 64)
+    return "value must be between 1 and 64";
+  return ins_immu (self, value - 1, code);
+}
+
+static const char*
+ext_cnt6a (const struct ia64_operand *self, ia64_insn code,
+	    ia64_insn *valuep)
+{
+  const char *result;
+
+  result = ext_immu (self, code, valuep);
+  if (result)
+    return result;
+
+  *valuep = *valuep + 1;
+  return 0;
+}
+
+static const char*
+ins_strd5b (const struct ia64_operand *self, ia64_insn value,
+	    ia64_insn *code)
+{
+  if (  value & 0x3f )
+    return "value must be a multiple of 64";
+  return ins_imms_scaled (self, value, code, 6);
+}
+
+static const char*
+ext_strd5b (const struct ia64_operand *self, ia64_insn code,
+	    ia64_insn *valuep)
+{
+  return ext_imms_scaled (self, code, valuep, 6);
+}
+
+
 static const char*
 ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
 {
@@ -480,6 +520,8 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "a general register" },
     { REG, ins_reg,   ext_reg,	 "r", {{ 2, 20}}, 0,		/* R3_2 */
       "a general register r0-r3" },
+    { REG, ins_reg,   ext_reg,	 "dahr", {{ 3, 23}}, 0,		/* DAHR */
+      "a dahr register dahr0-7" },
 
     /* memory operands: */
     { IND, ins_reg,   ext_reg,	"",      {{7, 20}}, 0,		/* MR3 */
@@ -504,6 +546,8 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
       "a pmc register" },
     { IND, ins_reg,   ext_reg,	"pmd",   {{7, 20}}, 0,		/* PMD_R3 */
       "a pmd register" },
+    { IND, ins_reg,   ext_reg,	"dahr",  {{7, 20}}, 0,		/* DAHR_R3 */
+      "a dahr register" },
     { IND, ins_reg,   ext_reg,	"rr",    {{7, 20}}, 0,		/* RR_R3 */
       "an rr register" },
 
@@ -568,9 +612,15 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
     { ABS, ins_imms,  ext_imms, 0,				/* IMM14 */
       {{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
       "a 14-bit integer (-8192-8191)" },
+    { ABS, ins_immu,  ext_immu,  0,				/* IMMU16 */
+      {{4,  6}, {11, 12}, { 1, 36}}, UDEC,
+      "a 16-bit unsigned" },
     { ABS, ins_imms1, ext_imms1, 0,				/* IMM17 */
       {{ 7,  6}, { 8, 24}, { 1, 36}}, 0,
       "a 17-bit integer (-65536-65535)" },
+    { ABS, ins_immu,  ext_immu,  0,				/* IMMU19 */
+      {{4,  6}, {14, 12}, { 1, 36}}, UDEC,
+      "a 19-bit unsigned" },
     { ABS, ins_immu,  ext_immu,  0, {{20,  6}, { 1, 36}}, 0,	/* IMMU21 */
       "a 21-bit unsigned" },
     { ABS, ins_imms,  ext_imms,  0,				/* IMM22 */
@@ -613,4 +663,8 @@ const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
 
     { ABS, ins_const, ext_const, 0, {{0, 0}}, 0,		/* LDXMOV */
       "ldxmov target" },
+    { ABS, ins_cnt6a, ext_cnt6a, 0, {{6, 6}}, UDEC,		/* CNT6a */
+      "lfetch count" },
+    { ABS, ins_strd5b, ext_strd5b, 0, {{5, 13}}, SDEC,		/* STRD5b*/
+      "lfetch stride" },
   };

gas/ChangeLog

@@ -1,3 +1,13 @@
+2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>
+
+	* config/tc-ia64.c (reg_symbol): Add a new register.
+	(indirect_reg): Ditto.
+	(pseudo_func): Add new symbolic constants.
+	(operand_match): Add new operand types recognition.
+	(operand_insn): Add new register recognition.
+	(md_begin): Add new register definition.
+	(specify_resource): Add new register recognition.
+
 2012-09-01  Hans-Peter Nilsson  <hp@bitrange.com>
 
 	PR gas/14521

gas/config/tc-ia64.c

@@ -114,7 +114,8 @@ enum reg_symbol
     REG_FR	= (REG_GR + 128),
     REG_AR	= (REG_FR + 128),
     REG_CR	= (REG_AR + 128),
-    REG_P	= (REG_CR + 128),
+    REG_DAHR	= (REG_CR + 128),
+    REG_P	= (REG_DAHR + 8),
     REG_BR	= (REG_P  + 64),
     REG_IP	= (REG_BR + 8),
     REG_CFM,
@@ -133,6 +134,7 @@ enum reg_symbol
     IND_PKR,
     IND_PMC,
     IND_PMD,
+    IND_DAHR,
     IND_RR,
     /* The following pseudo-registers are used for unwind directives only:  */
     REG_PSP,
@@ -539,6 +541,7 @@ indirect_reg[] =
     { "pkr",	IND_PKR },
     { "pmc",	IND_PMC },
     { "pmd",	IND_PMD },
+    { "dahr",	IND_DAHR },
     { "rr",	IND_RR },
   };
 
@@ -609,6 +612,12 @@ pseudo_func[] =
 
     /* hint constants: */
     { "pause",	PSEUDO_FUNC_CONST, { 0x0 } },
+    { "priority", PSEUDO_FUNC_CONST, { 0x1 } },
+
+    /* tf constants: */
+    { "clz",	PSEUDO_FUNC_CONST, {  32 } },
+    { "mpy",	PSEUDO_FUNC_CONST, {  33 } },
+    { "datahints",	PSEUDO_FUNC_CONST, {  34 } },
 
     /* unwind-related constants:  */
     { "svr4",	PSEUDO_FUNC_CONST,	{ ELFOSABI_NONE } },
@@ -5567,6 +5576,12 @@ operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e)
 	return OPERAND_MATCH;
       break;
 
+    case IA64_OPND_DAHR3:
+      if (e->X_op == O_register && e->X_add_number >= REG_DAHR
+	  && e->X_add_number < REG_DAHR + 8)
+	return OPERAND_MATCH;
+      break;
+
     case IA64_OPND_F1:
     case IA64_OPND_F2:
     case IA64_OPND_F3:
@@ -5611,6 +5626,7 @@ operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e)
     case IA64_OPND_PKR_R3:
     case IA64_OPND_PMC_R3:
     case IA64_OPND_PMD_R3:
+    case IA64_OPND_DAHR_R3:
     case IA64_OPND_RR_R3:
       if (e->X_op == O_index && e->X_op_symbol
 	  && (S_GET_VALUE (e->X_op_symbol) - IND_CPUID
@@ -5731,6 +5747,8 @@ operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e)
     case IA64_OPND_IMMU2:
     case IA64_OPND_IMMU7a:
     case IA64_OPND_IMMU7b:
+    case IA64_OPND_IMMU16:
+    case IA64_OPND_IMMU19:
     case IA64_OPND_IMMU21:
     case IA64_OPND_IMMU24:
     case IA64_OPND_MBTYPE4:
@@ -5987,6 +6005,39 @@ operand_match (const struct ia64_opcode *idesc, int res_index, expressionS *e)
       ++CURR_SLOT.num_fixups;
       return OPERAND_MATCH;
 
+    case IA64_OPND_STRD5b:
+      if (e->X_op == O_constant)
+	{
+	  /* 5-bit signed scaled by 64 */
+	  if ((e->X_add_number <=  	( 0xf  << 6 )) 
+	       && (e->X_add_number >=  -( 0x10 << 6 )))
+	    {
+	      
+	      /* Must be a multiple of 64 */
+	      if ((e->X_add_number & 0x3f) != 0)
+	        as_warn (_("stride must be a multiple of 64; lower 6 bits ignored"));
+
+	      e->X_add_number &= ~ 0x3f;
+	      return OPERAND_MATCH;
+	    }
+	  else
+	    return OPERAND_OUT_OF_RANGE;
+	}
+      break;
+    case IA64_OPND_CNT6a:
+      if (e->X_op == O_constant)
+	{
+	  /* 6-bit unsigned biased by 1 -- count 0 is meaningless */
+	  if ((e->X_add_number     <=   64) 
+	       && (e->X_add_number > 0) )
+	    {
+	      return OPERAND_MATCH;
+	    }
+	  else
+	    return OPERAND_OUT_OF_RANGE;
+	}
+      break;
+
     default:
       break;
     }
@@ -6437,6 +6488,10 @@ build_insn (struct slot *slot, bfd_vma *insnp)
 	  val -= REG_CR;
 	  break;
 
+	case IA64_OPND_DAHR3:
+	  val -= REG_DAHR;
+	  break;
+
 	case IA64_OPND_F1:
 	case IA64_OPND_F2:
 	case IA64_OPND_F3:
@@ -6463,6 +6518,7 @@ build_insn (struct slot *slot, bfd_vma *insnp)
 	case IA64_OPND_PKR_R3:
 	case IA64_OPND_PMC_R3:
 	case IA64_OPND_PMD_R3:
+	case IA64_OPND_DAHR_R3:
 	case IA64_OPND_RR_R3:
 	  val -= REG_GR;
 	  break;
@@ -7435,6 +7491,9 @@ md_begin (void)
   for (i = 0; i < NELEMS (cr); ++i)
     declare_register (cr[i].name, REG_CR + cr[i].regnum);
 
+  /* dahr registers:  */
+  declare_register_set ("dahr", 8, REG_DAHR);
+
   declare_register ("ip", REG_IP);
   declare_register ("cfm", REG_CFM);
   declare_register ("psr", REG_PSR);
@@ -8688,6 +8747,22 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note)
 	}
       break;
 
+    case IA64_RS_DAHR:
+      if (note == 0)
+	{
+	  if (idesc->operands[!rsrc_write] == IA64_OPND_DAHR3)
+	    {
+	      specs[count] = tmpl;
+	      specs[count++].index =
+		CURR_SLOT.opnd[!rsrc_write].X_add_number - REG_DAHR;
+	    }
+	}
+      else
+	{
+	  UNHANDLED;
+	}
+      break;
+
     case IA64_RS_FR:
     case IA64_RS_FRb:
       if (note != 1)
@@ -8762,6 +8837,7 @@ dep->name, idesc->name, (rsrc_write?"write":"read"), note)
 		      || idesc->operands[i] == IA64_OPND_PKR_R3
 		      || idesc->operands[i] == IA64_OPND_PMC_R3
 		      || idesc->operands[i] == IA64_OPND_PMD_R3
+		      || idesc->operands[i] == IA64_OPND_DAHR_R3
 		      || idesc->operands[i] == IA64_OPND_RR_R3
 		      || ((i >= idesc->num_outputs)
 			  && (idesc->operands[i] == IA64_OPND_R1

gas/testsuite/ChangeLog

@@ -1,3 +1,11 @@
+2012-09-04  Sergey A. Guriev  <sergey.a.guriev@intel.com>
+
+	* gas/testsuite/gas/ia64/psn.d: New file.
+	* gas/testsuite/gas/ia64/psn.s: New file.
+	* gas/testsuite/gas/ia64/ia64.exp: Add new testcase.
+	* gas/testsuite/gas/ia64/opc-i.d: Fixed failing tests.
+	* gas/testsuite/gas/ia64/opc-m.d: Ditto.
+
 2012-09-01  Hans-Peter Nilsson  <hp@bitrange.com>
 
 	PR gas/14521

gas/testsuite/gas/ia64/ia64.exp

@@ -11,6 +11,7 @@ if [istarget "ia64-*"] then {
     run_dump_test "opc-i"
     run_dump_test "opc-m"
     run_dump_test "opc-x"
+    run_dump_test "psn"
     run_dump_test "pseudo"
     run_dump_test "nop_x"
     run_dump_test "mov-ar"

gas/testsuite/gas/ia64/opc-i.d

@@ -244,7 +244,7 @@ Disassembly of section \.text:
  976:	30 20 18 84 03 60 	            mov\.ret\.dptk b3=r4,a70 <_start\+0xa70>
  97c:	40 70 08 07       	            mov\.ret\.dptk\.imp b3=r4,a70 <_start\+0xa70>;;
 	\.\.\.
- a70:	00 00 00 80 01 00 	\[MII\]       hint\.m 0x0
+ a70:	00 00 00 80 01 00 	\[MII\]       hint\.m 0
  a76:	00 00 00 03 00 00 	            hint\.i 0x0
  a7c:	00 00 06 00       	            hint\.i 0x0
  a80:	00 00 00 00 01 00 	\[MII\]       nop\.m 0x0

gas/testsuite/gas/ia64/opc-m.d

@@ -1327,10 +1327,10 @@ Disassembly of section \.text:
     1b70:	18 20 00 0a 1e 04 	\[MMB\]       tpa r4=r5
     1b76:	40 00 14 3e 08 00 	            tak r4=r5
     1b7c:	00 00 00 20       	            nop\.b 0x0
-    1b80:	18 00 00 80 01 00 	\[MMB\]       hint\.m 0x0
+    1b80:	18 00 00 80 01 00 	\[MMB\]       hint\.m 0
-    1b86:	00 00 00 03 00 00 	            hint\.m 0x0
+    1b86:	00 00 00 03 00 00 	            hint\.m 0
     1b8c:	00 00 00 20       	            nop\.b 0x0
-    1b90:	18 f8 ff 8f 01 00 	\[MMB\]       hint\.m 0x1ffff
+    1b90:	18 78 fe bf 01 00 	\[MMB\]       hint\.m 131071
     1b96:	40 30 14 02 22 00 	            cmp8xchg16\.acq r4=\[r5\],r6,ar\.csd,ar\.ccv
     1b9c:	00 00 00 20       	            nop\.b 0x0
     1ba0:	18 20 18 0a 03 11 	\[MMB\]       cmp8xchg16\.acq\.nt1 r4=\[r5\],r6,ar\.csd,ar\.ccv

include/opcode/ChangeLog

@@ -1,3 +1,7 @@
+2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+	* ia64.h (ia64_opnd): Add new operand types.
+
 2012-08-21  David S. Miller  <davem@davemloft.net>
 
 	* sparc.h (F3F4): New macro.

include/opcode/ia64.h

@@ -91,6 +91,7 @@ enum ia64_opnd
     IA64_OPND_R2,	/* second register # */
     IA64_OPND_R3,	/* third register # */
     IA64_OPND_R3_2,	/* third register # (limited to gr0-gr3) */
+    IA64_OPND_DAHR3,	/* dahr reg # ( bits 23-25) */
 
     /* memory operands: */
     IA64_OPND_MR3,	/* memory at addr of third register # */
@@ -105,6 +106,7 @@ enum ia64_opnd
     IA64_OPND_PKR_R3,	/* pkr[reg] */
     IA64_OPND_PMC_R3,	/* pmc[reg] */
     IA64_OPND_PMD_R3,	/* pmd[reg] */
+    IA64_OPND_DAHR_R3,	/* dahr[reg] */
     IA64_OPND_RR_R3,	/* rr[reg] */
 
     /* immediate operands: */
@@ -134,7 +136,9 @@ enum ia64_opnd
     IA64_OPND_IMM9a,	/* signed 9-bit immediate (bits 6-12, 27, 36) */
     IA64_OPND_IMM9b,	/* signed 9-bit immediate (bits 13-19, 27, 36) */
     IA64_OPND_IMM14,	/* signed 14-bit immediate (bits 13-19, 27-32, 36) */
+    IA64_OPND_IMMU16,	/* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */
     IA64_OPND_IMM17,	/* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
+    IA64_OPND_IMMU19,	/* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */
     IA64_OPND_IMMU21,	/* unsigned 21-bit immediate (bits 6-25, 36) */
     IA64_OPND_IMM22,	/* signed 22-bit immediate (bits 13-19, 22-36) */
     IA64_OPND_IMMU24,	/* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
@@ -155,6 +159,9 @@ enum ia64_opnd
     IA64_OPND_TGT64,    /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
     IA64_OPND_LDXMOV,	/* any symbol, generates R_IA64_LDXMOV.  */
 
+    IA64_OPND_CNT6a,	/* 6-bit count  (bits 6-11) */
+    IA64_OPND_STRD5b,	/* 5-bit stride (bits 13-17) */
+
     IA64_OPND_COUNT	/* # of operand types (MUST BE LAST!) */
   };
 
@@ -191,6 +198,7 @@ enum ia64_resource_specifier
   IA64_RS_CR_IRR,
   IA64_RS_CR_LRR,
   IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */
+  IA64_RS_DAHR,
   IA64_RS_DBR,
   IA64_RS_FR,
   IA64_RS_FRb,
@@ -212,6 +220,7 @@ enum ia64_resource_specifier
   IA64_RS_PSR, /* PSR bits */
   IA64_RS_RSE, /* implementation-specific RSE resources */
   IA64_RS_AR_FPSR,
+
 };
 
 enum ia64_rse_resource

opcodes/ChangeLog

@@ -1,3 +1,21 @@
+2012-09-04  Sergey A. Guriev <sergey.a.guriev@intel.com>
+
+	* ia64-asmtab.h (completer_index): Extend bitfield to full uint.
+	* ia64-gen.c: Promote completer index type to longlong.
+	(irf_operand): Add new register recognition.
+	(in_iclass_mov_x): Add an entry for the new mov_* instruction type.
+	(lookup_specifier): Add new resource recognition.
+	(insert_bit_table_ent): Relax abort condition according to the
+	changed completer index type.
+	(print_dis_table): Fix printf format for completer index.
+	* ia64-ic.tbl: Add a new instruction class.
+	* ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
+	* ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
+	* ia64-opc.h: Define short names for new operand types.
+	* ia64-raw.tbl: Add new RAW resource for DAHR register.
+	* ia64-waw.tbl: Add new WAW resource for DAHR register.
+	* ia64-asmtab.c: Regenerate.
+
 2012-08-29  Peter Bergner  <bergner@vnet.ibm.com>
 
 	* ppc-opc.c (VXASHB_MASK): New define.

opcodes/ia64-asmtab.h

@@ -131,7 +131,7 @@ struct ia64_dis_names
      bits.
 
      There is always at least one 1 bit. */
-  unsigned int completer_index : 20;
+  unsigned int completer_index ;
 
   /* The index in the main_table[] array for the instruction. */
   unsigned short insn_index : 11;

opcodes/ia64-gen.c

@@ -69,6 +69,7 @@ int debug = 0;
 #define NELEMS(a) (sizeof (a) / sizeof ((a)[0]))
 #define tmalloc(X) (X *) xmalloc (sizeof (X))
 
+typedef unsigned long long  ci_t;
 /* The main opcode table entry.  Each entry is a unique combination of
    name and flags (no two entries in the table compare as being equal
    via opcodes_eq).  */
@@ -146,7 +147,7 @@ struct disent
   int priority;
 
   /* The completer_index value for this entry.  */
-  int completer_index;
+  ci_t completer_index;
 
   /* How many other entries share this decode.  */
   int nextcnt;
@@ -290,11 +291,11 @@ static void shrink (struct ia64_opcode *);
 static void print_version (void);
 static void usage (FILE *, int);
 static void finish_distable (void);
-static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_insn, int, int, int);
+static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_insn, int, int, ci_t);
-static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, struct completer_entry *, int);
+static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, struct completer_entry *, ci_t);
 static void compact_distree (struct bittree *);
 static struct bittree * make_bittree_entry (void);
-static struct disent * add_dis_table_ent (struct disent *, int, int, int);
+static struct disent * add_dis_table_ent (struct disent *, int, int, ci_t);
 
 
 static void
@@ -902,12 +903,13 @@ irf_operand (int op, const char *field)
               || (op == IA64_OPND_PMC_R3 && strstr (field, "pmc"))
               || (op == IA64_OPND_PMD_R3 && strstr (field, "pmd"))
               || (op == IA64_OPND_MSR_R3 && strstr (field, "msr"))
-              || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid")));
+              || (op == IA64_OPND_CPUID_R3 && strstr (field, "cpuid"))
+              || (op == IA64_OPND_DAHR_R3  && strstr (field, "dahr")));
     }
 }
 
-/* Handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and
+/* Handle mov_ar, mov_br, mov_cr, move_dahr, mov_indirect, mov_ip, mov_pr,
-   mov_um insn classes.  */
+ * mov_psr, and  mov_um insn classes.  */
 static int
 in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, 
                  const char *format, const char *field)
@@ -965,6 +967,13 @@ in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic,
           return strstr (format, "M33") != NULL;
       }
       break;
+    case 'd':
+      {
+        int m50 = plain_mov && idesc->operands[0] == IA64_OPND_DAHR3;
+        if (m50)
+          return strstr (format, "M50") != NULL;
+      }
+      break;
     case 'i':
       if (ic->name[5] == 'n')
         {
@@ -1441,6 +1450,8 @@ lookup_specifier (const char *name)
         return IA64_RS_CR_LRR;
       if (strstr (name, "CR%") != NULL)
         return IA64_RS_CR;
+      if (strstr (name, "DAHR%, % in 0") != NULL)
+        return IA64_RS_DAHR;
       if (strstr (name, "FR%, % in 0") != NULL)
         return IA64_RS_FR;
       if (strstr (name, "FR%, % in 2") != NULL)
@@ -1723,7 +1734,7 @@ make_bittree_entry (void)
 
 static struct disent *
 add_dis_table_ent (struct disent *which, int insn, int order,
-                   int completer_index)
+                   ci_t completer_index)
 {
   int ci = 0;
   struct disent *ent;
@@ -1776,7 +1787,7 @@ finish_distable (void)
 static void
 insert_bit_table_ent (struct bittree *curr_ent, int bit, ia64_insn opcode,
                       ia64_insn mask, int opcodenum, int order,
-                      int completer_index)
+                      ci_t completer_index)
 {
   ia64_insn m;
   int b;
@@ -1810,9 +1821,9 @@ insert_bit_table_ent (struct bittree *curr_ent, int bit, ia64_insn opcode,
 
 static void
 add_dis_entry (struct bittree *first, ia64_insn opcode, ia64_insn mask,
-               int opcodenum, struct completer_entry *ent, int completer_index)
+               int opcodenum, struct completer_entry *ent, ci_t completer_index)
 {
-  if (completer_index & (1 << 20))
+  if (completer_index & ((ci_t)1 << 32) )
     abort ();
 
   while (ent != NULL)
@@ -2131,7 +2142,7 @@ print_dis_table (void)
 
       while (ent != NULL)
 	{
-	  printf ("{ 0x%x, %d, %d, %d },\n", ent->completer_index,
+	  printf ("{ 0x%lx, %d, %d, %d },\n", ( long ) ent->completer_index,
 		  ent->insn, (ent->nexte != NULL ? 1 : 0),
                   ent->priority);
 	  ent = ent->nexte;

opcodes/ia64-ic.tbl

@@ -189,6 +189,7 @@ mov-to-CR-LRR;	IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}]
 mov-to-CR-PMV;	IC:mov-to-CR[Field(cr3) == PMV]
 mov-to-CR-PTA;	IC:mov-to-CR[Field(cr3) == PTA]
 mov-to-CR-TPR;	IC:mov-to-CR[Field(cr3) == TPR]
+mov-to-DAHR;	mov_dahr[Format in {M50}]
 mov-to-IND;	mov_indirect[Format in {M42}]
 mov-to-IND-CPUID;	IC:mov-to-IND[Field(ireg) == cpuid]
 mov-to-IND-DBR;	IC:mov-to-IND[Field(ireg) == dbr]

opcodes/ia64-opc-i.c

@@ -276,9 +276,12 @@ struct ia64_opcode ia64_opcodes_i[] =
     {"pshl2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
     {"pshl4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
     {"shl",	I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY},
+    {"mpy4",    I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 1, 3), {R1, R2, R3}, EMPTY},
+    {"mpyshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 3, 3), {R1, R2, R3}, EMPTY},
     {"pshl2",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
     {"pshl4",	I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY},
     {"popcnt",	I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY},
+    {"clz",     I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 3), {R1, R3}, EMPTY},
 
     {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL}
   };

opcodes/ia64-opc.h

@@ -71,6 +71,7 @@
 #define R2	IA64_OPND_R2
 #define R3	IA64_OPND_R3
 #define R3_2	IA64_OPND_R3_2
+#define DAHR	IA64_OPND_DAHR3
 
 #define CPUID_R3 IA64_OPND_CPUID_R3
 #define DBR_R3	IA64_OPND_DBR_R3
@@ -82,6 +83,7 @@
 #define PKR_R3	IA64_OPND_PKR_R3
 #define PMC_R3	IA64_OPND_PMC_R3
 #define PMD_R3	IA64_OPND_PMD_R3
+#define DAHR_R3	IA64_OPND_DAHR_R3
 #define RR_R3	IA64_OPND_RR_R3
 
 #define CCNT5	IA64_OPND_CCNT5
@@ -109,6 +111,8 @@
 #define IMM9a	IA64_OPND_IMM9a
 #define IMM9b	IA64_OPND_IMM9b
 #define IMMU2	IA64_OPND_IMMU2
+#define IMMU16	IA64_OPND_IMMU16
+#define IMMU19	IA64_OPND_IMMU19
 #define IMMU21	IA64_OPND_IMMU21
 #define IMMU24	IA64_OPND_IMMU24
 #define IMMU62	IA64_OPND_IMMU62
@@ -129,5 +133,7 @@
 #define TGT25b	IA64_OPND_TGT25b
 #define TGT25c	IA64_OPND_TGT25c
 #define TGT64   IA64_OPND_TGT64
+#define CNT6a	IA64_OPND_CNT6a
+#define STRD5b	IA64_OPND_STRD5b
 
 #endif

opcodes/ia64-raw.tbl

@@ -76,6 +76,7 @@ CR[TPR];	IC:mov-to-CR-TPR;	IC:mov-from-CR-TPR, IC:mov-from-CR-IVR;	data
 CR[TPR];	IC:mov-to-CR-TPR;	IC:mov-to-PSR-l+17, ssm+17;	SC Section 5.8.3.3, "Task Priority Register (TPR Ð CR66)" on page 2:119
 CR[TPR];	IC:mov-to-CR-TPR;	rfi;	implied
 CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127;	IC:none;	IC:mov-from-CR-rv+1;	none
+DAHR%, % in 0-7;	br.call, brl.call, br.ret, IC:mov-to-DAHR;	br.call, IC:mem-readers, IC:mem-writers, IC:mov-from-DAHR;	implied
 DBR#;	IC:mov-to-IND-DBR+3;	IC:mov-from-IND-DBR+3;	impliedF
 DBR#;	IC:mov-to-IND-DBR+3;	IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers;	data
 DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;	IC:mem-readers, IC:mem-writers, IC:non-access;	data

opcodes/ia64-waw.tbl

@@ -67,6 +67,7 @@ CR[PMV];	IC:mov-to-CR-PMV;	IC:mov-to-CR-PMV;	impliedF
 CR[PTA];	IC:mov-to-CR-PTA;	IC:mov-to-CR-PTA;	impliedF
 CR[TPR];	IC:mov-to-CR-TPR;	IC:mov-to-CR-TPR;	impliedF
 CR%, % in 3-7, 10-15, 18, 28-63, 75-79, 82-127;	IC:none;	IC:none;	none
+DAHR%, % in 0-7;	IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mov-to-DAHR, rfi;	IC:br.call, brl.call, br.ret, IC:mov-to-AR-BSPSTORE, IC:mov-to-DAHR, rfi;	implied
 DBR#;	IC:mov-to-IND-DBR+3;	IC:mov-to-IND-DBR+3;	impliedF
 DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d;	none
 DTC;	ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d;	itc.i, itc.d, itr.i, itr.d;	impliedF