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RISC-V: Add support for XCVbi extension in CV32E40P

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Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett682@gmail.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>
  Nazareno Bruschi <nazareno.bruschi@embecosm.com>
  Lin Sinan

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	macros for XCVbi.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
	for XCVbi.
	(enum riscv_insn_class): Add the XCVbi instruction class.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Add the necessary
	operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Note XCVbi as an additional ISA extension
	for CORE-V.
	* testsuite/gas/riscv/cv-bi-beqimm.d: New test.
	* testsuite/gas/riscv/cv-bi-beqimm.s: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.d: New test.
	* testsuite/gas/riscv/cv-bi-bneimm.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-march.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-bi-fail-operand-03.s: New test.
	* testsuite/gas/riscv/march-help.l: Add xcvbi string.

include/ChangeLog:

	* opcode/riscv-opc.h: Add corresponding MATCH and MASK
	macros for XCVbi.
	* opcode/riscv.h: Add corresponding EXTRACT and ENCODE macros
	for XCVbi.
	(enum riscv_insn_class): Add the XCVbi instruction class.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Add disassembly for new operand.
	* riscv-opc.c: Add XCVbi instructions.
This commit is contained in:
Mary Bennett 2024-05-30 16:06:58 +01:00 • committed by Nelson Chu
parent 940da069b4
commit b0f266f38b
24 changed files with 124 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
bfd/elfxx-riscv.c
View file

@ -1455,6 +1455,7 @@ static struct riscv_supported_ext riscv_supported_vendor_x_ext[] =
{"xcvmac", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvalu", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvelw", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xcvbi", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"xtheadbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@ -2677,6 +2678,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "xcvalu");
case INSN_CLASS_XCVELW:
return riscv_subset_supports (rps, "xcvelw");
case INSN_CLASS_XCVBI:
return riscv_subset_supports (rps, "xcvbi");
case INSN_CLASS_XTHEADBA:
return riscv_subset_supports (rps, "xtheadba");
case INSN_CLASS_XTHEADBB:
@ -2937,6 +2940,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return "xcvalu";
case INSN_CLASS_XCVELW:
return "xcvelw";
case INSN_CLASS_XCVBI:
return "xcvbi";
case INSN_CLASS_XTHEADBA:
return "xtheadba";
case INSN_CLASS_XTHEADBB:

12
gas/config/tc-riscv.c
View file

@ -1660,7 +1660,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
switch (*++oparg)
{
case '2':
/* ls2[4:0] */
case '4':
used_bits |= ENCODE_CV_IS2_UIMM5 (-1U);
break;
case '3':
@ -3956,6 +3956,16 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
ip->insn_opcode
|= ENCODE_CV_IS3_UIMM5 (imm_expr->X_add_number);
continue;
case '4':
my_getExpression (imm_expr, asarg);
check_absolute_expr (ip, imm_expr, FALSE);
asarg = expr_parse_end;
if (imm_expr->X_add_number < -16
|| imm_expr->X_add_number > 15)
break;
ip->insn_opcode
|= ENCODE_CV_IS2_UIMM5 (imm_expr->X_add_number);
continue;
default:
goto unknown_riscv_ip_operand;
}

5
gas/doc/c-riscv.texi
View file

@ -755,6 +755,11 @@ The Xcvelw extension provides instructions for event load word operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
@item Xcvbi
The Xcvbi extension provides instructions for branch immediate operations.
It is documented in @url{https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html}
@item XTheadBa
The XTheadBa extension provides instructions for address calculations.

12
gas/testsuite/gas/riscv/cv-bi-beqimm.d Normal file
View file

@ -0,0 +1,12 @@
#as: -march=rv32i_xcvbi
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <foo>:
[ ]+0:[ ]+0102e00b[ ]+cv.beqimm[ ]+t0,-16,0 +<foo>
[ ]+4:[ ]+fe5eee8b[ ]+cv.beqimm[ ]+t4,5,0 +<foo>
[ ]+8:[ ]+fef3ec8b[ ]+cv.beqimm[ ]+t2,15,0 +<foo>

4
gas/testsuite/gas/riscv/cv-bi-beqimm.s Normal file
View file

@ -0,0 +1,4 @@
foo:
cv.beqimm t0, -16, foo
cv.beqimm t4, 5, foo
cv.beqimm t2, 15, foo

12
gas/testsuite/gas/riscv/cv-bi-bneimm.d Normal file
View file

@ -0,0 +1,12 @@
#as: -march=rv32i_xcvbi
#objdump: -d
.*:[ ]+file format .*
Disassembly of section .text:
0+000 <foo>:
[ ]+0:[ ]+0102f00b[ ]+cv.bneimm[ ]+t0,-16,0 +<foo>
[ ]+4:[ ]+fe5efe8b[ ]+cv.bneimm[ ]+t4,5,0 +<foo>
[ ]+8:[ ]+fef3fc8b[ ]+cv.bneimm[ ]+t2,15,0 +<foo>

4
gas/testsuite/gas/riscv/cv-bi-bneimm.s Normal file
View file

@ -0,0 +1,4 @@
foo:
cv.bneimm t0, -16, foo
cv.bneimm t4, 5, foo
cv.bneimm t2, 15, foo

3
gas/testsuite/gas/riscv/cv-bi-fail-march.d Normal file
View file

@ -0,0 +1,3 @@
#as: -march=rv32i
#source: cv-bi-fail-march.s
#error_output: cv-bi-fail-march.l

3
gas/testsuite/gas/riscv/cv-bi-fail-march.l Normal file
View file

@ -0,0 +1,3 @@
.*: Assembler messages:
.*: Error: unrecognized opcode `cv.beqimm t2,1,foo', extension `xcvbi' required
.*: Error: unrecognized opcode `cv.bneimm t2,1,foo', extension `xcvbi' required

5
gas/testsuite/gas/riscv/cv-bi-fail-march.s Normal file
View file

@ -0,0 +1,5 @@
# Absence of xcorev or xcorevbi march option disables all CORE-V
# immediate branching extensions.
foo:
cv.beqimm t2, 1, foo
cv.bneimm t2, 1, foo

3
gas/testsuite/gas/riscv/cv-bi-fail-operand-01.d Normal file
View file

@ -0,0 +1,3 @@
#as: -march=rv32i_xcvbi
#source: cv-bi-fail-operand-01.s
#error_output: cv-bi-fail-operand-01.l

3
gas/testsuite/gas/riscv/cv-bi-fail-operand-01.l Normal file
View file

@ -0,0 +1,3 @@
.*: Assembler messages:
.*: Error: illegal operands `cv.beqimm 20,10,foo'
.*: Error: illegal operands `cv.bneimm 8,-4,foo'

4
gas/testsuite/gas/riscv/cv-bi-fail-operand-01.s Normal file
View file

@ -0,0 +1,4 @@
# Comparison target must be a register
foo:
cv.beqimm 20, 10, foo
cv.bneimm 8, -4, foo

3
gas/testsuite/gas/riscv/cv-bi-fail-operand-02.d Normal file
View file

@ -0,0 +1,3 @@
#as: -march=rv32i_xcvbi
#source: cv-bi-fail-operand-02.s
#error_output: cv-bi-fail-operand-02.l

3
gas/testsuite/gas/riscv/cv-bi-fail-operand-02.l Normal file
View file

@ -0,0 +1,3 @@
.*: Assembler messages:
.*: Error: instruction cv.beqimm requires absolute expression
.*: Error: instruction cv.bneimm requires absolute expression

4
gas/testsuite/gas/riscv/cv-bi-fail-operand-02.s Normal file
View file

@ -0,0 +1,4 @@
# Comparison value must be an immediate
foo:
cv.beqimm t0, t1, foo
cv.bneimm t3, t4, foo

3
gas/testsuite/gas/riscv/cv-bi-fail-operand-03.d Normal file
View file

@ -0,0 +1,3 @@
#as: -march=rv32i_xcvbi
#source: cv-bi-fail-operand-03.s
#error_output: cv-bi-fail-operand-03.l

9
gas/testsuite/gas/riscv/cv-bi-fail-operand-03.l Normal file
View file

@ -0,0 +1,9 @@
.*: Assembler messages:
.*: Error: illegal operands `cv.beqimm t0,-17,foo'
.*: Error: illegal operands `cv.beqimm t2,-32,foo'
.*: Error: illegal operands `cv.beqimm t4,16,foo'
.*: Error: illegal operands `cv.beqimm t3,44,foo'
.*: Error: illegal operands `cv.bneimm t0,-17,foo'
.*: Error: illegal operands `cv.bneimm t2,-32,foo'
.*: Error: illegal operands `cv.bneimm t4,16,foo'
.*: Error: illegal operands `cv.bneimm t3,44,foo'

10
gas/testsuite/gas/riscv/cv-bi-fail-operand-03.s Normal file
View file

@ -0,0 +1,10 @@
# Comparison value must be an immediate in range [-16, +15]
foo:
cv.beqimm t0, -17, foo
cv.beqimm t2, -32, foo
cv.beqimm t4, 16, foo
cv.beqimm t3, 44, foo
cv.bneimm t0, -17, foo
cv.bneimm t2, -32, foo
cv.bneimm t4, 16, foo
cv.bneimm t3, 44, foo

1
gas/testsuite/gas/riscv/march-help.l
View file

@ -106,6 +106,7 @@ All available -march extensions for RISC-V:
xcvmac 1.0
xcvalu 1.0
xcvelw 1.0
xcvbi 1.0
xtheadba 1.0
xtheadbb 1.0
xtheadbs 1.0

5
include/opcode/riscv-opc.h
View file

@ -2472,6 +2472,11 @@
/* Vendor-specific (CORE-V) Xcvelw instructions. */
#define MATCH_CV_ELW 0x600b
#define MASK_CV_ELW 0x707f
/* Vendor-specific (CORE-V) Xcvbi instructions. */
#define MATCH_CV_BNEIMM 0x700b
#define MASK_CV_BNEIMM 0x707f
#define MATCH_CV_BEQIMM 0x600b
#define MASK_CV_BEQIMM 0x707f
/* Vendor-specific (T-Head) XTheadBa instructions. */
#define MATCH_TH_ADDSL 0x0000100b
#define MASK_TH_ADDSL 0xf800707f

4
include/opcode/riscv.h
View file

@ -55,6 +55,7 @@ static inline unsigned int riscv_insn_length (insn_t insn)
#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
#define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
#define RV_IMM_SIGN_N(x, s, n) (-(((x) >> ((s) + (n) - 1)) & 1))
#define EXTRACT_ITYPE_IMM(x) \
(RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
@ -119,6 +120,8 @@ static inline unsigned int riscv_insn_length (insn_t insn)
(RV_X(x, 20, 5))
#define EXTRACT_CV_IS3_UIMM5(x) \
(RV_X(x, 25, 5))
#define EXTRACT_CV_BI_IMM5(x) \
(RV_X(x, 20, 5) | (RV_IMM_SIGN_N(x, 20, 5) << 5))
#define ENCODE_ITYPE_IMM(x) \
(RV_X(x, 0, 12) << 20)
@ -490,6 +493,7 @@ enum riscv_insn_class
INSN_CLASS_XCVMAC,
INSN_CLASS_XCVALU,
INSN_CLASS_XCVELW,
INSN_CLASS_XCVBI,
INSN_CLASS_XTHEADBA,
INSN_CLASS_XTHEADBB,
INSN_CLASS_XTHEADBS,

4
opcodes/riscv-dis.c
View file

@ -771,6 +771,10 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info
print (info->stream, dis_style_immediate, "%d",
((int) EXTRACT_CV_IS3_UIMM5 (l)));
break;
case '4':
print (info->stream, dis_style_immediate, "%d",
((int) EXTRACT_CV_BI_IMM5 (l)));
break;
default:
goto undefined_modifier;
}

4
opcodes/riscv-opc.c
View file

@ -2210,6 +2210,10 @@ const struct riscv_opcode riscv_opcodes[] =
/* Vendor-specific (CORE-V) Xcvelw instructions. */
{"cv.elw", 0, INSN_CLASS_XCVELW, "d,o(s)", MATCH_CV_ELW, MASK_CV_ELW, match_opcode, 0},
/* Vendor-specific (CORE-V) Xcvbi instructions. */
{"cv.beqimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BEQIMM, MASK_CV_BEQIMM, match_opcode, 0},
{"cv.bneimm", 0, INSN_CLASS_XCVBI, "s,Xc4,p", MATCH_CV_BNEIMM, MASK_CV_BNEIMM, match_opcode, 0},
/* Vendor-specific (T-Head) XTheadBa instructions. */
{"th.addsl", 0, INSN_CLASS_XTHEADBA, "d,s,t,Xtu2@25", MATCH_TH_ADDSL, MASK_TH_ADDSL, match_opcode, 0},