2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
opcodes: * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu. * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions accordingly. bfd: * archures.c: Add bfd_mach_sh4_nommu_nofpu. * cpu-sh.c: Ditto. * elf32-sh.c: Ditto. * bfd-in2.h: Regenerate. include/elf: * sh.h: Add EF_SH4_NOMMU_NOFPU. gas: * config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and -isa=sh4-nommu-nofpu options. Adjust help messages accordingly. (sh_elf_final_processing): Output BFD type sh4_nofpu if that is the most general type or the user specifically requested it. (md_assemble): Add a new error message for when an instruction is understood, but is not allowed due to an -isa option.
This commit is contained in:
Joern Rennecke
parent
9545c4ce85
commit
ae51a426eb
12 changed files with 140 additions and 36 deletions
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@ -1,3 +1,10 @@
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2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
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* archures.c: Add bfd_mach_sh4_nommu_nofpu.
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* cpu-sh.c: Ditto.
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* elf32-sh.c: Ditto.
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* bfd-in2.h: Regenerate.
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2004-03-02 Alexandre Oliva <aoliva@redhat.com>
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* elf32-frv.c (struct frv_pic_relocs_info): Added fixups and
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@ -1,6 +1,6 @@
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/* BFD library support routines for architectures.
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Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
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2000, 2001, 2002, 2003
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2000, 2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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Hacked by John Gilmore and Steve Chamberlain of Cygnus Support.
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@ -230,6 +230,7 @@ DESCRIPTION
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.#define bfd_mach_sh3e 0x3e
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.#define bfd_mach_sh4 0x40
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.#define bfd_mach_sh4_nofpu 0x41
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.#define bfd_mach_sh4_nommu_nofpu 0x42
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.#define bfd_mach_sh4a 0x4a
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.#define bfd_mach_sh4a_nofpu 0x4b
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.#define bfd_mach_sh4al_dsp 0x4d
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@ -1662,6 +1662,7 @@ enum bfd_architecture
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#define bfd_mach_sh3e 0x3e
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#define bfd_mach_sh4 0x40
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#define bfd_mach_sh4_nofpu 0x41
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#define bfd_mach_sh4_nommu_nofpu 0x42
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#define bfd_mach_sh4a 0x4a
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#define bfd_mach_sh4a_nofpu 0x4b
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#define bfd_mach_sh4al_dsp 0x4d
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19
bfd/cpu-sh.c
19
bfd/cpu-sh.c
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@ -1,5 +1,5 @@
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/* BFD library support routines for the Renesas / SuperH SH architecture.
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Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003
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Copyright 1993, 1994, 1997, 1998, 2000, 2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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Hacked by Steve Chamberlain of Cygnus Support.
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@ -34,7 +34,8 @@
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#define SH4A_NEXT &arch_info_struct[8]
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#define SH4AL_DSP_NEXT &arch_info_struct[9]
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#define SH4_NOFPU_NEXT &arch_info_struct[10]
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#define SH4A_NOFPU_NEXT &arch_info_struct[11]
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#define SH4_NOMMU_NOFPU_NEXT &arch_info_struct[11]
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#define SH4A_NOFPU_NEXT &arch_info_struct[12]
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#define SH64_NEXT NULL
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static const bfd_arch_info_type arch_info_struct[] =
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@ -179,6 +180,20 @@ static const bfd_arch_info_type arch_info_struct[] =
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bfd_default_scan,
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SH4_NOFPU_NEXT
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},
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{
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32, /* 32 bits in a word */
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32, /* 32 bits in an address */
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8, /* 8 bits in a byte */
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bfd_arch_sh,
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bfd_mach_sh4_nommu_nofpu,
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"sh", /* arch_name */
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"sh4-nommu-nofpu", /* printable name */
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1,
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FALSE, /* not the default */
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bfd_default_compatible,
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bfd_default_scan,
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SH4_NOMMU_NOFPU_NEXT
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},
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{
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32, /* 32 bits in a word */
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32, /* 32 bits in an address */
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@ -1,5 +1,5 @@
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/* Renesas / SuperH SH specific support for 32-bit ELF
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
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Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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Contributed by Ian Lance Taylor, Cygnus Support.
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@ -6876,6 +6876,9 @@ sh_elf_set_mach_from_flags (bfd *abfd)
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case EF_SH4AL_DSP:
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bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4al_dsp);
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break;
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case EF_SH4_NOMMU_NOFPU:
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bfd_default_set_arch_mach (abfd, bfd_arch_sh, bfd_mach_sh4_nommu_nofpu);
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break;
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default:
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return FALSE;
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}
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@ -1,3 +1,12 @@
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2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
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* config/tc-sh.c (md_parse_option): Add -isa=sh4-nofpu and
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-isa=sh4-nommu-nofpu options. Adjust help messages accordingly.
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(sh_elf_final_processing): Output BFD type sh4_nofpu if that is
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the most general type or the user specifically requested it.
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(md_assemble): Add a new error message for when an instruction
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is understood, but is not allowed due to an -isa option.
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2004-03-02 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-ia64.c (align_frag): New.
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@ -2587,6 +2587,7 @@ md_assemble (char *str)
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sh_operand_info operand[3];
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sh_opcode_info *opcode;
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unsigned int size = 0;
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char *initial_str = str;
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#ifdef HAVE_SH64
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if (sh64_isa_mode == sh64_isa_shmedia)
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@ -2613,7 +2614,45 @@ md_assemble (char *str)
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if (opcode == NULL)
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{
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as_bad (_("unknown opcode"));
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/* The opcode is not in the hash table.
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This means we definately have an assembly failure,
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but the instruction may be valid in another CPU variant.
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In this case emit something better than 'unknown opcode'.
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Search the full table in sh-opc.h to check. */
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char *name = initial_str;
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int name_length = 0;
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const sh_opcode_info *op;
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int found = 0;
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/* identify opcode in string */
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while (isspace (*name))
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{
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name++;
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}
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while (!isspace (name[name_length]))
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{
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name_length++;
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}
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/* search for opcode in full list */
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for (op = sh_table; op->name; op++)
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{
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if (strncasecmp (op->name, name, name_length) == 0)
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{
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found = 1;
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break;
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}
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}
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if ( found )
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{
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as_bad (_("opcode not valid for this cpu variant"));
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}
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else
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{
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as_bad (_("unknown opcode"));
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}
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return;
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}
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@ -2895,6 +2934,10 @@ md_parse_option (int c, char *arg ATTRIBUTE_UNUSED)
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case OPTION_ISA:
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if (strcasecmp (arg, "sh4") == 0)
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preset_target_arch = arch_sh4;
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else if (strcasecmp (arg, "sh4-nofpu") == 0)
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preset_target_arch = arch_sh4_nofpu;
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else if (strcasecmp (arg, "sh4-nommu-nofpu") == 0)
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preset_target_arch = arch_sh4_nommu_nofpu;
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else if (strcasecmp (arg, "sh4a") == 0)
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preset_target_arch = arch_sh4a;
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else if (strcasecmp (arg, "dsp") == 0)
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@ -2976,17 +3019,20 @@ SH options:\n\
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-big generate big endian code\n\
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-relax alter jump instructions for long displacements\n\
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-small align sections to 4 byte boundaries, not 16\n\
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-dsp enable sh-dsp insns, and disable floating-point ISAs.\n"));
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-dsp enable sh-dsp insns, and disable floating-point ISAs.\n\
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-isa=[sh4\n\
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| sh4-nofpu sh4 with fpu disabled\n\
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| sh4-nommu-nofpu sh4 with no MMU or FPU\n\
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| sh4a\n\
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| dsp same as '-dsp'\n\
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| fp\n\
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| any] use most appropriate isa\n"));
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#ifdef HAVE_SH64
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fprintf (stream, _("\
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-isa=[sh4\n\
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| sh4a\n\
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| dsp same as '-dsp'\n\
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| fp\n\
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| shmedia set as the default instruction set for SH64\n\
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-isa=[shmedia set as the default instruction set for SH64\n\
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| SHmedia\n\
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| shcompact\n\
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| SHcompact\n"));
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| SHcompact]\n"));
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fprintf (stream, _("\
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-abi=[32|64] set size of expanded SHmedia operands and object\n\
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file type\n\
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@ -2997,13 +3043,6 @@ SH options:\n\
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-no-expand do not expand MOVI, PT, PTA or PTB instructions\n\
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-expand-pt32 with -abi=64, expand PT, PTA and PTB instructions\n\
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to 32 bits only\n"));
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#else
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fprintf (stream, _("\
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-isa=[sh4\n\
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| sh4a\n\
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| dsp same as '-dsp'\n\
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| fp\n\
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| any]\n"));
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#endif /* HAVE_SH64 */
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}
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@ -3563,6 +3602,8 @@ sh_elf_final_processing (void)
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val = EF_SH3_DSP;
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else if (valid_arch & arch_sh3e)
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val = EF_SH3E;
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else if (valid_arch & arch_sh4_nommu_nofpu)
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val = EF_SH4_NOMMU_NOFPU;
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else if (valid_arch & arch_sh4_nofpu)
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val = EF_SH4_NOFPU;
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else if (valid_arch & arch_sh4)
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@ -1,3 +1,7 @@
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2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh.h: Add EF_SH4_NOMMU_NOFPU.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define.
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@ -1,5 +1,5 @@
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/* SH ELF support for BFD.
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Copyright 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
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Copyright 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
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This file is part of BFD, the Binary File Descriptor library.
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@ -39,6 +39,7 @@
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#define EF_SH4_NOFPU 0x10
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#define EF_SH4A_NOFPU 0x11
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#define EF_SH4_NOMMU_NOFPU 0x12
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/* This one can only mix in objects from other EF_SH5 objects. */
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#define EF_SH5 10
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@ -1,3 +1,10 @@
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2003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
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* sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
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nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
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* sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
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accordingly.
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2004-03-01 Richard Sandiford <rsandifo@redhat.com>
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* frv-asm.c: Regenerate.
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@ -1,5 +1,5 @@
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/* Disassemble SH instructions.
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Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003
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Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
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Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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@ -433,8 +433,10 @@ print_insn_sh (memaddr, info)
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case bfd_mach_sh3e:
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target_arch = arch_sh3e;
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break;
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case bfd_mach_sh4:
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case bfd_mach_sh4_nofpu:
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target_arch = arch_sh4_nofpu;
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break;
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case bfd_mach_sh4:
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target_arch = arch_sh4;
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break;
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case bfd_mach_sh4a:
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@ -444,6 +446,9 @@ print_insn_sh (memaddr, info)
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case bfd_mach_sh4al_dsp:
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target_arch = arch_sh4al_dsp;
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break;
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case bfd_mach_sh4_nommu_nofpu:
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target_arch = arch_sh4_nommu_nofpu;
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break;
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case bfd_mach_sh5:
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#ifdef INCLUDE_SHMEDIA
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status = print_insn_sh64 (memaddr, info);
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@ -1,5 +1,5 @@
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/* Definitions for SH opcodes.
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Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003
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Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003, 2004
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Free Software Foundation, Inc.
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This program is free software; you can redistribute it and/or modify
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@ -188,12 +188,13 @@ sh_dsp_reg_nums;
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#define arch_sh4al_dsp 0x0400
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#define arch_sh4_nofpu 0x1000
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#define arch_sh4a_nofpu 0x2000
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#define arch_sh4_nommu_nofpu 0x4000 /* no mmu nor fpu */
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#define arch_sh1_up (arch_sh1 | arch_sh2_up)
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#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp)
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#define arch_sh2e_up (arch_sh2e | arch_sh3e_up)
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#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
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| arch_sh4_nofp_up)
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| arch_sh4_nommu_nofpu_up)
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#define arch_sh3e_up (arch_sh3e | arch_sh4_up)
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#define arch_sh4_up (arch_sh4 | arch_sh4a_up)
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#define arch_sh4a_up (arch_sh4a)
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@ -202,9 +203,14 @@ sh_dsp_reg_nums;
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#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up)
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#define arch_sh4al_dsp_up (arch_sh4al_dsp)
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#define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
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#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
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#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
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#define arch_sh_any_with_mmu (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \
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| arch_sh4_nofp_up) /* arch _sh3_up omitting arch_sh4_nommu_nofpu */
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typedef struct
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{
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char *name;
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@ -297,6 +303,8 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn00011110 ldc <REG_N>,GBR */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
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/* 0100nnnn00111010 ldc <REG_N>,SGR */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
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/* 0100nnnn00101110 ldc <REG_N>,VBR */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
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/* 0100nnnn01011110 ldc <REG_N>,MOD */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
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@ -309,7 +317,7 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up},
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/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
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/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
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/* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up},
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@ -319,6 +327,8 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
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/* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
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/* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
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/* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
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@ -329,7 +339,7 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up},
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/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up},
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/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
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/* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up},
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@ -384,7 +394,7 @@ const sh_opcode_info sh_table[] =
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/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
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/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
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/* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh_any_with_mmu},
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/* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
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@ -457,7 +467,7 @@ const sh_opcode_info sh_table[] =
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/* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
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/* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
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/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up},
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/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
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/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
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||||
/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
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||||
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|
@ -482,11 +492,11 @@ const sh_opcode_info sh_table[] =
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/* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
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||||
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||||
/* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
|
||||
/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up},
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||||
/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up},
|
||||
/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up},
|
||||
/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
|
||||
/* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
|
||||
|
|
@ -495,7 +505,7 @@ const sh_opcode_info sh_table[] =
|
|||
|
||||
/* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
|
||||
|
||||
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up},
|
||||
/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
|
||||
|
||||
|
|
@ -567,9 +577,9 @@ const sh_opcode_info sh_table[] =
|
|||
|
||||
/* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up},
|
||||
|
||||
/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up},
|
||||
/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up},
|
||||
/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up},
|
||||
|
||||
|
|
@ -589,9 +599,9 @@ const sh_opcode_info sh_table[] =
|
|||
|
||||
/* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
|
||||
|
||||
/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up},
|
||||
/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up},
|
||||
/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
|
||||
|
||||
/* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up},
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue