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arm: opcodes: remove Maverick disassembly.

Browse source 
Remove the patterns to match Maverick co-processor instructions from
the disassembly tables.

This required fixing a couple of tests in the assembler testsuite
where we, probably incorrectly, disassembled generic co-processor
instructions as a Maverick instruction (it particularly made no sense
to do this for Armv6t2 in Thumb state).
This commit is contained in:
Richard Earnshaw 2024-04-29 13:59:38 +01:00
parent e06a561b73
commit ad5da6e6d8
4 changed files with 12 additions and 191 deletions
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8
gas/testsuite/gas/arm/copro-arm_v2plus-arm_v2.d
View file

@ -9,15 +9,15 @@
Disassembly of section .text: Disassembly of section .text:
0+000 <[^>]*> ee421103 dvfs f1, f2, f3 0+000 <[^>]*> ee421103 dvfs f1, f2, f3
0+004 <[^>]*> 0e3414a5 cfadddeq mvd1, mvd4, mvd5 0+004 <[^>]*> 0e3414a5 cdpeq 4, 3, cr1, cr4, cr5, \{5\}
0+008 <[^>]*> ed939500 cfldr32 mvfx9, \[r3\] 0+008 <[^>]*> ed939500 ldc 5, cr9, \[r3\]
0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\] 0+00c <[^>]*> edd1e108 ldfp f6, \[r1, #32\]
0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.* 0+010 <[^>]*> 4db200ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.* 0+014 <[^>]*> 5cf31710 ldclpl 7, cr1, \[r3\], #64.*
0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] @ .* <foo> 0+018 <[^>]*> ed1f8001 ldc 0, cr8, \[pc, #-4\] @ .* <foo>
0+01c <[^>]*> ed830500 cfstr32 mvfx0, \[r3\] 0+01c <[^>]*> ed830500 stc 5, cr0, \[r3\]
0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\] 0+020 <[^>]*> edc0f302 stcl 3, cr15, \[r0, #8\]
0+024 <[^>]*> 0da2c419 cfstrseq mvf12, \[r2, #100\]!.* 0+024 <[^>]*> 0da2c419 stceq 4, cr12, \[r2, #100\]! @.*
0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.* 0+028 <[^>]*> 3ca4860c stccc 6, cr8, \[r4\], #48.*
0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] @ .* <bar> 0+02c <[^>]*> ed0f7101 stfs f7, \[pc, #-4\] @ .* <bar>
0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\} 0+030 <[^>]*> ee715212 mrc 2, 3, r5, cr1, cr2, \{0\}

8
gas/testsuite/gas/arm/copro-thumb_v6t2plus-thumb_v6t2-1.d
View file

@ -10,17 +10,17 @@
Disassembly of section .text: Disassembly of section .text:
0+000 <[^>]*> ee42 1103 dvfs f1, f2, f3 0+000 <[^>]*> ee42 1103 dvfs f1, f2, f3
0+004 <[^>]*> [^ ]* it eq 0+004 <[^>]*> [^ ]* it eq
0+006 <[^>]*> ee34 14a5 cfadddeq mvd1, mvd4, mvd5 0+006 <[^>]*> ee34 14a5 cdpeq 4, 3, cr1, cr4, cr5, \{5\}
0+00a <[^>]*> ed93 9500 cfldr32 mvfx9, \[r3\] 0+00a <[^>]*> ed93 9500 ldc 5, cr9, \[r3\]
0+00e <[^>]*> edd1 e108 ldfp f6, \[r1, #32\] 0+00e <[^>]*> edd1 e108 ldfp f6, \[r1, #32\]
0+012 <[^>]*> [^ ]* ite mi 0+012 <[^>]*> [^ ]* ite mi
0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.* 0+014 <[^>]*> edb2 00ff ldcmi 0, cr0, \[r2, #1020\]!.*
0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.* 0+018 <[^>]*> ecf3 1710 ldclpl 7, cr1, \[r3\], #64.*
0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] @ .* <foo> 0+01c <[^>]*> ed9f 8000 ldc 0, cr8, \[pc] @ .* <foo>
0+020 <[^>]*> ed83 0500 cfstr32 mvfx0, \[r3\] 0+020 <[^>]*> ed83 0500 stc 5, cr0, \[r3\]
0+024 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\] 0+024 <[^>]*> edc0 f302 stcl 3, cr15, \[r0, #8\]
0+028 <[^>]*> [^ ]* it eq 0+028 <[^>]*> [^ ]* it eq
0+02a <[^>]*> eda2 c419 cfstrseq mvf12, \[r2, #100\]!.* 0+02a <[^>]*> eda2 c419 stceq 4, cr12, \[r2, #100\]! @.*
0+02e <[^>]*> [^ ]* it cc 0+02e <[^>]*> [^ ]* it cc
0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.* 0+030 <[^>]*> eca4 860c stccc 6, cr8, \[r4\], #48.*
0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] @ .* <bar> 0+034 <[^>]*> ed8f 7100 stfs f7, \[pc\] @ .* <bar>

8
include/opcode/arm.h
View file

@ -98,7 +98,7 @@
/* Co-processor space extensions. */ /* Co-processor space extensions. */
#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ /* unused 0x00000002 */
#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology
coprocessor. */ coprocessor. */
#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology #define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology
@ -107,7 +107,7 @@
#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */ #define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */ #define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */ /* unused 0x10000000 */
#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
@ -325,8 +325,6 @@
#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE) #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
#define FPU_ARCH_MAVERICK ARM_FEATURE_COPROC (FPU_MAVERICK)
#define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1) #define ARM_ARCH_V1 ARM_FEATURE_CORE_LOW (ARM_AEXT_V1)
#define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2) #define ARM_ARCH_V2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V2)
#define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S) #define ARM_ARCH_V2S ARM_FEATURE_CORE_LOW (ARM_AEXT_V2S)
@ -409,7 +407,7 @@
#define ARM_ARCH_UNKNOWN ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1) /* Machine type is unknown. */ #define ARM_ARCH_UNKNOWN ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, -1) /* Machine type is unknown. */
#define ARM_ANY ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0) /* Any basic core. */ #define ARM_ANY ARM_FEATURE_ALL (-1, -1 & ~(ARM_EXT2_MVE | ARM_EXT2_MVE_FP), -1, 0) /* Any basic core. */
#define FPU_ANY ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU. */ #define FPU_ANY ARM_FEATURE_COPROC (-1 & ~(ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)) /* Any FPU. */
#define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD)
/* Extensions containing some Thumb-2 instructions. If any is present, Thumb /* Extensions containing some Thumb-2 instructions. If any is present, Thumb
ISA is Thumb-2. */ ISA is Thumb-2. */
#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \ #define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \

179
opcodes/arm-dis.c
View file

@ -1041,180 +1041,6 @@ static const struct sopcode32 coprocessor_opcodes[] =
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1), {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_V1),
0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"}, 0x0e800b00, 0x0fb00f50, "vdiv%c.f64\t%z1, %z2, %z0"},
/* Cirrus coprocessor instructions. */
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100400, 0x0f500f00, "cfldrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500400, 0x0f500f00, "cfldrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c100500, 0x0f500f00, "cfldr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c500500, 0x0f500f00, "cfldr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000400, 0x0f500f00, "cfstrs%c\t%{R:mvf%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400400, 0x0f500f00, "cfstrd%c\t%{R:mvd%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c000500, 0x0f500f00, "cfstr32%c\t%{R:mvfx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0d400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0c400500, 0x0f500f00, "cfstr64%c\t%{R:mvdx%12-15d%}, %A"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000450, 0x0ff00ff0, "cfmvsr%c\t%{R:mvf%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000410, 0x0ff00ff0, "cfmvdlr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000430, 0x0ff00ff0, "cfmvdhr%c\t%{R:mvd%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000510, 0x0ff00fff, "cfmv64lr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000530, 0x0ff00fff, "cfmv64hr%c\t%{R:mvdx%16-19d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200440, 0x0ff00fff, "cfmval32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100440, 0x0ff00fff, "cfmv32al%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200460, 0x0ff00fff, "cfmvam32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100460, 0x0ff00fff, "cfmv32am%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200480, 0x0ff00fff, "cfmvah32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100480, 0x0ff00fff, "cfmv32ah%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004a0, 0x0ff00fff, "cfmva32%c\t%{R:mvax%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004a0, 0x0ff00fff, "cfmv32a%c\t%{R:mvfx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004c0, 0x0ff00fff, "cfmva64%c\t%{R:mvax%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004c0, 0x0ff00fff, "cfmv64a%c\t%{R:mvdx%12-15d%}, %{R:mvax%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\t%{R:dspsc%}, %{R:mvdx%12-15d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\t%{R:mvdx%12-15d%}, %{R:dspsc%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000400, 0x0ff00fff, "cfcpys%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000420, 0x0ff00fff, "cfcpyd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000460, 0x0ff00fff, "cfcvtsd%c\t%{R:mvd%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000440, 0x0ff00fff, "cfcvtds%c\t%{R:mvf%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000480, 0x0ff00fff, "cfcvt32s%c\t%{R:mvf%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\t%{R:mvd%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\t%{R:mvf%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\t%{R:mvd%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100580, 0x0ff00fff, "cfcvts32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005c0, 0x0ff00fff, "cftruncs32%c\t%{R:mvfx%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005e0, 0x0ff00fff, "cftruncd32%c\t%{R:mvfx%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000550, 0x0ff00ff0, "cfrshl32%c\t%{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000570, 0x0ff00ff0, "cfrshl64%c\t%{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}, %12-15r"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000500, 0x0ff00f10, "cfsh32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200500, 0x0ff00f10, "cfsh64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{I:#%I%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300400, 0x0ff00fff, "cfabss%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300420, 0x0ff00fff, "cfabsd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300440, 0x0ff00fff, "cfnegs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300460, 0x0ff00fff, "cfnegd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300480, 0x0ff00ff0, "cfadds%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004a0, 0x0ff00ff0, "cfaddd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004c0, 0x0ff00ff0, "cfsubs%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3004e0, 0x0ff00ff0, "cfsubd%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100400, 0x0ff00ff0, "cfmuls%c\t%{R:mvf%12-15d%}, %{R:mvf%16-19d%}, %{R:mvf%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100420, 0x0ff00ff0, "cfmuld%c\t%{R:mvd%12-15d%}, %{R:mvd%16-19d%}, %{R:mvd%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300500, 0x0ff00fff, "cfabs32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300520, 0x0ff00fff, "cfabs64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300540, 0x0ff00fff, "cfneg32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300560, 0x0ff00fff, "cfneg64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300580, 0x0ff00ff0, "cfadd32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005a0, 0x0ff00ff0, "cfadd64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005c0, 0x0ff00ff0, "cfsub32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e3005e0, 0x0ff00ff0, "cfsub64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100500, 0x0ff00ff0, "cfmul32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100520, 0x0ff00ff0, "cfmul64%c\t%{R:mvdx%12-15d%}, %{R:mvdx%16-19d%}, %{R:mvdx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100540, 0x0ff00ff0, "cfmac32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100560, 0x0ff00ff0, "cfmsc32%c\t%{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e000600, 0x0ff00f10,
"cfmadd32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e100600, 0x0ff00f10,
"cfmsub32%c\t%{R:mvax%5-7d%}, %{R:mvfx%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e200600, 0x0ff00f10,
"cfmadda32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
{ANY, ARM_FEATURE_COPROC (ARM_CEXT_MAVERICK),
0x0e300600, 0x0ff00f10,
"cfmsuba32%c\t%{R:mvax%5-7d%}, %{R:mvax%12-15d%}, %{R:mvfx%16-19d%}, %{R:mvfx%0-3d%}"},
/* VFP Fused multiply add instructions. */ /* VFP Fused multiply add instructions. */
{ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA), {ANY, ARM_FEATURE_COPROC (FPU_VFP_EXT_FMA),
0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"}, 0x0ea00a00, 0x0fb00f50, "vfma%c.f32\t%y1, %y2, %y0"},
@ -12650,15 +12476,12 @@ select_arm_features (unsigned long mach,
case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break; case bfd_mach_arm_3: ARM_SET_FEATURES (ARM_ARCH_V3); break;
case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break; case bfd_mach_arm_3M: ARM_SET_FEATURES (ARM_ARCH_V3M); break;
case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break; case bfd_mach_arm_4: ARM_SET_FEATURES (ARM_ARCH_V4); break;
case bfd_mach_arm_ep9312:
case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break; case bfd_mach_arm_4T: ARM_SET_FEATURES (ARM_ARCH_V4T); break;
case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break; case bfd_mach_arm_5: ARM_SET_FEATURES (ARM_ARCH_V5); break;
case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break; case bfd_mach_arm_5T: ARM_SET_FEATURES (ARM_ARCH_V5T); break;
case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break; case bfd_mach_arm_5TE: ARM_SET_FEATURES (ARM_ARCH_V5TE); break;
case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break; case bfd_mach_arm_XScale: ARM_SET_FEATURES (ARM_ARCH_XSCALE); break;
case bfd_mach_arm_ep9312:
ARM_SET_FEATURES (ARM_FEATURE_LOW (ARM_AEXT_V4T,
ARM_CEXT_MAVERICK | FPU_MAVERICK));
break;
case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break; case bfd_mach_arm_iWMMXt: ARM_SET_FEATURES (ARM_ARCH_IWMMXT); break;
case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break; case bfd_mach_arm_iWMMXt2: ARM_SET_FEATURES (ARM_ARCH_IWMMXT2); break;
case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break; case bfd_mach_arm_5TEJ: ARM_SET_FEATURES (ARM_ARCH_V5TEJ); break;