[MIPS] Add Loongson 3A1000 proccessor support.
bfd/ * archures.c (bfd_architecture): Rename bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464. * bfd-in2.h (bfd_architecture): Likewise. * cpu-mips.c (enum I_xxx): Likewise. (arch_info_struct): Likewise. * elfxx-mips.c (_bfd_elf_mips_mach): Likewise. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Likewise. (bfd_mips_isa_ext_mach): Likewise. (bfd_mips_isa_ext): Likewise. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. binutils/ * NEWS: Mention Loongson 3A1000 proccessor support. * readelf.c (get_machine_flags): Rename loongson-3a to gs464. (print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A. elfcpp/ * mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. gas/ * config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename CPU_LOONGSON_3A to CPU_GS464. (mips_cpu_info_table): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * doc/as.texi (march table): Rename loongson3a to gs464. * testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension" flag to None. gold/ * mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach): Rename loongson3a to gs464. (mips_isa_ext_mach, mips_isa_ext): Delete loongson3a. (infer_abiflags): Use ases instead of isa_ext for infer ABI flags. (elf_mips_mach_name): Rename loongson3a to gs464. include/ * elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to E_MIPS_MACH_GS464. (AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A. * opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A. (CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464. * opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case. ld/ * testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a to gs464. opcodes/ * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep loongson3a as an alias of gs464 for compatibility. * mips-opc.c (mips_opcodes): Change Comments.
This commit is contained in:
Chenghua Xu
parent
a693765e23
commit
ac8cb70f36
25 changed files with 109 additions and 50 deletions
|
|
@ -1,3 +1,17 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* archures.c (bfd_architecture): Rename
|
||||
bfd_mach_mips_loongson_3a to bfd_mach_mips_gs464.
|
||||
* bfd-in2.h (bfd_architecture): Likewise.
|
||||
* cpu-mips.c (enum I_xxx): Likewise.
|
||||
(arch_info_struct): Likewise.
|
||||
* elfxx-mips.c (_bfd_elf_mips_mach): Likewise.
|
||||
(mips_set_isa_flags): Likewise.
|
||||
(mips_mach_extensions): Likewise.
|
||||
(bfd_mips_isa_ext_mach): Likewise.
|
||||
(bfd_mips_isa_ext): Likewise.
|
||||
(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* elfxx-mips.c (print_mips_ases): Add Loongson EXT2 extension.
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ DESCRIPTION
|
|||
.#define bfd_mach_mips5 5
|
||||
.#define bfd_mach_mips_loongson_2e 3001
|
||||
.#define bfd_mach_mips_loongson_2f 3002
|
||||
.#define bfd_mach_mips_loongson_3a 3003
|
||||
.#define bfd_mach_mips_gs464 3003
|
||||
.#define bfd_mach_mips_sb1 12310201 {* octal 'SB', 01. *}
|
||||
.#define bfd_mach_mips_octeon 6501
|
||||
.#define bfd_mach_mips_octeonp 6601
|
||||
|
|
|
|||
|
|
@ -2069,7 +2069,7 @@ enum bfd_architecture
|
|||
#define bfd_mach_mips5 5
|
||||
#define bfd_mach_mips_loongson_2e 3001
|
||||
#define bfd_mach_mips_loongson_2f 3002
|
||||
#define bfd_mach_mips_loongson_3a 3003
|
||||
#define bfd_mach_mips_gs464 3003
|
||||
#define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01. */
|
||||
#define bfd_mach_mips_octeon 6501
|
||||
#define bfd_mach_mips_octeonp 6601
|
||||
|
|
|
|||
|
|
@ -98,7 +98,7 @@ enum
|
|||
I_sb1,
|
||||
I_loongson_2e,
|
||||
I_loongson_2f,
|
||||
I_loongson_3a,
|
||||
I_gs464,
|
||||
I_mipsocteon,
|
||||
I_mipsocteonp,
|
||||
I_mipsocteon2,
|
||||
|
|
@ -150,7 +150,7 @@ static const bfd_arch_info_type arch_info_struct[] =
|
|||
N (64, 64, bfd_mach_mips_sb1, "mips:sb1", FALSE, NN(I_sb1)),
|
||||
N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e", FALSE, NN(I_loongson_2e)),
|
||||
N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f", FALSE, NN(I_loongson_2f)),
|
||||
N (64, 64, bfd_mach_mips_loongson_3a, "mips:loongson_3a", FALSE, NN(I_loongson_3a)),
|
||||
N (64, 64, bfd_mach_mips_gs464, "mips:gs464", FALSE, NN(I_gs464)),
|
||||
N (64, 64, bfd_mach_mips_octeon,"mips:octeon", FALSE, NN(I_mipsocteon)),
|
||||
N (64, 64, bfd_mach_mips_octeonp,"mips:octeon+", FALSE, NN(I_mipsocteonp)),
|
||||
N (64, 64, bfd_mach_mips_octeon2,"mips:octeon2", FALSE, NN(I_mipsocteon2)),
|
||||
|
|
|
|||
|
|
@ -6787,8 +6787,8 @@ _bfd_elf_mips_mach (flagword flags)
|
|||
case E_MIPS_MACH_LS2F:
|
||||
return bfd_mach_mips_loongson_2f;
|
||||
|
||||
case E_MIPS_MACH_LS3A:
|
||||
return bfd_mach_mips_loongson_3a;
|
||||
case E_MIPS_MACH_GS464:
|
||||
return bfd_mach_mips_gs464;
|
||||
|
||||
case E_MIPS_MACH_OCTEON3:
|
||||
return bfd_mach_mips_octeon3;
|
||||
|
|
@ -11984,8 +11984,8 @@ mips_set_isa_flags (bfd *abfd)
|
|||
val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
|
||||
break;
|
||||
|
||||
case bfd_mach_mips_loongson_3a:
|
||||
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_LS3A;
|
||||
case bfd_mach_mips_gs464:
|
||||
val = E_MIPS_ARCH_64R2 | E_MIPS_MACH_GS464;
|
||||
break;
|
||||
|
||||
case bfd_mach_mips_octeon:
|
||||
|
|
@ -13993,7 +13993,7 @@ static const struct mips_mach_extension mips_mach_extensions[] =
|
|||
{ bfd_mach_mips_octeon2, bfd_mach_mips_octeonp },
|
||||
{ bfd_mach_mips_octeonp, bfd_mach_mips_octeon },
|
||||
{ bfd_mach_mips_octeon, bfd_mach_mipsisa64r2 },
|
||||
{ bfd_mach_mips_loongson_3a, bfd_mach_mipsisa64r2 },
|
||||
{ bfd_mach_mips_gs464, bfd_mach_mipsisa64r2 },
|
||||
|
||||
/* MIPS64 extensions. */
|
||||
{ bfd_mach_mipsisa64r2, bfd_mach_mipsisa64 },
|
||||
|
|
@ -14105,7 +14105,6 @@ bfd_mips_isa_ext_mach (unsigned int isa_ext)
|
|||
case AFL_EXT_10000: return bfd_mach_mips10000;
|
||||
case AFL_EXT_LOONGSON_2E: return bfd_mach_mips_loongson_2e;
|
||||
case AFL_EXT_LOONGSON_2F: return bfd_mach_mips_loongson_2f;
|
||||
case AFL_EXT_LOONGSON_3A: return bfd_mach_mips_loongson_3a;
|
||||
case AFL_EXT_SB1: return bfd_mach_mips_sb1;
|
||||
case AFL_EXT_OCTEON: return bfd_mach_mips_octeon;
|
||||
case AFL_EXT_OCTEONP: return bfd_mach_mips_octeonp;
|
||||
|
|
@ -14134,7 +14133,6 @@ bfd_mips_isa_ext (bfd *abfd)
|
|||
case bfd_mach_mips10000: return AFL_EXT_10000;
|
||||
case bfd_mach_mips_loongson_2e: return AFL_EXT_LOONGSON_2E;
|
||||
case bfd_mach_mips_loongson_2f: return AFL_EXT_LOONGSON_2F;
|
||||
case bfd_mach_mips_loongson_3a: return AFL_EXT_LOONGSON_3A;
|
||||
case bfd_mach_mips_sb1: return AFL_EXT_SB1;
|
||||
case bfd_mach_mips_octeon: return AFL_EXT_OCTEON;
|
||||
case bfd_mach_mips_octeonp: return AFL_EXT_OCTEONP;
|
||||
|
|
@ -15709,9 +15707,6 @@ print_mips_isa_ext (FILE *file, unsigned int isa_ext)
|
|||
case AFL_EXT_OCTEONP:
|
||||
fputs ("Cavium Networks OcteonP", file);
|
||||
break;
|
||||
case AFL_EXT_LOONGSON_3A:
|
||||
fputs ("Loongson 3A", file);
|
||||
break;
|
||||
case AFL_EXT_OCTEON:
|
||||
fputs ("Cavium Networks Octeon", file);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* NEWS: Mention Loongson 3A1000 proccessor support.
|
||||
* readelf.c (get_machine_flags): Rename loongson-3a to gs464.
|
||||
(print_mips_isa_ext): Delete AFL_EXT_LOONGSON_3A.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* readelf.c (print_mips_ases): Add Loongson EXT2 extension.
|
||||
|
|
|
|||
|
|
@ -1,5 +1,11 @@
|
|||
-*- text -*-
|
||||
|
||||
* The MIPS port now supports the Loongson 3A1000 processor, aka Loongson3a,
|
||||
which implements the MIPS64r2 ISA, the Loongson-mmi ASE, Loongson-cam ASE
|
||||
and Loongson-ext ASE instructions. Add -march=gs464 option for Loongson
|
||||
3A1000 processor, The -march=loongson3a is an alias of -march=gs464 for
|
||||
compatibility.
|
||||
|
||||
Changes in 2.31:
|
||||
|
||||
* Add support for disassembling netronome Flow Processor (NFP) firmware files.
|
||||
|
|
|
|||
|
|
@ -3404,7 +3404,7 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
|
|||
case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
|
||||
case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
|
||||
case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
|
||||
case E_MIPS_MACH_LS3A: strcat (buf, ", loongson-3a"); break;
|
||||
case E_MIPS_MACH_GS464: strcat (buf, ", gs464"); break;
|
||||
case E_MIPS_MACH_OCTEON: strcat (buf, ", octeon"); break;
|
||||
case E_MIPS_MACH_OCTEON2: strcat (buf, ", octeon2"); break;
|
||||
case E_MIPS_MACH_OCTEON3: strcat (buf, ", octeon3"); break;
|
||||
|
|
@ -15683,9 +15683,6 @@ print_mips_isa_ext (unsigned int isa_ext)
|
|||
case AFL_EXT_OCTEONP:
|
||||
fputs ("Cavium Networks OcteonP", stdout);
|
||||
break;
|
||||
case AFL_EXT_LOONGSON_3A:
|
||||
fputs ("Loongson 3A", stdout);
|
||||
break;
|
||||
case AFL_EXT_OCTEON:
|
||||
fputs ("Cavium Networks Octeon", stdout);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* mips.c (EF_MIPS_MACH): Rename E_MIPS_MACH_LS3A to
|
||||
E_MIPS_MACH_GS464.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* mips.h (AFL_ASE_LOONGSON_EXT): New enum.
|
||||
|
|
|
|||
|
|
@ -235,7 +235,7 @@ enum
|
|||
E_MIPS_MACH_9000 = 0x00990000,
|
||||
E_MIPS_MACH_LS2E = 0x00A00000,
|
||||
E_MIPS_MACH_LS2F = 0x00A10000,
|
||||
E_MIPS_MACH_LS3A = 0x00A20000,
|
||||
E_MIPS_MACH_GS464 = 0x00A20000,
|
||||
};
|
||||
|
||||
// MIPS architecture
|
||||
|
|
|
|||
|
|
@ -1,3 +1,13 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* config/tc-mips.c (ISA_HAS_ODD_SINGLE_FPR): Rename
|
||||
CPU_LOONGSON_3A to CPU_GS464.
|
||||
(mips_cpu_info_table): Add gs464 descriptors, Keep
|
||||
loongson3a as an alias of gs464 for compatibility.
|
||||
* doc/as.texi (march table): Rename loongson3a to gs464.
|
||||
* testsuite/gas/mips/loongson-3a-mmi.d: Set "ISA Extension"
|
||||
flag to None.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* NEWS: Mention Loongson EXTensions R2 (EXT2) support.
|
||||
|
|
|
|||
|
|
@ -422,7 +422,7 @@ static int mips_32bitmode = 0;
|
|||
|| (ISA) == ISA_MIPS64R5 \
|
||||
|| (ISA) == ISA_MIPS64R6 \
|
||||
|| (CPU) == CPU_R5900) \
|
||||
&& (CPU) != CPU_LOONGSON_3A)
|
||||
&& (CPU) != CPU_GS464)
|
||||
|
||||
/* Return true if ISA supports move to/from high part of a 64-bit
|
||||
floating-point register. */
|
||||
|
|
@ -19809,8 +19809,11 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
|
|||
|
||||
/* MIPS 64 Release 2 */
|
||||
/* Loongson CPU core */
|
||||
/* -march=loongson3a is an alias of -march=gs464 for compatibility */
|
||||
{ "loongson3a", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
|
||||
ISA_MIPS64R2, CPU_LOONGSON_3A },
|
||||
ISA_MIPS64R2, CPU_GS464 },
|
||||
{ "gs464", 0, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
|
||||
ISA_MIPS64R2, CPU_GS464 },
|
||||
|
||||
/* Cavium Networks Octeon CPU core */
|
||||
{ "octeon", 0, 0, ISA_MIPS64R2, CPU_OCTEON },
|
||||
|
|
|
|||
|
|
@ -437,7 +437,7 @@ i6400,
|
|||
p6600,
|
||||
loongson2e,
|
||||
loongson2f,
|
||||
loongson3a,
|
||||
gs464,
|
||||
octeon,
|
||||
octeon+,
|
||||
octeon2,
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ GPR size: .*
|
|||
CPR1 size: .*
|
||||
CPR2 size: .*
|
||||
FP ABI: .*
|
||||
ISA Extension: Loongson 3A
|
||||
ISA Extension: None
|
||||
ASEs:
|
||||
Loongson MMI ASE
|
||||
Loongson CAM ASE
|
||||
|
|
|
|||
|
|
@ -1394,8 +1394,8 @@ if { [istarget mips*-*-vxworks*] } {
|
|||
run_dump_test "loongson-2f-mmi"
|
||||
run_dump_test "loongson-3a-mmi"
|
||||
|
||||
run_dump_test "loongson-cam"
|
||||
run_dump_test "loongson-ext2"
|
||||
run_dump_test_arches "loongson-cam" [mips_arch_list_matching gs464]
|
||||
run_dump_test_arches "loongson-ext2" [mips_arch_list_matching gs464]
|
||||
|
||||
if { $has_newabi } {
|
||||
run_dump_test_arches "octeon" [mips_arch_list_matching octeon]
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* mips.cc (Mips_mach, add_machine_extensions, elf_mips_mach):
|
||||
Rename loongson3a to gs464.
|
||||
(mips_isa_ext_mach, mips_isa_ext): Delete loongson3a.
|
||||
(infer_abiflags): Use ases instead of isa_ext for infer ABI
|
||||
flags.
|
||||
(elf_mips_mach_name): Rename loongson3a to gs464.
|
||||
|
||||
2018-07-10 Tulio Magno Quites Machado Filho <tuliom@linux.ibm.com>
|
||||
|
||||
* object.cc (Sized_relobj_file::map_to_kept_section): Initialize
|
||||
|
|
|
|||
20
gold/mips.cc
20
gold/mips.cc
|
|
@ -3982,7 +3982,7 @@ class Target_mips : public Sized_target<size, big_endian>
|
|||
mach_mips5 = 5,
|
||||
mach_mips_loongson_2e = 3001,
|
||||
mach_mips_loongson_2f = 3002,
|
||||
mach_mips_loongson_3a = 3003,
|
||||
mach_mips_gs464 = 3003,
|
||||
mach_mips_sb1 = 12310201, // octal 'SB', 01
|
||||
mach_mips_octeon = 6501,
|
||||
mach_mips_octeonp = 6601,
|
||||
|
|
@ -4148,7 +4148,7 @@ class Target_mips : public Sized_target<size, big_endian>
|
|||
this->add_extension(mach_mips_octeon2, mach_mips_octeonp);
|
||||
this->add_extension(mach_mips_octeonp, mach_mips_octeon);
|
||||
this->add_extension(mach_mips_octeon, mach_mipsisa64r2);
|
||||
this->add_extension(mach_mips_loongson_3a, mach_mipsisa64r2);
|
||||
this->add_extension(mach_mips_gs464, mach_mipsisa64r2);
|
||||
|
||||
// MIPS64 extensions.
|
||||
this->add_extension(mach_mipsisa64r2, mach_mipsisa64);
|
||||
|
|
@ -8858,8 +8858,8 @@ Target_mips<size, big_endian>::elf_mips_mach(elfcpp::Elf_Word flags)
|
|||
case elfcpp::E_MIPS_MACH_LS2F:
|
||||
return mach_mips_loongson_2f;
|
||||
|
||||
case elfcpp::E_MIPS_MACH_LS3A:
|
||||
return mach_mips_loongson_3a;
|
||||
case elfcpp::E_MIPS_MACH_GS464:
|
||||
return mach_mips_gs464;
|
||||
|
||||
case elfcpp::E_MIPS_MACH_OCTEON3:
|
||||
return mach_mips_octeon3;
|
||||
|
|
@ -8959,9 +8959,6 @@ Target_mips<size, big_endian>::mips_isa_ext_mach(unsigned int isa_ext)
|
|||
case elfcpp::AFL_EXT_LOONGSON_2F:
|
||||
return mach_mips_loongson_2f;
|
||||
|
||||
case elfcpp::AFL_EXT_LOONGSON_3A:
|
||||
return mach_mips_loongson_3a;
|
||||
|
||||
case elfcpp::AFL_EXT_SB1:
|
||||
return mach_mips_sb1;
|
||||
|
||||
|
|
@ -9026,9 +9023,6 @@ Target_mips<size, big_endian>::mips_isa_ext(unsigned int mips_mach)
|
|||
case mach_mips_loongson_2f:
|
||||
return elfcpp::AFL_EXT_LOONGSON_2F;
|
||||
|
||||
case mach_mips_loongson_3a:
|
||||
return elfcpp::AFL_EXT_LOONGSON_3A;
|
||||
|
||||
case mach_mips_sb1:
|
||||
return elfcpp::AFL_EXT_SB1;
|
||||
|
||||
|
|
@ -9160,7 +9154,7 @@ Target_mips<size, big_endian>::infer_abiflags(
|
|||
&& abiflags->fp_abi != elfcpp::Val_GNU_MIPS_ABI_FP_SOFT
|
||||
&& abiflags->fp_abi != elfcpp::Val_GNU_MIPS_ABI_FP_64A
|
||||
&& abiflags->isa_level >= 32
|
||||
&& abiflags->isa_ext != elfcpp::AFL_EXT_LOONGSON_3A)
|
||||
&& abiflags->ases != elfcpp::AFL_ASE_LOONGSON_EXT)
|
||||
abiflags->flags1 |= elfcpp::AFL_FLAGS1_ODDSPREG;
|
||||
}
|
||||
|
||||
|
|
@ -12530,8 +12524,8 @@ Target_mips<size, big_endian>::elf_mips_mach_name(elfcpp::Elf_Word e_flags)
|
|||
return "mips:loongson_2e";
|
||||
case elfcpp::E_MIPS_MACH_LS2F:
|
||||
return "mips:loongson_2f";
|
||||
case elfcpp::E_MIPS_MACH_LS3A:
|
||||
return "mips:loongson_3a";
|
||||
case elfcpp::E_MIPS_MACH_GS464:
|
||||
return "mips:gs464";
|
||||
case elfcpp::E_MIPS_MACH_OCTEON:
|
||||
return "mips:octeon";
|
||||
case elfcpp::E_MIPS_MACH_OCTEON2:
|
||||
|
|
|
|||
|
|
@ -1,3 +1,12 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* elf/mips.h (E_MIPS_MACH_XXX): Rename E_MIPS_MACH_LS3A to
|
||||
E_MIPS_MACH_GS464.
|
||||
(AFL_EXT_XXX): Delete AFL_EXT_LOONGSON_3A.
|
||||
* opcode/mips.h (INSN_XXX): Delete INSN_LOONGSON_3A.
|
||||
(CPU_XXX): Rename CPU_LOONGSON_3A to CPU_GS464.
|
||||
* opcode/mips.h (mips_isa_table): Delete CPU_LOONGSON_3A case.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* elf/mips.h (AFL_ASE_LOONGSON_EXT2): New macro.
|
||||
|
|
|
|||
|
|
@ -299,7 +299,7 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
|
|||
#define E_MIPS_MACH_9000 0x00990000
|
||||
#define E_MIPS_MACH_LS2E 0x00A00000
|
||||
#define E_MIPS_MACH_LS2F 0x00A10000
|
||||
#define E_MIPS_MACH_LS3A 0x00A20000
|
||||
#define E_MIPS_MACH_GS464 0x00A20000
|
||||
|
||||
/* Processor specific section indices. These sections do not actually
|
||||
exist. Symbols with a st_shndx field corresponding to one of these
|
||||
|
|
@ -1249,7 +1249,6 @@ extern void bfd_mips_elf_swap_abiflags_v0_out
|
|||
#define AFL_EXT_XLR 1 /* RMI Xlr instruction. */
|
||||
#define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */
|
||||
#define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */
|
||||
#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */
|
||||
#define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */
|
||||
#define AFL_EXT_5900 6 /* MIPS R5900 instruction. */
|
||||
#define AFL_EXT_4650 7 /* MIPS R4650 instruction. */
|
||||
|
|
|
|||
|
|
@ -928,7 +928,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
|
|||
"+S" Length-minus-one field of cins/exts. Requires msb position
|
||||
of the field to be <= 63.
|
||||
|
||||
Loongson-3A:
|
||||
Loongson-ext ASE:
|
||||
"+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
|
||||
"+b" 8-bit signed offset in bit 3 (OP_*_OFFSET_B)
|
||||
"+c" 9-bit signed offset in bit 6 (OP_*_OFFSET_C)
|
||||
|
|
@ -1256,8 +1256,6 @@ static const unsigned int mips_isa_table[] = {
|
|||
#define INSN_LOONGSON_2E 0x40000000
|
||||
/* ST Microelectronics Loongson 2F. */
|
||||
#define INSN_LOONGSON_2F 0x80000000
|
||||
/* Loongson 3A. */
|
||||
#define INSN_LOONGSON_3A 0x00000400
|
||||
/* RMI Xlr instruction */
|
||||
#define INSN_XLR 0x00000020
|
||||
/* Imagination interAptiv MR2. */
|
||||
|
|
@ -1374,7 +1372,7 @@ static const unsigned int mips_isa_table[] = {
|
|||
#define CPU_SB1 12310201 /* octal 'SB', 01. */
|
||||
#define CPU_LOONGSON_2E 3001
|
||||
#define CPU_LOONGSON_2F 3002
|
||||
#define CPU_LOONGSON_3A 3003
|
||||
#define CPU_GS464 3003
|
||||
#define CPU_OCTEON 6501
|
||||
#define CPU_OCTEONP 6601
|
||||
#define CPU_OCTEON2 6502
|
||||
|
|
@ -1433,9 +1431,6 @@ cpu_is_member (int cpu, unsigned int mask)
|
|||
case CPU_LOONGSON_2F:
|
||||
return (mask & INSN_LOONGSON_2F) != 0;
|
||||
|
||||
case CPU_LOONGSON_3A:
|
||||
return (mask & INSN_LOONGSON_3A) != 0;
|
||||
|
||||
case CPU_OCTEON:
|
||||
return (mask & INSN_OCTEON) != 0;
|
||||
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* testsuite/ld-mips-elf/mips-elf-flags.exp: Rename loongson3a
|
||||
to gs464.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* testsuite/ld-mips-elf/mips-elf-flags.exp (good_combination):
|
||||
|
|
|
|||
|
|
@ -242,7 +242,7 @@ isa_conflict { "-march=sb1 -32" "-mips64r2 -32" } sb1 isa64r2
|
|||
isa_conflict { "-march=vr4100 -32" "-march=r10000 -32" } 4100 8000
|
||||
isa_conflict { "-march=r5900 -32" "-march=vr4111 -32" } 5900 4111
|
||||
isa_conflict { "-march=loongson2e -32" "-march=loongson2f -32" } loongson_2e loongson_2f
|
||||
isa_conflict { "-march=loongson3a -32" "-march=loongson2f -32" } loongson_3a loongson_2f
|
||||
isa_conflict { "-march=gs464 -32" "-march=loongson2f -32" } gs464 loongson_2f
|
||||
|
||||
isa_conflict { "-march=interaptiv-mr2 -32" \
|
||||
"-march=r4010 -32" } interaptiv-mr2 4010
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
|
||||
loongson3a as an alias of gs464 for compatibility.
|
||||
* mips-opc.c (mips_opcodes): Change Comments.
|
||||
|
||||
2018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
|
||||
|
||||
* mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
|
||||
|
|
|
|||
|
|
@ -629,7 +629,13 @@ const struct mips_arch_choice mips_arch_choices[] =
|
|||
ISA_MIPS3 | INSN_LOONGSON_2F, ASE_LOONGSON_MMI, mips_cp0_names_numeric,
|
||||
NULL, 0, mips_cp1_names_numeric, mips_hwr_names_numeric },
|
||||
|
||||
{ "loongson3a", 1, bfd_mach_mips_loongson_3a, CPU_LOONGSON_3A,
|
||||
/* The loongson3a is an alias of gs464 for compatibility */
|
||||
{ "loongson3a", 1, bfd_mach_mips_gs464, CPU_GS464,
|
||||
ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
|
||||
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
|
||||
mips_hwr_names_numeric },
|
||||
|
||||
{ "g464", 1, bfd_mach_mips_gs464, CPU_GS464,
|
||||
ISA_MIPS64R2, ASE_LOONGSON_MMI | ASE_LOONGSON_CAM | ASE_LOONGSON_EXT,
|
||||
mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264,
|
||||
mips_hwr_names_numeric },
|
||||
|
|
|
|||
|
|
@ -464,7 +464,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
|
|||
{"lapc", "s,-A", 0xec000000, 0xfc180000, WR_1, RD_pc, I37, 0, 0 },
|
||||
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1, 0, 0 },
|
||||
|
||||
/* Loongson specific instructions. Loongson 3A redefines the Coprocessor 2
|
||||
/* Loongson specific instructions. Loongson gs464 (aka loongson3a) redefines the Coprocessor 2
|
||||
instructions. Put them here so that disassembler will find them first.
|
||||
The assemblers uses a hash table based on the instruction name anyhow. */
|
||||
{"campi", "d,s", 0x70000075, 0xfc1f07ff, WR_1|RD_2, 0, 0, LCAM, 0 },
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue