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* Makefile.in: Fix typo.

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* simops.c: Add condition code handling to "sub" "subr" and
        "divh" instructions.
This commit is contained in:
Jeff Law 1996-08-30 03:07:24 +00:00
parent 0ef0eba580
commit aabce0f46c
2 changed files with 79 additions and 19 deletions
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4
sim/v850/ChangeLog
View file

@ -1,5 +1,9 @@
Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com) Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com)
* Makefile.in: Fix typo.
* simops.c: Add condition code handling to "sub" "subr" and
"divh" instructions.
* interp.c (hash): Update to be more accurate. * interp.c (hash): Update to be more accurate.
(lookup_hash): Call hash rather than computing the hash (lookup_hash): Call hash rather than computing the hash
code here. code here.

94
sim/v850/simops.c
View file

@ -204,27 +204,58 @@ OP_600 ()
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0)); | (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
} }
/* sub reg1, reg2 /* sub reg1, reg2 */
XXX condition codes */
void void
OP_1A0 () OP_1A0 ()
{ {
State.regs[OP[1]] -= State.regs[OP[0]]; unsigned int op0, op1, result, z, s, cy, ov;
/* Compute the result. */
op0 = State.regs[OP[0]];
op1 = State.regs[OP[1]];
result = op1 - op0;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
cy = (result < -op0);
ov = ((op1 & 0x80000000) != (op0 & 0x80000000)
&& (op1 & 0x80000000) != (result & 0x80000000));
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
State.regs[OP[1]] = State.regs[OP[0]];
} }
/* subr reg1, reg2 /* subr reg1, reg2 */
XXX condition codes */
void void
OP_180 () OP_180 ()
{ {
State.regs[OP[1]] = State.regs[OP[0]] - State.regs[OP[1]]; unsigned int op0, op1, result, z, s, cy, ov;
/* Compute the result. */
op0 = State.regs[OP[0]];
op1 = State.regs[OP[1]];
result = op0 - op1;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
cy = (result < -op1);
ov = ((op0 & 0x80000000) != (op1 & 0x80000000)
&& (op0 & 0x80000000) != (result & 0x80000000));
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
State.psw &= ~(PSW_Z | PSW_S | PSW_CY | PSW_OV);
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
| (cy ? PSW_CY : 0) | (ov ? PSW_OV : 0));
} }
/* mulh reg1, reg2 /* mulh reg1, reg2 */
XXX condition codes */
void void
OP_E0 () OP_E0 ()
{ {
@ -245,9 +276,7 @@ OP_2E0 ()
State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value; State.regs[OP[1]] = (State.regs[OP[1]] & 0xffff) * value;
} }
/* mulhi imm16, reg1, reg2 /* mulhi imm16, reg1, reg2 */
XXX condition codes */
void void
OP_6E0 () OP_6E0 ()
{ {
@ -258,14 +287,41 @@ OP_6E0 ()
State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value; State.regs[OP[2]] = (State.regs[OP[1]] & 0xffff) * value;
} }
/* divh reg1, reg2 /* divh reg1, reg2 */
XXX condition codes.
XXX Is this signed or unsigned? */
void void
OP_40 () OP_40 ()
{ {
State.regs[OP[1]] /= (State.regs[OP[0]] & 0xffff); unsigned int op0, op1, result, z, s, cy, ov;
int temp;
/* Compute the result. */
temp = State.regs[OP[0]] & 0xffff;
temp = (temp << 16) >> 16;
op0 = temp;
op1 = State.regs[OP[1]];
if (op0 == 0xffffffff && op1 == 0x80000000)
{
result = 0x80000000;
ov = 1;
}
else if (op0 != 0)
{
result = op1 / op0;
ov = 0;
}
else
ov = 1;
/* Compute the condition codes. */
z = (result == 0);
s = (result & 0x80000000);
/* Store the result and condition codes. */
State.regs[OP[1]] = result;
State.psw &= ~(PSW_Z | PSW_S | PSW_OV);
State.psw |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)
| (ov ? PSW_OV : 0));
} }
void void