aarch64: Make SME instructions use F_STRICT
This patch makes all SME instructions use F_STRICT, so that qualifiers have to be provided explicitly rather than being inferred from other operands. The main change is to move the qualifier setting from the operand-level decoders to the opcode level. This is one step towards consolidating the ZA parsing code and extending it to handle SME2.
This commit is contained in:
Richard Sandiford
parent
eee2ecccda
commit
a5791d5814
4 changed files with 69 additions and 62 deletions
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@ -659,7 +659,9 @@ enum aarch64_insn_class
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pcreladdr,
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ic_system,
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sme_misc,
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sme_mov,
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sme_ldr,
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sme_psel,
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sme_str,
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sme_start,
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sme_stop,
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@ -1852,6 +1852,11 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
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int variant = 0;
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switch (inst->opcode->iclass)
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{
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case sme_mov:
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case sme_psel:
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/* The variant is encoded as part of the immediate. */
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break;
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case sve_cpy:
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insert_fields (&inst->value, aarch64_get_variant (inst),
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0, 2, FLD_SVE_M_14, FLD_size);
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@ -1872,8 +1877,9 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
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encoding. */
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break;
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case sme_misc:
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case sve_misc:
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/* sve_misc instructions have only a single variant. */
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/* These instructions have only a single variant. */
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break;
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case sve_movprfx:
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@ -1785,45 +1785,36 @@ aarch64_ext_sme_za_hv_tiles (const aarch64_operand *self,
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/* Deduce qualifier encoded in size and Q fields. */
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if (fld_size == 0)
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info->qualifier = AARCH64_OPND_QLF_S_B;
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{
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info->za_tile_vector.regno = 0;
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info->za_tile_vector.index.imm = fld_zan_imm;
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}
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else if (fld_size == 1)
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info->qualifier = AARCH64_OPND_QLF_S_H;
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{
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info->za_tile_vector.regno = fld_zan_imm >> 3;
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info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
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}
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else if (fld_size == 2)
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info->qualifier = AARCH64_OPND_QLF_S_S;
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{
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info->za_tile_vector.regno = fld_zan_imm >> 2;
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info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
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}
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else if (fld_size == 3 && fld_q == 0)
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info->qualifier = AARCH64_OPND_QLF_S_D;
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{
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info->za_tile_vector.regno = fld_zan_imm >> 1;
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info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
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}
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else if (fld_size == 3 && fld_q == 1)
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info->qualifier = AARCH64_OPND_QLF_S_Q;
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{
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info->za_tile_vector.regno = fld_zan_imm;
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info->za_tile_vector.index.imm = 0;
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}
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else
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return false;
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info->za_tile_vector.index.regno = fld_rv + 12;
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info->za_tile_vector.v = fld_v;
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switch (info->qualifier)
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{
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case AARCH64_OPND_QLF_S_B:
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info->za_tile_vector.regno = 0;
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info->za_tile_vector.index.imm = fld_zan_imm;
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break;
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case AARCH64_OPND_QLF_S_H:
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info->za_tile_vector.regno = fld_zan_imm >> 3;
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info->za_tile_vector.index.imm = fld_zan_imm & 0x07;
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break;
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case AARCH64_OPND_QLF_S_S:
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info->za_tile_vector.regno = fld_zan_imm >> 2;
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info->za_tile_vector.index.imm = fld_zan_imm & 0x03;
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break;
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case AARCH64_OPND_QLF_S_D:
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info->za_tile_vector.regno = fld_zan_imm >> 1;
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info->za_tile_vector.index.imm = fld_zan_imm & 0x01;
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break;
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case AARCH64_OPND_QLF_S_Q:
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info->za_tile_vector.regno = fld_zan_imm;
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info->za_tile_vector.index.imm = 0;
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break;
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default:
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return false;
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}
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return true;
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}
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@ -1914,26 +1905,14 @@ aarch64_ext_sme_pred_reg_with_index (const aarch64_operand *self,
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info->za_tile_vector.regno = fld_pn;
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info->za_tile_vector.index.regno = fld_rm + 12;
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if (fld_tszh == 0x1 && fld_tszl == 0x0)
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{
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info->qualifier = AARCH64_OPND_QLF_S_D;
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imm = fld_i1;
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}
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else if (fld_tszl == 0x4)
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{
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info->qualifier = AARCH64_OPND_QLF_S_S;
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imm = (fld_i1 << 1) | fld_tszh;
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}
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else if ((fld_tszl & 0x3) == 0x2)
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{
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info->qualifier = AARCH64_OPND_QLF_S_H;
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imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
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}
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else if (fld_tszl & 0x1)
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{
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info->qualifier = AARCH64_OPND_QLF_S_B;
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imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
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}
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if (fld_tszl & 0x1)
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imm = (fld_i1 << 3) | (fld_tszh << 2) | (fld_tszl >> 1);
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else if (fld_tszl & 0x2)
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imm = (fld_i1 << 2) | (fld_tszh << 1) | (fld_tszl >> 2);
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else if (fld_tszl & 0x4)
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imm = (fld_i1 << 1) | fld_tszh;
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else if (fld_tszh)
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imm = fld_i1;
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else
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return false;
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@ -2975,6 +2954,25 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
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variant = 0;
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switch (inst->opcode->iclass)
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{
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case sme_mov:
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variant = extract_fields (inst->value, 0, 2, FLD_SME_Q, FLD_SME_size_10);
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if (variant >= 4 && variant < 7)
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return false;
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if (variant == 7)
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variant = 4;
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break;
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case sme_psel:
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i = extract_fields (inst->value, 0, 2, FLD_SME_tszh, FLD_SME_tszl);
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if (i == 0)
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return false;
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while ((i & 1) == 0)
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{
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i >>= 1;
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variant += 1;
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}
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break;
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case sve_cpy:
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variant = extract_fields (inst->value, 0, 2, FLD_size, FLD_SVE_M_14);
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break;
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@ -3002,8 +3000,9 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
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variant = 3;
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break;
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case sme_misc:
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case sve_misc:
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/* sve_misc instructions have only a single variant. */
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/* These instructions have only a single variant. */
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break;
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case sve_movprfx:
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@ -2650,16 +2650,16 @@ static const aarch64_feature_set aarch64_feature_cssc =
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FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
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#define SME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
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FLAGS, 0, TIED, NULL }
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F_STRICT | FLAGS, 0, TIED, NULL }
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#define SME_F64F64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME_F64F64, OPS, QUALS, \
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FLAGS, 0, TIED, NULL }
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F_STRICT | FLAGS, 0, TIED, NULL }
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#define SME_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME_I16I64, OPS, QUALS, \
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FLAGS, 0, TIED, NULL }
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F_STRICT | FLAGS, 0, TIED, NULL }
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#define SME_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SME, OPS, QUALS, \
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FLAGS, CONSTRAINTS, TIED, NULL }
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F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
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#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
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{ NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
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FLAGS | F_STRICT, 0, TIED, NULL }
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@ -5238,10 +5238,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_S_PM_PM_B_B, 0, 0),
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SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SME_ZADA_D_PM_PM_H_H, 0, 0),
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SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
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SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
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@ -5275,7 +5275,7 @@ const struct aarch64_opcode aarch64_opcode_table[] =
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SME_INSNC ("revd", 0x52e8000, 0xffffe000, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_QMQ, 0, C_SCAN_MOVPRFX, 0),
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SME_INSNC ("sclamp", 0x4400c000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
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SME_INSNC ("uclamp", 0x4400c400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
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SME_INSN ("psel", 0x25204000, 0xff20c210, sme_misc, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
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SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
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/* SIMD Dot Product (optional in v8.2-A). */
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DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
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