Disallow 3-operand cmp[l][i] for ppc64
cmp[l][o] get an optional L field only when generating 32-bit code. dcbf, tlbie and tlbiel keep their optional L field, ditto for R field of tbegin. cmprb, tsr., wlcr[all] and mtsle all change to a compulsory L field. L field of dcbf and wclr is 2 bits. PR 20641 include/ * opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define. opcodes/ * ppc-opc.c (L): Make compulsory. (LOPT): New, optional form of L. (HTM_R): Define as LOPT. (L0, L1): Delete. (L32OPT): New, optional for 32-bit L. (L2OPT): New, 2-bit L for dcbf. (SVC_LEC): Update. (L2): Define. (insert_l0, extract_l0, insert_l1, extract_l2): Delete. (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT. <dcbf>: Use L2OPT. <tlbiel, tlbie>: Use LOPT. <wclr, wclrall>: Use L2. gas/ * config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32. * testsuite/gas/ppc/power8.s: Provide tbegin. operand. * testsuite/gas/ppc/power9.d: Update cmprb disassembly.
This commit is contained in:
Alan Modra
parent
b82317dd34
commit
a5721ba270
8 changed files with 59 additions and 77 deletions
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@ -1,3 +1,9 @@
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2016-09-29 Alan Modra <amodra@gmail.com>
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* config/tc-ppc.c (md_assemble): Handle PPC_OPERAND_OPTIONAL32.
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* testsuite/gas/ppc/power8.s: Provide tbegin. operand.
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* testsuite/gas/ppc/power9.d: Update cmprb disassembly.
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2016-09-26 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
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* config/tc-xtensa.c (xg_reverse_shift_count): Pass cnt_arg instead of
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@ -2695,7 +2695,8 @@ md_assemble (char *str)
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const struct powerpc_operand *operand;
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operand = &powerpc_operands[*opindex_ptr];
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if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
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if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
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{
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unsigned int opcount;
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unsigned int num_operands_expected;
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@ -2765,6 +2766,7 @@ md_assemble (char *str)
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/* If this is an optional operand, and we are skipping it, just
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insert a zero. */
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if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
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&& skip_optional)
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{
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long val = ppc_optional_operand_value (operand);
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@ -5,7 +5,7 @@ power8:
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tabortdc. 20,11,10
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tabortwci. 17,10,-13
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tabortdci. 29,3,-5
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tbegin.
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tbegin. 0
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tcheck 7
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tend. 0
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tend.
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@ -274,8 +274,8 @@ Disassembly of section \.text:
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.*: (f3 89 ef 6f|6f ef 89 f3) xvxsigsp vs60,vs61
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.*: (7c 06 39 c0|c0 39 06 7c) cmpeqb cr0,r6,r7
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.*: (7f 86 39 c0|c0 39 86 7f) cmpeqb cr7,r6,r7
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.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,r8,r9
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.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,r8,r9
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.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,0,r8,r9
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.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,0,r8,r9
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.*: (7c 28 49 80|80 49 28 7c) cmprb cr0,1,r8,r9
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.*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9
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.*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0
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@ -1,3 +1,7 @@
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2016-09-29 Alan Modra <amodra@gmail.com>
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* opcode/ppc.h (PPC_OPERAND_OPTIONAL32): Define.
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2016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
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* opcode/arc.h (insn_class_t): Add two new classes.
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@ -407,6 +407,10 @@ extern const unsigned int num_powerpc_operands;
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is omitted, then the value it should use for the operand is stored
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in the SHIFT field of the immediatly following operand field. */
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#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
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/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
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only optional when generating 32-bit code. */
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#define PPC_OPERAND_OPTIONAL32 (0x800000)
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/* The POWER and PowerPC assemblers use a few macros. We keep them
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with the operands table for simplicity. The macro table is an
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@ -1,3 +1,19 @@
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2016-09-29 Alan Modra <amodra@gmail.com>
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* ppc-opc.c (L): Make compulsory.
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(LOPT): New, optional form of L.
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(HTM_R): Define as LOPT.
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(L0, L1): Delete.
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(L32OPT): New, optional for 32-bit L.
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(L2OPT): New, 2-bit L for dcbf.
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(SVC_LEC): Update.
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(L2): Define.
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(insert_l0, extract_l0, insert_l1, extract_l2): Delete.
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(powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
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<dcbf>: Use L2OPT.
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<tlbiel, tlbie>: Use LOPT.
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<wclr, wclrall>: Use L2.
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2016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
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* Makefile.in: Regenerate.
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@ -62,10 +62,6 @@ static unsigned long insert_dxdn (unsigned long, long, ppc_cpu_t, const char **)
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static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
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static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
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static long extract_fxm (unsigned long, ppc_cpu_t, int *);
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static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
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static long extract_l0 (unsigned long, ppc_cpu_t, int *);
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static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
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static long extract_l1 (unsigned long, ppc_cpu_t, int *);
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static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
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static long extract_li20 (unsigned long, ppc_cpu_t, int *);
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static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
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@ -429,20 +425,24 @@ const struct powerpc_operand powerpc_operands[] =
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/* The L field in a D or X form instruction. */
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#define L IMM20 + 1
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{ 0x1, 21, NULL, NULL, 0 },
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/* The optional L field in tlbie and tlbiel instructions. */
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#define LOPT L + 1
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/* The R field in a HTM X form instruction. */
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#define HTM_R L
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#define HTM_R LOPT
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{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The L field in an X form instruction which must be zero. */
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#define L0 L + 1
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{ 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
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/* The optional (for 32-bit) L field in cmp[l][i] instructions. */
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#define L32OPT LOPT + 1
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{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
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/* The L field in an X form instruction which must be one. */
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#define L1 L0 + 1
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{ 0x1, 21, insert_l1, extract_l1, 0 },
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/* The L field in dcbf instruction. */
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#define L2OPT L32OPT + 1
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{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The LEV field in a POWER SVC form instruction. */
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#define SVC_LEV L1 + 1
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#define SVC_LEV L2OPT + 1
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{ 0x7f, 5, NULL, NULL, 0 },
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/* The LEV field in an SC form instruction. */
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@ -688,6 +688,8 @@ const struct powerpc_operand powerpc_operands[] =
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#define STRM SR + 1
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/* The T field in a tlbilx form instruction. */
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#define T STRM
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/* The L field in wclr instructions. */
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#define L2 STRM
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{ 0x3, 21, NULL, NULL, 0 },
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/* The ESYNC field in an X (sync) form instruction. */
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@ -1483,58 +1485,6 @@ extract_fxm (unsigned long insn,
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return mask;
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}
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/* The L field in an X form instruction which must have the value zero. */
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static unsigned long
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insert_l0 (unsigned long insn,
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long value,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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const char **errmsg)
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{
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if (value != 0)
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*errmsg = _("invalid operand constant");
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return insn & ~(0x1 << 21);
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}
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static long
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extract_l0 (unsigned long insn,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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int *invalid)
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{
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long value;
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value = (insn >> 21) & 0x1;
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if (value != 0)
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*invalid = 1;
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return value;
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}
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/* The L field in an X form instruction which must have the value one. */
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static unsigned long
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insert_l1 (unsigned long insn,
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long value,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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const char **errmsg)
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{
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if (value != 1)
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*errmsg = _("invalid operand constant");
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return insn | (0x1 << 21);
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}
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static long
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extract_l1 (unsigned long insn,
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ppc_cpu_t dialect ATTRIBUTE_UNUSED,
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int *invalid)
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{
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long value;
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value = (insn >> 21) & 0x1;
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if (value != 1)
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*invalid = 1;
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return value;
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}
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static unsigned long
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insert_li20 (unsigned long insn,
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long value,
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@ -3890,12 +3840,12 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
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{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
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{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
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{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
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{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
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{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
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{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
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{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
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{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
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{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
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{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
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@ -4713,7 +4663,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
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{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
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{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
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{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
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{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
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{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
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@ -4821,7 +4771,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
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{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
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{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
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{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
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{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
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{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
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@ -4907,7 +4857,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
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{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
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{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
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{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
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{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
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@ -5149,7 +5099,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
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{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
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{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
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{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
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{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
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@ -5183,7 +5133,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
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{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
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{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
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{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
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{"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
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{"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
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@ -6234,8 +6184,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
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{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
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{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
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{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
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{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
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{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
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{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
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Add table
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