sim-main.h: Re-arange r5900 registers so that they have their own
little struct. interp.c: Update. Also add floating point Max/Min functions. mips.igen: Remove r5900 tag from any floating point instructions. r5900.igen: Rewrite. Implement *all* floating point insns (except ld/st). r5400.igen: Tag mdmx functions as being mdmx specific.
This commit is contained in:
Andrew Cagney
parent
0325f2dc89
commit
a48e8c8d21
7 changed files with 628 additions and 261 deletions
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@ -12,14 +12,14 @@
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// IGEN config - mips16
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:option:16::insn-bit-size:16
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:option:16::hi-bit-nr:15
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// :option:16::insn-bit-size:16
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// :option:16::hi-bit-nr:15
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:option:16::insn-specifying-widths:true
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:option:16::gen-delayed-branch:false
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// IGEN config - mips32/64..
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:option:32::insn-bit-size:32
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:option:32::hi-bit-nr:31
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// :option:32::insn-bit-size:32
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// :option:32::hi-bit-nr:31
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:option:32::insn-specifying-widths:true
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:option:32::gen-delayed-branch:false
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@ -35,17 +35,17 @@
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:model:::mipsIV:mipsIV:
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:model:::mips16:mips16:
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// start-sanitize-r5900
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:model:::r5900:r5900:
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:model:::r5900:mips5900:
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// end-sanitize-r5900
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:model:::r3900:r3900:
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:model:::r3900:mips3900:
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// start-sanitize-tx19
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:model:::tx19:tx19:
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// end-sanitize-tx19
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// start-sanitize-vr5400
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:model:::vr5400:vr5400:
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:model:::vr5400:mips5400:
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:model:::mdmx:mdmx:
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// end-sanitize-vr5400
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:model:::vr5000:vr5000:
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:model:::vr5000:mips5000:
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@ -1258,6 +1258,25 @@
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}
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:function:::void:do_load_byte:address_word gpr_base, int rt, signed16 offset
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{
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address_word vaddr = offset + gpr_base;
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address_word paddr;
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int uncached;
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if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
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{
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unsigned64 memval = 0;
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address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
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unsigned int reverse = (ReverseEndian ? mask : 0);
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unsigned int bigend = (BigEndianCPU ? mask : 0);
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unsigned int byte;
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paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverse));
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LoadMemory (&memval, NULL, uncached, AccessLength_BYTE, paddr, vaddr, isDATA, isREAL);
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byte = ((vaddr & mask) ^ bigend);
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GPR[rt] = EXTEND8 ((memval >> (8 * byte)));
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}
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}
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100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
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"lb r<RT>, <OFFSET>(r<BASE>)"
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*mipsI,mipsII,mipsIII,mipsIV:
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@ -1273,6 +1292,8 @@
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*tx19:
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// end-sanitize-tx19
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{
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do_load_byte (SD_, GPR[BASE], RT, OFFSET);
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#if 0
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unsigned32 instruction = instruction_0;
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signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
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int destreg = ((instruction >> 16) & 0x0000001F);
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@ -1298,6 +1319,7 @@
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}
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}
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}
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#endif
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}
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@ -3430,9 +3452,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -3452,16 +3471,13 @@
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010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD
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010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
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"add.%s<FMT> f<FD>, f<FS>, f<FT>"
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*mipsI,mipsII,mipsIII,mipsIV:
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*vr5000:
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -3494,14 +3510,22 @@
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*r5900:
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// end-sanitize-r5900
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{
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TRACE_BRANCH_INPUT (PREVCOC1());
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if (PREVCOC1() == TF)
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{
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DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
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address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
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TRACE_BRANCH_RESULT (dest);
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DELAY_SLOT (dest);
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}
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else if (ND)
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{
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TRACE_BRANCH_RESULT (0);
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NULLIFY_NEXT_INSTRUCTION ();
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}
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else
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{
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TRACE_BRANCH_RESULT (NIA);
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}
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}
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010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
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@ -3584,9 +3608,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -3841,9 +3862,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -4133,16 +4151,13 @@
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//
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// FIXME: Not correct for mips*
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//
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010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32::MADD.D
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010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
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"madd.d f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*vr5000:
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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unsigned32 instruction = instruction_0;
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int destreg = ((instruction >> 6) & 0x0000001F);
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@ -4155,16 +4170,13 @@
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}
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010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32::MADD.S
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010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
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"madd.s f<FD>, f<FR>, f<FS>, f<FT>"
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*mipsIV:
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*vr5000:
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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{
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unsigned32 instruction = instruction_0;
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int destreg = ((instruction >> 6) & 0x0000001F);
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@ -4202,9 +4214,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -4225,9 +4234,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -4387,9 +4393,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -4416,9 +4419,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -4739,9 +4739,6 @@
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// start-sanitize-vr5400
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*vr5400:
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// end-sanitize-vr5400
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// start-sanitize-r5900
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*r5900:
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// end-sanitize-r5900
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*r3900:
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// start-sanitize-tx19
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*tx19:
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@ -5099,10 +5096,10 @@
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// end-sanitize-r5900
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:include:::m16.igen
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:include:16::m16.igen
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// start-sanitize-vr5400
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:include::vr5400:vr5400.igen
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:include:::mdmx.igen
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:include:64,f::mdmx.igen
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// end-sanitize-vr5400
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// start-sanitize-r5900
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:include::r5900:r5900.igen
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@ -5206,4 +5203,4 @@
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// }
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// }
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// start-sanitize-cygnus-never
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// end-sanitize-cygnus-never
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