x86: correct MPX insn w/o base or index encoding in 16-bit mode
Since 16-bit addressing isn't allowed, Disp32 needs to be forced; Disp16 fails to match the templates. The SDM leaves open whether BNDC[LNU] with a GPR operand require an operand size override; this aspect is therefore left untouched here.
This commit is contained in:
Jan Beulich
parent
a04973848d
commit
a23b33b3d1
7 changed files with 201 additions and 4 deletions
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@ -1,3 +1,11 @@
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (i386_addressing_mode): For 32-bit
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addressing for MPX insns without base/index.
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* testsuite/gas/i386/mpx-16bit.s,
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* testsuite/gas/i386/mpx-16bit.d: New.
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* testsuite/gas/i386/i386.exp: Run new test.
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/adx.s, testsuite/gas/i386/cet.s,
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@ -10359,6 +10359,21 @@ i386_addressing_mode (void)
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if (i.prefix[ADDR_PREFIX])
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addr_mode = flag_code == CODE_32BIT ? CODE_16BIT : CODE_32BIT;
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else if (flag_code == CODE_16BIT
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&& current_templates->start->cpu_flags.bitfield.cpumpx
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/* Avoid replacing the "16-bit addressing not allowed" diagnostic
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from md_assemble() by "is not a valid base/index expression"
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when there is a base and/or index. */
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&& !i.types[this_operand].bitfield.baseindex)
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{
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/* MPX insn memory operands with neither base nor index must be forced
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to use 32-bit addressing in 16-bit mode. */
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addr_mode = CODE_32BIT;
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i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
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++i.prefixes;
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gas_assert (!i.types[this_operand].bitfield.disp16);
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gas_assert (!i.types[this_operand].bitfield.disp32);
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}
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else
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{
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addr_mode = flag_code;
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@ -329,6 +329,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_list_test "mpx-inval-1" "-al"
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run_list_test "mpx-inval-2" "-al"
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run_dump_test "mpx-add-bnd-prefix"
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run_dump_test "mpx-16bit"
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run_list_test "bnd" "-al"
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run_dump_test "sha"
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run_dump_test "clflushopt"
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145
gas/testsuite/gas/i386/mpx-16bit.d
Normal file
145
gas/testsuite/gas/i386/mpx-16bit.d
Normal file
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@ -0,0 +1,145 @@
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#as: -I${srcdir}/$subdir
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#objdump: -drw -Mi8086
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#name: i386 MPX (16-bit)
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.*: +file format .*
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Disassembly of section .text:
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0+ <start>:
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[ ]*[a-f0-9]+: 67 f3 0f 1b 08 bndmk \(%eax\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 0d 99 03 00 00 addr32 bndmk 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 4a 03 bndmk 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 0c 08 bndmk \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 0c 0d 00 00 00 00 bndmk 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 4c 01 03 bndmk 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 08 bndmov \(%eax\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 0d 99 03 00 00 addr32 bndmov 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 52 03 bndmov 0x3\(%edx\),%bnd2
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[ ]*[a-f0-9]+: 67 66 0f 1a 14 10 bndmov \(%eax,%edx,1\),%bnd2
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[ ]*[a-f0-9]+: 67 66 0f 1a 14 05 00 00 00 00 bndmov 0x0\(,%eax,1\),%bnd2
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[ ]*[a-f0-9]+: 67 66 0f 1a 4c 01 03 bndmov 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 66 0f 1a c2 bndmov %bnd2,%bnd0
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[ ]*[a-f0-9]+: 67 66 0f 1b 08 bndmov %bnd1,\(%eax\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 0d 99 03 00 00 addr32 bndmov %bnd1,0x399
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[ ]*[a-f0-9]+: 67 66 0f 1b 52 03 bndmov %bnd2,0x3\(%edx\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 14 10 bndmov %bnd2,\(%eax,%edx,1\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 14 05 00 00 00 00 bndmov %bnd2,0x0\(,%eax,1\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 4c 01 03 bndmov %bnd1,0x3\(%ecx,%eax,1\)
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[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
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[ ]*[a-f0-9]+: 67 f3 0f 1a 09 bndcl \(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 0d 99 03 00 00 addr32 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 4a 03 bndcl 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 0c 0d 00 00 00 00 bndcl 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 4c 01 03 bndcl 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 09 bndcu \(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 0d 99 03 00 00 addr32 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 4a 03 bndcu 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 0c 0d 00 00 00 00 bndcu 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 4c 01 03 bndcu 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 09 bndcn \(%ecx\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 0d 99 03 00 00 addr32 bndcn 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 4a 03 bndcn 0x3\(%edx\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 0c 0d 00 00 00 00 bndcn 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 4c 01 03 bndcn 0x3\(%ecx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 0f 1b 44 18 03 bndstx %bnd0,0x3\(%eax,%ebx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 54 13 03 bndstx %bnd2,0x3\(%ebx,%edx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 14 15 03 00 00 00 bndstx %bnd2,0x3\(,%edx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 9a 99 03 00 00 bndstx %bnd3,0x399\(%edx\)
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[ ]*[a-f0-9]+: 67 0f 1b 93 34 12 00 00 bndstx %bnd2,0x1234\(%ebx\)
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[ ]*[a-f0-9]+: 67 0f 1b 53 03 bndstx %bnd2,0x3\(%ebx\)
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[ ]*[a-f0-9]+: 67 0f 1b 0a bndstx %bnd1,\(%edx\)
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[ ]*[a-f0-9]+: 67 0f 1a 44 18 03 bndldx 0x3\(%eax,%ebx,1\),%bnd0
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[ ]*[a-f0-9]+: 67 0f 1a 54 13 03 bndldx 0x3\(%ebx,%edx,1\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 14 15 03 00 00 00 bndldx 0x3\(,%edx,1\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
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[ ]*[a-f0-9]+: 67 0f 1a 93 34 12 00 00 bndldx 0x1234\(%ebx\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 53 03 bndldx 0x3\(%ebx\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 0a bndldx \(%edx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 91 01 bnd call [a-f0-9]+ <foo>
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[ ]*[a-f0-9]+: 67 f2 ff 10 bnd call \*\(%eax\)
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[ ]*[a-f0-9]+: f2 0f 84 88 01 bnd je [a-f0-9]+ <foo>
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[ ]*[a-f0-9]+: f2 e9 84 01 bnd jmp [a-f0-9]+ <foo>
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[ ]*[a-f0-9]+: 67 f2 ff 21 bnd jmp \*\(%ecx\)
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[ ]*[a-f0-9]+: f2 c3 bnd ret *
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[ ]*[a-f0-9]+: 67 f3 0f 1b 08 bndmk \(%eax\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 0d 99 03 00 00 addr32 bndmk 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 49 03 bndmk 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 0c 08 bndmk \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 0c 0d 00 00 00 00 bndmk 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1b 4c 02 03 bndmk 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 08 bndmov \(%eax\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 0d 99 03 00 00 addr32 bndmov 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 49 03 bndmov 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 0c 08 bndmov \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 0c 0d 00 00 00 00 bndmov 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 66 0f 1a 4c 02 03 bndmov 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 66 0f 1a c1 bndmov %bnd1,%bnd0
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[ ]*[a-f0-9]+: 67 66 0f 1b 08 bndmov %bnd1,\(%eax\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 0d 99 03 00 00 addr32 bndmov %bnd1,0x399
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[ ]*[a-f0-9]+: 67 66 0f 1b 49 03 bndmov %bnd1,0x3\(%ecx\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 0c 08 bndmov %bnd1,\(%eax,%ecx,1\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 0c 0d 00 00 00 00 bndmov %bnd1,0x0\(,%ecx,1\)
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[ ]*[a-f0-9]+: 67 66 0f 1b 4c 02 03 bndmov %bnd1,0x3\(%edx,%eax,1\)
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[ ]*[a-f0-9]+: 66 0f 1a c8 bndmov %bnd0,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 08 bndcl \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1a c9 bndcl %ecx,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 0d 99 03 00 00 addr32 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 49 03 bndcl 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 0c 08 bndcl \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 0c 0d 00 00 00 00 bndcl 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f3 0f 1a 4c 02 03 bndcl 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 08 bndcu \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a c9 bndcu %ecx,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 0d 99 03 00 00 addr32 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 49 03 bndcu 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 0c 08 bndcu \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 0c 0d 00 00 00 00 bndcu 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1a 4c 02 03 bndcu 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 08 bndcn \(%eax\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b c9 bndcn %ecx,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 0d 99 03 00 00 addr32 bndcn 0x399,%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 49 03 bndcn 0x3\(%ecx\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 0c 08 bndcn \(%eax,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 0c 0d 00 00 00 00 bndcn 0x0\(,%ecx,1\),%bnd1
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[ ]*[a-f0-9]+: 67 f2 0f 1b 4c 02 03 bndcn 0x3\(%edx,%eax,1\),%bnd1
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[ ]*[a-f0-9]+: 67 0f 1b 44 18 03 bndstx %bnd0,0x3\(%eax,%ebx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 54 13 03 bndstx %bnd2,0x3\(%ebx,%edx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 14 0d 00 00 00 00 bndstx %bnd2,0x0\(,%ecx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 9a 99 03 00 00 bndstx %bnd3,0x399\(%edx\)
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[ ]*[a-f0-9]+: 67 0f 1b 14 1d 03 00 00 00 bndstx %bnd2,0x3\(,%ebx,1\)
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[ ]*[a-f0-9]+: 67 0f 1b 0a bndstx %bnd1,\(%edx\)
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[ ]*[a-f0-9]+: 67 0f 1a 44 18 03 bndldx 0x3\(%eax,%ebx,1\),%bnd0
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[ ]*[a-f0-9]+: 67 0f 1a 54 13 03 bndldx 0x3\(%ebx,%edx,1\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 14 0d 00 00 00 00 bndldx 0x0\(,%ecx,1\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 9a 99 03 00 00 bndldx 0x399\(%edx\),%bnd3
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[ ]*[a-f0-9]+: 67 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%ebx,1\),%bnd2
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[ ]*[a-f0-9]+: 67 0f 1a 0a bndldx \(%edx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 10 00 bnd call [a-f0-9]+ <foo>
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[ ]*[a-f0-9]+: 66 f2 ff d0 bnd calll? \*%eax
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[ ]*[a-f0-9]+: f2 74 09 bnd je [a-f0-9]+ <foo>
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[ ]*[a-f0-9]+: f2 eb 06 bnd jmp [a-f0-9]+ <foo>
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[ ]*[a-f0-9]+: 66 f2 ff e1 bnd jmpl? \*%ecx
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[ ]*[a-f0-9]+: f2 c3 bnd ret *
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[a-f0-9]+ <foo>:
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[ ]*[a-f0-9]+: f2 c3 bnd ret *
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[a-f0-9]+ <bad>:
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#...
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[a-f0-9]+ <bad16>:
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[ ]*[a-f0-9]+: f3 0f 1b 00 bndmk \(bad\),%bnd0
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[ ]*[a-f0-9]+: 66 0f 1a 00 bndmov \(bad\),%bnd0
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[ ]*[a-f0-9]+: f3 0f 1a 00 bndcl \(bad\),%bnd0
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[ ]*[a-f0-9]+: f2 0f 1b 00 bndcn \(bad\),%bnd0
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[ ]*[a-f0-9]+: f2 0f 1a 00 bndcu \(bad\),%bnd0
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[ ]*[a-f0-9]+: 0f 1b 00 bndstx %bnd0,\(bad\)
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[ ]*[a-f0-9]+: 0f 1a 00 bndldx \(bad\),%bnd0
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#pass
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13
gas/testsuite/gas/i386/mpx-16bit.s
Normal file
13
gas/testsuite/gas/i386/mpx-16bit.s
Normal file
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@ -0,0 +1,13 @@
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.code16
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.include "mpx.s"
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.att_syntax prefix
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.code32
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bad16: # 16-bit addressing mode seen by the disassembler
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bndmk (%eax), %bnd0
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bndmov (%eax), %bnd0
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bndcl (%eax), %bnd0
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bndcn (%eax), %bnd0
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bndcu (%eax), %bnd0
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bndstx %bnd0, (%eax)
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bndldx (%eax), %bnd0
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@ -1,3 +1,9 @@
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (OP_E_memory): Exclude recording of used address
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prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
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addressed memory operands for MPX insns.
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2020-03-06 Jan Beulich <jbeulich@suse.com>
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* i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
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@ -14272,10 +14272,11 @@ OP_E_memory (int bytemode, int sizeflag)
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}
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if ((havebase || haveindex || needindex || needaddr32 || riprel)
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&& (bytemode != v_bnd_mode)
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&& (bytemode != v_bndmk_mode)
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&& (bytemode != bnd_mode)
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&& (bytemode != bnd_swap_mode))
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&& (address_mode != mode_64bit
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|| ((bytemode != v_bnd_mode)
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&& (bytemode != v_bndmk_mode)
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&& (bytemode != bnd_mode)
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&& (bytemode != bnd_swap_mode))))
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used_prefixes |= PREFIX_ADDR;
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if (havedisp || (intel_syntax && riprel))
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@ -14356,6 +14357,14 @@ OP_E_memory (int bytemode, int sizeflag)
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}
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}
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}
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else if (bytemode == v_bnd_mode
|
||||
|| bytemode == v_bndmk_mode
|
||||
|| bytemode == bnd_mode
|
||||
|| bytemode == bnd_swap_mode)
|
||||
{
|
||||
oappend ("(bad)");
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* 16 bit address mode */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue