FreeChainXenon/binutils-gdb
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[cpu]

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* m32c.cpu (lde, ste): Add dsp[a0] and [a1a] addressing.
(indexb, indexbd, indexbs, indexw, indexwd, indexws, indexl,
indexld, indexls): .w variants have `1' bit.
(rot32.b): QI, not SI.
(rot32.w): HI, not SI.
(xchg16): HI for .w variant.

[opcodes]
* m32c-asm.c: Regenerate.
* m32c-desc.c: Regenerate.
* m32c-desc.h: Regenerate.
* m32c-dis.c: Regenerate.
* m32c-ibld.c: Regenerate.
* m32c-opc.c: Regenerate.
* m32c-opc.h: Regenerate.
This commit is contained in:
DJ Delorie 2005-10-22 00:03:13 +00:00
parent a0ffed4b33
commit a1a280bb84
10 changed files with 1614 additions and 716 deletions
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3
opcodes/m32c-asm.c
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@ -879,6 +879,9 @@ m32c_cgen_parse_operand (CGEN_CPU_DESC cd,
case M32C_OPERAND_A1 :
errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_a1, & junk);
break;
case M32C_OPERAND_A1A0 :
errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_SI, & junk);
break;
case M32C_OPERAND_AN16_PUSH_S :
errmsg = cgen_parse_keyword (cd, strp, & m32c_cgen_opval_h_ar_HI, & fields->f_4_1);
break;