Add support for RX V2 Instruction Set
binutils * readelf.c(get_machine_flags): Add v2 flag. gas * config/rx-defs.h(rx_cpu_type): Add RXV2 type. * config/tc-rx.c(cpu_type_list): New type lookup table. (md_parse_option): Use lookup table for choose cpu. (md_show_usage): Add rxv2 for mcpu option. * doc/c-rx.texi: Likewise. * config/rx-parse.y: Add v2 instructions and ACC register. (rx_check_v2): check v2 type. include/elf * rx.h(E_FLAG_RX_V2): New RXv2 type. include/opcode * rx.h: Add new instructions. opcoes * rx-deocde.opc(rx_decode_opcode): Add new instructions pattern. * rx-dis.c(register_name): Add new register. gas/testsuite * gas/rx/emaca.d: New. * gas/rx/emaca.sm: New. * gas/rx/emsba.d: New. * gas/rx/emsba.sm: New. * gas/rx/emula.d: New. * gas/rx/emula.sm: New. * gas/rx/fadd.d: Add new pattern. * gas/rx/fadd.sm: Add new pattern. * gas/rx/fmul.d: Add new pattern. * gas/rx/fmul.sm: Add new pattern. * gas/rx/fsqrt.d: New. * gas/rx/fsqrt.sm: New. * gas/rx/fsub.d: Add new pattern. * gas/rx/fsub.sm: Add new pattern. * gas/rx/ftou.d: New. * gas/rx/ftou.sm: New. * gas/rx/maclh.d: New. * gas/rx/maclh.sm: New. * gas/rx/maclo.d: Add new pattern. * gas/rx/maclo.sm: Add new pattern. * gas/rx/macros.inc: Add new register. * gas/rx/movco.d: New. * gas/rx/movco.sm: New. * gas/rx/movli.d: New. * gas/rx/movli.sm: New. * gas/rx/msbhi.d: New. * gas/rx/msbhi.sm: New. * gas/rx/msblh.d: New. * gas/rx/msblh.sm: New. * gas/rx/msblo.d: New. * gas/rx/msblo.sm: New. * gas/rx/mullh.d: New. * gas/rx/mullh.sm: New. * gas/rx/mvfacgu.d: New. * gas/rx/mvfacgu.sm: New. * gas/rx/mvfachi.d: Add new pattern. * gas/rx/mvfachi.sm: Add new pattern. * gas/rx/mvfaclo.d: Add new pattern. * gas/rx/mvfaclo.sm: Add new pattern. * gas/rx/mvfacmi.d: Add new pattern. * gas/rx/mvfacmi.sm: Add new pattern. * gas/rx/mvfc.d: Add new pattern. * gas/rx/mvtacgu.d: New. * gas/rx/mvtacgu.sm: New. * gas/rx/mvtc.d: Add new pattern. * gas/rx/popc.d: Add new pattern. * gas/rx/pushc.d: Add new pattern. * gas/rx/racl.d: New. * gas/rx/racl.sm: New. * gas/rx/racw.d: Add new pattern. * gas/rx/racw.sm: Add new pattern. * gas/rx/rdacl.d: New. * gas/rx/rdacl.sm: New. * gas/rx/rdacw.d: New. * gas/rx/rdacw.sm: New. * gas/rx/rx.exp: Add option. * gas/rx/stnz.d: Add new pattern. * gas/rx/stnz.sm: Add new pattern. * gas/rx/stz.d: Add new pattern. * gas/rx/stz.sm: Add new pattern. * gas/rx/utof.d: New. * gas/rx/utof.sm: New.
This commit is contained in:
Yoshinori Sato
Nick Clifton
parent
ef603459d5
commit
a117b0a51c
92 changed files with 3802 additions and 1370 deletions
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@ -1,3 +1,7 @@
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2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
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* readelf.c (get_machine_flags): Add support for RX v2 flag.
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2015-12-14 Jan Beulich <jbeulich@suse.com>
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* nm.c: Include coff/external.h, coff/internal.h, and
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@ -3376,6 +3376,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
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if (e_flags & E_FLAG_RX_SINSNS_SET)
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strcat (buf, e_flags & E_FLAG_RX_SINSNS_YES
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? ", uses String instructions" : ", bans String instructions");
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if (e_flags & E_FLAG_RX_V2)
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strcat (buf, ", V2");
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break;
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case EM_S390:
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@ -9,6 +9,16 @@
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* config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
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qualifier from per-type base and offet.
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2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
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* config/rx-defs.h(rx_cpu_type): Add RXV2 type.
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* config/tc-rx.c(cpu_type_list): New type lookup table.
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(md_parse_option): Use lookup table for choose cpu.
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(md_show_usage): Add rxv2 for mcpu option.
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* doc/c-rx.texi: Likewise.
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* config/rx-parse.y: Add v2 instructions and ACC register.
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(rx_check_v2): check v2 type.
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2015-12-14 Jan Beulich <jbeulich@suse.com>
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* dw2gencfi.c (dot_cfi_label): Free "name".
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@ -38,7 +38,8 @@ enum rx_cpu_types
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RX600,
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RX610,
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RX200,
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RX100
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RX100,
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RXV2
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};
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extern int rx_pid_register;
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@ -101,7 +101,7 @@ static int sizemap[] = { BSIZE, WSIZE, LSIZE, WSIZE };
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else rx_linkrelax_dsp (pos); \
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F (displacement (v, msz), pos, 2)
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#define id24(a,b2,b3) B3 (0xfb+a, b2, b3)
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#define id24(a,b2,b3) B3 (0xfb + a, b2, b3)
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static void rx_check_float_support (void);
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static int rx_intop (expressionS, int, int);
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@ -115,6 +115,7 @@ static int immediate (expressionS, int, int, int);
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static int displacement (expressionS, int);
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static void rtsd_immediate (expressionS);
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static void rx_range (expressionS, int, int);
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static void rx_check_v2 (void);
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static int need_flag = 0;
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static int rx_in_brackets = 0;
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@ -136,11 +137,11 @@ static int sub_op2;
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expressionS exp;
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}
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%type <regno> REG FLAG CREG BCND BMCND SCCND
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%type <regno> REG FLAG CREG BCND BMCND SCCND ACC
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%type <regno> flag bwl bw memex
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%type <exp> EXPR disp
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%token REG FLAG CREG
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%token REG FLAG CREG ACC
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%token EXPR UNKNOWN_OPCODE IS_OPCODE
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@ -150,19 +151,22 @@ static int sub_op2;
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%token BCLR BCND BMCND BNOT BRA BRK BSET BSR BTST
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%token CLRPSW CMP
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%token DBT DIV DIVU
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%token EDIV EDIVU EMUL EMULU
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%token FADD FCMP FDIV FMUL FREIT FSUB FTOI
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%token EDIV EDIVU EMACA EMSBA EMUL EMULA EMULU
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%token FADD FCMP FDIV FMUL FREIT FSUB FSQRT FTOI FTOU
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%token INT ITOF
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%token JMP JSR
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%token MACHI MACLO MAX MIN MOV MOVU MUL MULHI MULLO MULU MVFACHI MVFACMI MVFACLO
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%token MVFC MVTACHI MVTACLO MVTC MVTIPL
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%token MACHI MACLH MACLO MAX MIN MOV MOVCO MOVLI MOVU MSBHI MSBLH MSBLO MUL
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%token MULHI MULLH MULLO MULU MVFACHI MVFACGU MVFACMI MVFACLO MVFC MVTACGU
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%token MVTACHI MVTACLO MVTC MVTIPL
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%token NEG NOP NOT
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%token OR
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%token POP POPC POPM PUSH PUSHA PUSHC PUSHM
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%token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD
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%token RACL RACW RDACL RDACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND
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%token RTE RTFI RTS RTSD
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%token SAT SATR SBB SCCND SCMPU SETPSW SHAR SHLL SHLR SMOVB SMOVF
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%token SMOVU SSTR STNZ STOP STZ SUB SUNTIL SWHILE
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%token TST
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%token UTOF
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%token WAIT
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%token XCHG XOR
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@ -466,7 +470,9 @@ statement :
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/* ---------------------------------------------------------------------- */
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| PUSHC CREG
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{ if ($2 < 16)
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{ if ($2 == 13)
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{ rx_check_v2 (); }
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if ($2 < 16)
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{ B2 (0x7e, 0xc0); F ($2, 12, 4); }
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else
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as_bad (_("PUSHC can only push the first 16 control registers")); }
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@ -474,7 +480,9 @@ statement :
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/* ---------------------------------------------------------------------- */
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| POPC CREG
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{ if ($2 < 16)
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{ if ($2 == 13)
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{ rx_check_v2 (); }
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if ($2 < 16)
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{ B2 (0x7e, 0xe0); F ($2, 12, 4); }
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else
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as_bad (_("POPC can only pop the first 16 control registers")); }
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@ -615,8 +623,8 @@ statement :
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| TST { sub_op = 12; } op_dp20_rim
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| XOR { sub_op = 13; } op_dp20_rim
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| NOT { sub_op = 14; sub_op2 = 0; } op_dp20_rr
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| STZ { sub_op = 14; } op_dp20_i
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| STNZ { sub_op = 15; } op_dp20_i
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| STZ { sub_op = 14; sub_op2 = 0; } op_dp20_ri
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| STNZ { sub_op = 15; sub_op2 = 1; } op_dp20_ri
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/* ---------------------------------------------------------------------- */
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@ -624,6 +632,7 @@ statement :
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| EMULU { sub_op = 7; } op_xchg
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| XCHG { sub_op = 16; } op_xchg
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| ITOF { sub_op = 17; } op_xchg
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| UTOF { sub_op = 21; } op_xchg
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/* ---------------------------------------------------------------------- */
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@ -647,14 +656,19 @@ statement :
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/* ---------------------------------------------------------------------- */
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| FSUB { sub_op = 0; } float2_op
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| FSUB { sub_op = 0; } float3_op
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| FCMP { sub_op = 1; } float2_op
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| FADD { sub_op = 2; } float2_op
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| FMUL { sub_op = 3; } float2_op
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| FADD { sub_op = 2; } float3_op
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| FMUL { sub_op = 3; } float3_op
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| FDIV { sub_op = 4; } float2_op
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| FSQRT { sub_op = 8; } float2_op_ni
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| FTOI { sub_op = 5; } float2_op_ni
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| FTOU { sub_op = 9; } float2_op_ni
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| ROUND { sub_op = 6; } float2_op_ni
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/* ---------------------------------------------------------------------- */
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/* ---------------------------------------------------------------------- */
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| SCCND DOT_L REG
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@ -678,27 +692,41 @@ statement :
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| MULHI REG ',' REG
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{ id24 (2, 0x00, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
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| MULHI REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x00, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MULLO REG ',' REG
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{ id24 (2, 0x01, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
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| MULLO REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x01, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MACHI REG ',' REG
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{ id24 (2, 0x04, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
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| MACHI REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x04, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MACLO REG ',' REG
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{ id24 (2, 0x05, 0x00); F ($2, 16, 4); F ($4, 20, 4); }
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| MACLO REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x05, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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/* ---------------------------------------------------------------------- */
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/* We don't have syntax for these yet. */
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| MVTACHI REG
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{ id24 (2, 0x17, 0x00); F ($2, 20, 4); }
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| MVTACHI REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x17, 0x00); F ($2, 20, 4); F ($4, 16, 1); }
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| MVTACLO REG
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{ id24 (2, 0x17, 0x10); F ($2, 20, 4); }
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| MVTACLO REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x17, 0x10); F ($2, 20, 4); F ($4, 16, 1); }
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| MVFACHI REG
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{ id24 (2, 0x1f, 0x00); F ($2, 20, 4); }
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| MVFACHI { sub_op = 0; } mvfa_op
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| MVFACMI REG
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{ id24 (2, 0x1f, 0x20); F ($2, 20, 4); }
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| MVFACMI { sub_op = 2; } mvfa_op
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| MVFACLO REG
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{ id24 (2, 0x1f, 0x10); F ($2, 20, 4); }
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| MVFACLO { sub_op = 1; } mvfa_op
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| RACW '#' EXPR
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{ id24 (2, 0x18, 0x00);
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if (rx_uintop ($3, 4) && $3.X_add_number == 1)
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@ -707,6 +735,14 @@ statement :
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F (1, 19, 1);
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else
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as_bad (_("RACW expects #1 or #2"));}
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| RACW '#' EXPR ',' ACC
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{ rx_check_v2 (); id24 (2, 0x18, 0x00); F ($5, 16, 1);
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if (rx_uintop ($3, 4) && $3.X_add_number == 1)
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;
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else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
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F (1, 19, 1);
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else
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as_bad (_("RACW expects #1 or #2"));}
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/* ---------------------------------------------------------------------- */
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@ -739,13 +775,17 @@ statement :
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/* ---------------------------------------------------------------------- */
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| MVTC REG ',' CREG
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{ id24 (2, 0x68, 0x00); F ($4 % 16, 20, 4); F ($4 / 16, 15, 1);
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{ if ($4 == 13)
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rx_check_v2 ();
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id24 (2, 0x68, 0x00); F ($4 % 16, 20, 4); F ($4 / 16, 15, 1);
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F ($2, 16, 4); }
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/* ---------------------------------------------------------------------- */
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| MVFC CREG ',' REG
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{ id24 (2, 0x6a, 0); F ($2, 15, 5); F ($4, 20, 4); }
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{ if ($2 == 13)
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rx_check_v2 ();
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id24 (2, 0x6a, 0); F ($2, 15, 5); F ($4, 20, 4); }
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/* ---------------------------------------------------------------------- */
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@ -757,7 +797,9 @@ statement :
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/* ---------------------------------------------------------------------- */
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| MVTC '#' EXPR ',' CREG
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{ id24 (2, 0x73, 0x00); F ($5, 19, 5); IMM ($3, 12); }
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{ if ($5 == 13)
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rx_check_v2 ();
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id24 (2, 0x73, 0x00); F ($5, 19, 5); IMM ($3, 12); }
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/* ---------------------------------------------------------------------- */
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@ -795,6 +837,62 @@ statement :
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| SBB '#' EXPR ',' REG
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{ id24 (2, 0x70, 0x20); F ($5, 20, 4); NBIMM ($3, 12); }
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/* ---------------------------------------------------------------------- */
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| MOVCO REG ',' '[' REG ']'
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{ rx_check_v2 (); B3 (0xfd, 0x27, 0x00); F ($5, 16, 4); F ($2, 20, 4); }
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/* ---------------------------------------------------------------------- */
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| MOVLI '[' REG ']' ',' REG
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{ rx_check_v2 (); B3 (0xfd, 0x2f, 0x00); F ($3, 16, 4); F ($6, 20, 4); }
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/* ---------------------------------------------------------------------- */
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| EMACA REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x07, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| EMSBA REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x47, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| EMULA REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x03, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MACLH REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x06, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MSBHI REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x44, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MSBLH REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x46, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MSBLO REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x45, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MULLH REG ',' REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x02, 0x00); F ($2, 16, 4); F ($4, 20, 4); F ($6, 12, 1); }
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| MVFACGU { sub_op = 3; } mvfa_op
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| MVTACGU REG ',' ACC
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{ rx_check_v2 (); id24 (2, 0x17, 0x30); F ($4, 16, 1); F ($2, 20, 4); }
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| RACL '#' EXPR ',' ACC
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{ rx_check_v2 (); id24 (2, 0x19, 0x00); F ($5, 16, 1);
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if (rx_uintop ($3, 4) && $3.X_add_number == 1)
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;
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else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
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F (1, 19, 1);
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else
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as_bad (_("RACL expects #1 or #2"));}
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| RDACL '#' EXPR ',' ACC
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{ rx_check_v2 (); id24 (2, 0x19, 0x40); F ($5, 16, 1);
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if (rx_uintop ($3, 4) && $3.X_add_number == 1)
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;
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else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
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F (1, 19, 1);
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else
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as_bad (_("RDACL expects #1 or #2"));}
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| RDACW '#' EXPR ',' ACC
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{ rx_check_v2 (); id24 (2, 0x18, 0x40); F ($5, 16, 1);
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if (rx_uintop ($3, 4) && $3.X_add_number == 1)
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;
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else if (rx_uintop ($3, 4) && $3.X_add_number == 2)
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F (1, 19, 1);
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else
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as_bad (_("RDACW expects #1 or #2"));}
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/* ---------------------------------------------------------------------- */
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;
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|
@ -856,7 +954,18 @@ op_dp20_rr
|
|||
{ B2 (0x7e, sub_op2 << 4); F ($1, 12, 4); }
|
||||
;
|
||||
|
||||
/* xchg, itof, emul, emulu */
|
||||
op_dp20_r
|
||||
: REG ',' REG
|
||||
{ id24 (1, 0x4b + (sub_op2<<2), 0x00); F ($1, 16, 4); F ($3, 20, 4); }
|
||||
;
|
||||
|
||||
op_dp20_ri
|
||||
: { rx_check_v2 (); }
|
||||
op_dp20_r
|
||||
| op_dp20_i
|
||||
;
|
||||
|
||||
/* xchg, utof, itof, emul, emulu */
|
||||
op_xchg
|
||||
: REG ',' REG
|
||||
{ id24 (1, 0x03 + (sub_op<<2), 0); F ($1, 16, 4); F ($3, 20, 4); }
|
||||
|
|
@ -880,6 +989,16 @@ op_shift
|
|||
| op_shift_rot
|
||||
;
|
||||
|
||||
float3_op
|
||||
: '#' EXPR ',' REG
|
||||
{ rx_check_float_support (); id24 (2, 0x72, sub_op << 4); F ($4, 20, 4); O4 ($2); }
|
||||
| REG ',' REG
|
||||
{ rx_check_float_support (); id24 (1, 0x83 + (sub_op << 2), 0); F ($1, 16, 4); F ($3, 20, 4); }
|
||||
| disp '[' REG ']' opt_l ',' REG
|
||||
{ rx_check_float_support (); id24 (1, 0x80 + (sub_op << 2), 0); F ($3, 16, 4); F ($7, 20, 4); DSP ($1, 14, LSIZE); }
|
||||
| REG ',' REG ',' REG
|
||||
{ rx_check_v2 (); id24 (4, 0x80 + (sub_op << 4), 0 ); F ($1, 16, 4); F ($3, 20, 4); F ($5, 12, 4); }
|
||||
;
|
||||
|
||||
float2_op
|
||||
: { rx_check_float_support (); }
|
||||
|
|
@ -897,6 +1016,29 @@ float2_op_ni
|
|||
{ id24 (1, 0x80 + (sub_op << 2), 0); F ($4, 16, 4); F ($8, 20, 4); DSP ($2, 14, LSIZE); }
|
||||
;
|
||||
|
||||
mvfa_op
|
||||
: { rx_check_v2 (); }
|
||||
'#' EXPR ',' ACC ',' REG
|
||||
{ id24 (2, 0x1e, sub_op << 4); F ($7, 20, 4); F ($5, 16, 1);
|
||||
if (rx_uintop ($3, 4))
|
||||
{
|
||||
switch (exp_val ($3))
|
||||
{
|
||||
case 0:
|
||||
F (1, 15, 1);
|
||||
break;
|
||||
case 1:
|
||||
F (1, 15, 1);
|
||||
F (1, 17, 1);
|
||||
break;
|
||||
case 2:
|
||||
break;
|
||||
default:
|
||||
as_bad (_("IMM expects #0 to #2"));}
|
||||
} else
|
||||
as_bad (_("IMM expects #0 to #2"));}
|
||||
;
|
||||
|
||||
/* ====================================================================== */
|
||||
|
||||
disp : { $$ = zero_expr (); }
|
||||
|
|
@ -976,6 +1118,7 @@ token_table[] =
|
|||
{ "isp", CREG, 10 },
|
||||
{ "fintv", CREG, 11 },
|
||||
{ "intb", CREG, 12 },
|
||||
{ "extb", CREG, 13 },
|
||||
|
||||
{ "pbp", CREG, 16 },
|
||||
{ "pben", CREG, 17 },
|
||||
|
|
@ -998,6 +1141,9 @@ token_table[] =
|
|||
{ "i", FLAG, 8 },
|
||||
{ "u", FLAG, 9 },
|
||||
|
||||
{ "a0", ACC, 0 },
|
||||
{ "a1", ACC, 1 },
|
||||
|
||||
#define OPC(x) { #x, x, IS_OPCODE }
|
||||
OPC(ABS),
|
||||
OPC(ADC),
|
||||
|
|
@ -1019,35 +1165,49 @@ token_table[] =
|
|||
OPC(DIVU),
|
||||
OPC(EDIV),
|
||||
OPC(EDIVU),
|
||||
OPC(EMACA),
|
||||
OPC(EMSBA),
|
||||
OPC(EMUL),
|
||||
OPC(EMULA),
|
||||
OPC(EMULU),
|
||||
OPC(FADD),
|
||||
OPC(FCMP),
|
||||
OPC(FDIV),
|
||||
OPC(FMUL),
|
||||
OPC(FREIT),
|
||||
OPC(FSQRT),
|
||||
OPC(FTOU),
|
||||
OPC(FSUB),
|
||||
OPC(FTOI),
|
||||
OPC(INT),
|
||||
OPC(ITOF),
|
||||
OPC(JMP),
|
||||
OPC(JSR),
|
||||
OPC(MVFACGU),
|
||||
OPC(MVFACHI),
|
||||
OPC(MVFACMI),
|
||||
OPC(MVFACLO),
|
||||
OPC(MVFC),
|
||||
OPC(MVTACGU),
|
||||
OPC(MVTACHI),
|
||||
OPC(MVTACLO),
|
||||
OPC(MVTC),
|
||||
OPC(MVTIPL),
|
||||
OPC(MACHI),
|
||||
OPC(MACLO),
|
||||
OPC(MACLH),
|
||||
OPC(MAX),
|
||||
OPC(MIN),
|
||||
OPC(MOV),
|
||||
OPC(MOVCO),
|
||||
OPC(MOVLI),
|
||||
OPC(MOVU),
|
||||
OPC(MSBHI),
|
||||
OPC(MSBLH),
|
||||
OPC(MSBLO),
|
||||
OPC(MUL),
|
||||
OPC(MULHI),
|
||||
OPC(MULLH),
|
||||
OPC(MULLO),
|
||||
OPC(MULU),
|
||||
OPC(NEG),
|
||||
|
|
@ -1061,7 +1221,10 @@ token_table[] =
|
|||
OPC(PUSHA),
|
||||
OPC(PUSHC),
|
||||
OPC(PUSHM),
|
||||
OPC(RACL),
|
||||
OPC(RACW),
|
||||
OPC(RDACL),
|
||||
OPC(RDACW),
|
||||
OPC(REIT),
|
||||
OPC(REVL),
|
||||
OPC(REVW),
|
||||
|
|
@ -1095,6 +1258,7 @@ token_table[] =
|
|||
OPC(SUNTIL),
|
||||
OPC(SWHILE),
|
||||
OPC(TST),
|
||||
OPC(UTOF),
|
||||
OPC(WAIT),
|
||||
OPC(XCHG),
|
||||
OPC(XOR),
|
||||
|
|
@ -1643,3 +1807,10 @@ rx_check_float_support (void)
|
|||
if (rx_cpu == RX100 || rx_cpu == RX200)
|
||||
rx_error (_("target CPU type does not support floating point instructions"));
|
||||
}
|
||||
|
||||
static void
|
||||
rx_check_v2 (void)
|
||||
{
|
||||
if (rx_cpu < RXV2)
|
||||
rx_error (_("target CPU type does not support v2 instructions"));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -106,6 +106,21 @@ struct option md_longopts[] =
|
|||
};
|
||||
size_t md_longopts_size = sizeof (md_longopts);
|
||||
|
||||
struct cpu_type
|
||||
{
|
||||
char *cpu_name;
|
||||
int type;
|
||||
};
|
||||
|
||||
struct cpu_type cpu_type_list[] =
|
||||
{
|
||||
{"rx100",RX100},
|
||||
{"rx200",RX200},
|
||||
{"rx600",RX600},
|
||||
{"rx610",RX610},
|
||||
{"rxv2",RXV2}
|
||||
};
|
||||
|
||||
int
|
||||
md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
|
||||
{
|
||||
|
|
@ -161,25 +176,27 @@ md_parse_option (int c ATTRIBUTE_UNUSED, char * arg ATTRIBUTE_UNUSED)
|
|||
return 1;
|
||||
|
||||
case OPTION_CPU:
|
||||
if (strcasecmp (arg, "rx100") == 0)
|
||||
rx_cpu = RX100;
|
||||
else if (strcasecmp (arg, "rx200") == 0)
|
||||
rx_cpu = RX200;
|
||||
else if (strcasecmp (arg, "rx600") == 0)
|
||||
rx_cpu = RX600;
|
||||
else if (strcasecmp (arg, "rx610") == 0)
|
||||
rx_cpu = RX610;
|
||||
else
|
||||
{
|
||||
as_warn (_("unrecognised RX CPU type %s"), arg);
|
||||
break;
|
||||
}
|
||||
return 1;
|
||||
{
|
||||
unsigned int i;
|
||||
for (i = 0; i < ARRAY_SIZE (cpu_type_list); i++)
|
||||
{
|
||||
if (strcasecmp (arg, cpu_type_list[i].cpu_name) == 0)
|
||||
{
|
||||
rx_cpu = cpu_type_list[i].type;
|
||||
if (rx_cpu == RXV2)
|
||||
elf_flags |= E_FLAG_RX_V2;
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
as_warn (_("unrecognised RX CPU type %s"), arg);
|
||||
break;
|
||||
}
|
||||
|
||||
case OPTION_DISALLOW_STRING_INSNS:
|
||||
elf_flags |= E_FLAG_RX_SINSNS_SET | E_FLAG_RX_SINSNS_NO;
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -197,7 +214,7 @@ md_show_usage (FILE * stream)
|
|||
fprintf (stream, _(" --mrelax\n"));
|
||||
fprintf (stream, _(" --mpid\n"));
|
||||
fprintf (stream, _(" --mint-register=<value>\n"));
|
||||
fprintf (stream, _(" --mcpu=<rx100|rx200|rx600|rx610>\n"));
|
||||
fprintf (stream, _(" --mcpu=<rx100|rx200|rx600|rx610|rxv2>\n"));
|
||||
fprintf (stream, _(" --mno-allow-string-insns"));
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -108,9 +108,10 @@ alignments. This option is the default.
|
|||
@cindex @samp{-mcpu=}
|
||||
@item -mcpu=@var{name}
|
||||
This option tells the assembler the target CPU type. Currently the
|
||||
@code{rx200}, @code{rx600} and @code{rx610} are recognised as valid
|
||||
cpu names. Attempting to assemble an instruction not supported by the
|
||||
indicated cpu type will result in an error message being generated.
|
||||
@code{rx100}, @code{rx200}, @code{rx600}, @code{rx610} and @code{rxv2}
|
||||
are recognised as valid cpu names. Attempting to assemble an instruction
|
||||
not supported by the indicated cpu type will result in an error message
|
||||
being generated.
|
||||
|
||||
@cindex @samp{-mno-allow-string-insns}
|
||||
@item -mno-allow-string-insns
|
||||
|
|
|
|||
|
|
@ -68,6 +68,71 @@
|
|||
* gas/aarch64/advsimd-fp16.d: New.
|
||||
* gas/aarch64/advsimd-fp16.s: New.
|
||||
|
||||
2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
|
||||
|
||||
* gas/rx/emaca.d: New.
|
||||
* gas/rx/emaca.sm: New.
|
||||
* gas/rx/emsba.d: New.
|
||||
* gas/rx/emsba.sm: New.
|
||||
* gas/rx/emula.d: New.
|
||||
* gas/rx/emula.sm: New.
|
||||
* gas/rx/fadd.d: Add new pattern.
|
||||
* gas/rx/fadd.sm: Add new pattern.
|
||||
* gas/rx/fmul.d: Add new pattern.
|
||||
* gas/rx/fmul.sm: Add new pattern.
|
||||
* gas/rx/fsqrt.d: New.
|
||||
* gas/rx/fsqrt.sm: New.
|
||||
* gas/rx/fsub.d: Add new pattern.
|
||||
* gas/rx/fsub.sm: Add new pattern.
|
||||
* gas/rx/ftou.d: New.
|
||||
* gas/rx/ftou.sm: New.
|
||||
* gas/rx/maclh.d: New.
|
||||
* gas/rx/maclh.sm: New.
|
||||
* gas/rx/maclo.d: Add new pattern.
|
||||
* gas/rx/maclo.sm: Add new pattern.
|
||||
* gas/rx/macros.inc: Add new register.
|
||||
* gas/rx/movco.d: New.
|
||||
* gas/rx/movco.sm: New.
|
||||
* gas/rx/movli.d: New.
|
||||
* gas/rx/movli.sm: New.
|
||||
* gas/rx/msbhi.d: New.
|
||||
* gas/rx/msbhi.sm: New.
|
||||
* gas/rx/msblh.d: New.
|
||||
* gas/rx/msblh.sm: New.
|
||||
* gas/rx/msblo.d: New.
|
||||
* gas/rx/msblo.sm: New.
|
||||
* gas/rx/mullh.d: New.
|
||||
* gas/rx/mullh.sm: New.
|
||||
* gas/rx/mvfacgu.d: New.
|
||||
* gas/rx/mvfacgu.sm: New.
|
||||
* gas/rx/mvfachi.d: Add new pattern.
|
||||
* gas/rx/mvfachi.sm: Add new pattern.
|
||||
* gas/rx/mvfaclo.d: Add new pattern.
|
||||
* gas/rx/mvfaclo.sm: Add new pattern.
|
||||
* gas/rx/mvfacmi.d: Add new pattern.
|
||||
* gas/rx/mvfacmi.sm: Add new pattern.
|
||||
* gas/rx/mvfc.d: Add new pattern.
|
||||
* gas/rx/mvtacgu.d: New.
|
||||
* gas/rx/mvtacgu.sm: New.
|
||||
* gas/rx/mvtc.d: Add new pattern.
|
||||
* gas/rx/popc.d: Add new pattern.
|
||||
* gas/rx/pushc.d: Add new pattern.
|
||||
* gas/rx/racl.d: New.
|
||||
* gas/rx/racl.sm: New.
|
||||
* gas/rx/racw.d: Add new pattern.
|
||||
* gas/rx/racw.sm: Add new pattern.
|
||||
* gas/rx/rdacl.d: New.
|
||||
* gas/rx/rdacl.sm: New.
|
||||
* gas/rx/rdacw.d: New.
|
||||
* gas/rx/rdacw.sm: New.
|
||||
* gas/rx/rx.exp: Add option.
|
||||
* gas/rx/stnz.d: Add new pattern.
|
||||
* gas/rx/stnz.sm: Add new pattern.
|
||||
* gas/rx/stz.d: Add new pattern.
|
||||
* gas/rx/stz.sm: Add new pattern.
|
||||
* gas/rx/utof.d: New.
|
||||
* gas/rx/utof.sm: New.
|
||||
|
||||
2015-12-12 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* gas/sh/tlsd.s: Use .tdata not .tbss.
|
||||
|
|
|
|||
16
gas/testsuite/gas/rx/emaca.d
Normal file
16
gas/testsuite/gas/rx/emaca.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 07 00 emaca r0, r0, a0
|
||||
3: fd 07 0f emaca r0, r15, a0
|
||||
6: fd 07 f0 emaca r15, r0, a0
|
||||
9: fd 07 ff emaca r15, r15, a0
|
||||
c: fd 0f 00 emaca r0, r0, a1
|
||||
f: fd 0f 0f emaca r0, r15, a1
|
||||
12: fd 0f f0 emaca r15, r0, a1
|
||||
15: fd 0f ff emaca r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/emaca.sm
Normal file
2
gas/testsuite/gas/rx/emaca.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
emaca {reg},{reg},a0
|
||||
emaca {reg},{reg},a1
|
||||
16
gas/testsuite/gas/rx/emsba.d
Normal file
16
gas/testsuite/gas/rx/emsba.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 47 00 emsba r0, r0, a0
|
||||
3: fd 47 0f emsba r0, r15, a0
|
||||
6: fd 47 f0 emsba r15, r0, a0
|
||||
9: fd 47 ff emsba r15, r15, a0
|
||||
c: fd 4f 00 emsba r0, r0, a1
|
||||
f: fd 4f 0f emsba r0, r15, a1
|
||||
12: fd 4f f0 emsba r15, r0, a1
|
||||
15: fd 4f ff emsba r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/emsba.sm
Normal file
2
gas/testsuite/gas/rx/emsba.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
emsba {reg},{reg},a0
|
||||
emsba {reg},{reg},a1
|
||||
16
gas/testsuite/gas/rx/emula.d
Normal file
16
gas/testsuite/gas/rx/emula.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 03 00 emula r0, r0, a0
|
||||
3: fd 03 0f emula r0, r15, a0
|
||||
6: fd 03 f0 emula r15, r0, a0
|
||||
9: fd 03 ff emula r15, r15, a0
|
||||
c: fd 0b 00 emula r0, r0, a1
|
||||
f: fd 0b 0f emula r0, r15, a1
|
||||
12: fd 0b f0 emula r15, r0, a1
|
||||
15: fd 0b ff emula r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/emula.sm
Normal file
2
gas/testsuite/gas/rx/emula.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
emula {reg},{reg},a0
|
||||
emula {reg},{reg},a1
|
||||
|
|
@ -26,3 +26,11 @@ Disassembly of section \.text:
|
|||
49: fc 8a 0f ff 3f fadd 65532\[r0\]\.l, r15
|
||||
4e: fc 8a f0 ff 3f fadd 65532\[r15\]\.l, r0
|
||||
53: fc 8a ff ff 3f fadd 65532\[r15\]\.l, r15
|
||||
58: ff a0 00 fadd r0, r0, r0
|
||||
5b: ff af 00 fadd r0, r0, r15
|
||||
5e: ff a0 0f fadd r0, r15, r0
|
||||
61: ff af 0f fadd r0, r15, r15
|
||||
64: ff a0 f0 fadd r15, r0, r0
|
||||
67: ff af f0 fadd r15, r0, r15
|
||||
6a: ff a0 ff fadd r15, r15, r0
|
||||
6d: ff af ff fadd r15, r15, r15
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
fadd #{imm32},{reg}
|
||||
fadd {reg},{reg}
|
||||
fadd {mem}.L,{reg}
|
||||
fadd {reg},{reg},{reg}
|
||||
|
|
|
|||
|
|
@ -26,3 +26,11 @@ Disassembly of section \.text:
|
|||
49: fc 8e 0f ff 3f fmul 65532\[r0\]\.l, r15
|
||||
4e: fc 8e f0 ff 3f fmul 65532\[r15\]\.l, r0
|
||||
53: fc 8e ff ff 3f fmul 65532\[r15\]\.l, r15
|
||||
58: ff b0 00 fmul r0, r0, r0
|
||||
5b: ff bf 00 fmul r0, r0, r15
|
||||
5e: ff b0 0f fmul r0, r15, r0
|
||||
61: ff bf 0f fmul r0, r15, r15
|
||||
64: ff b0 f0 fmul r15, r0, r0
|
||||
67: ff bf f0 fmul r15, r0, r15
|
||||
6a: ff b0 ff fmul r15, r15, r0
|
||||
6d: ff bf ff fmul r15, r15, r15
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
fmul #{imm32},{reg}
|
||||
fmul {reg},{reg}
|
||||
fmul {mem}.L,{reg}
|
||||
fmul {reg},{reg},{reg}
|
||||
|
|
|
|||
24
gas/testsuite/gas/rx/fsqrt.d
Normal file
24
gas/testsuite/gas/rx/fsqrt.d
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fc a3 00 fsqrt r0, r0
|
||||
3: fc a3 0f fsqrt r0, r15
|
||||
6: fc a3 f0 fsqrt r15, r0
|
||||
9: fc a3 ff fsqrt r15, r15
|
||||
c: fc a0 00 fsqrt \[r0\]\.l, r0
|
||||
f: fc a0 0f fsqrt \[r0\]\.l, r15
|
||||
12: fc a0 f0 fsqrt \[r15\]\.l, r0
|
||||
15: fc a0 ff fsqrt \[r15\]\.l, r15
|
||||
18: fc a1 00 3f fsqrt 252\[r0\]\.l, r0
|
||||
1c: fc a1 0f 3f fsqrt 252\[r0\]\.l, r15
|
||||
20: fc a1 f0 3f fsqrt 252\[r15\]\.l, r0
|
||||
24: fc a1 ff 3f fsqrt 252\[r15\]\.l, r15
|
||||
28: fc a2 00 ff 3f fsqrt 65532\[r0\]\.l, r0
|
||||
2d: fc a2 0f ff 3f fsqrt 65532\[r0\]\.l, r15
|
||||
32: fc a2 f0 ff 3f fsqrt 65532\[r15\]\.l, r0
|
||||
37: fc a2 ff ff 3f fsqrt 65532\[r15\]\.l, r15
|
||||
2
gas/testsuite/gas/rx/fsqrt.sm
Normal file
2
gas/testsuite/gas/rx/fsqrt.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
fsqrt {reg},{reg}
|
||||
fsqrt {mem}.L,{reg}
|
||||
|
|
@ -26,3 +26,11 @@ Disassembly of section \.text:
|
|||
49: fc 82 0f ff 3f fsub 65532\[r0\]\.l, r15
|
||||
4e: fc 82 f0 ff 3f fsub 65532\[r15\]\.l, r0
|
||||
53: fc 82 ff ff 3f fsub 65532\[r15\]\.l, r15
|
||||
58: ff 80 00 fsub r0, r0, r0
|
||||
5b: ff 8f 00 fsub r0, r0, r15
|
||||
5e: ff 80 0f fsub r0, r15, r0
|
||||
61: ff 8f 0f fsub r0, r15, r15
|
||||
64: ff 80 f0 fsub r15, r0, r0
|
||||
67: ff 8f f0 fsub r15, r0, r15
|
||||
6a: ff 80 ff fsub r15, r15, r0
|
||||
6d: ff 8f ff fsub r15, r15, r15
|
||||
|
|
|
|||
|
|
@ -1,3 +1,4 @@
|
|||
fsub #{imm32},{reg}
|
||||
fsub {reg},{reg}
|
||||
fsub {mem}.L,{reg}
|
||||
fsub {reg},{reg},{reg}
|
||||
|
|
|
|||
24
gas/testsuite/gas/rx/ftou.d
Normal file
24
gas/testsuite/gas/rx/ftou.d
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fc a7 00 ftou r0, r0
|
||||
3: fc a7 0f ftou r0, r15
|
||||
6: fc a7 f0 ftou r15, r0
|
||||
9: fc a7 ff ftou r15, r15
|
||||
c: fc a4 00 ftou \[r0\]\.l, r0
|
||||
f: fc a4 0f ftou \[r0\]\.l, r15
|
||||
12: fc a4 f0 ftou \[r15\]\.l, r0
|
||||
15: fc a4 ff ftou \[r15\]\.l, r15
|
||||
18: fc a5 00 3f ftou 252\[r0\]\.l, r0
|
||||
1c: fc a5 0f 3f ftou 252\[r0\]\.l, r15
|
||||
20: fc a5 f0 3f ftou 252\[r15\]\.l, r0
|
||||
24: fc a5 ff 3f ftou 252\[r15\]\.l, r15
|
||||
28: fc a6 00 ff 3f ftou 65532\[r0\]\.l, r0
|
||||
2d: fc a6 0f ff 3f ftou 65532\[r0\]\.l, r15
|
||||
32: fc a6 f0 ff 3f ftou 65532\[r15\]\.l, r0
|
||||
37: fc a6 ff ff 3f ftou 65532\[r15\]\.l, r15
|
||||
2
gas/testsuite/gas/rx/ftou.sm
Normal file
2
gas/testsuite/gas/rx/ftou.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
ftou {reg},{reg}
|
||||
ftou {mem}.L,{reg}
|
||||
|
|
@ -3,9 +3,9 @@
|
|||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section .text:
|
||||
Disassembly of section .*:
|
||||
|
||||
00000000 <_start>:
|
||||
00000000 <.*>:
|
||||
0: ce f1 04 00 mov\.b 4\[r15\], r1
|
||||
2: R_RX_SYM _foo
|
||||
2: R_RX_SYM __gp
|
||||
|
|
@ -16,7 +16,7 @@ Disassembly of section .text:
|
|||
6: R_RX_SYM __gp
|
||||
6: R_RX_OPsub __gp
|
||||
6: R_RX_ABS16U __gp
|
||||
8: ce f1 00 00 mov\.b \[r15\], r1
|
||||
8: ce f1 00 00 mov\.b 0\[r15\], r1
|
||||
a: R_RX_SYM _grill
|
||||
a: R_RX_SYM __gp
|
||||
a: R_RX_OPsub __gp
|
||||
|
|
@ -31,7 +31,7 @@ Disassembly of section .text:
|
|||
12: R_RX_SYM __gp
|
||||
12: R_RX_OPsub __gp
|
||||
12: R_RX_ABS16UW __gp
|
||||
14: de f1 00 00 mov\.w \[r15\], r1
|
||||
14: de f1 00 00 mov\.w 0\[r15\], r1
|
||||
16: R_RX_SYM _grill
|
||||
16: R_RX_SYM __gp
|
||||
16: R_RX_OPsub __gp
|
||||
|
|
@ -46,7 +46,7 @@ Disassembly of section .text:
|
|||
1e: R_RX_SYM __gp
|
||||
1e: R_RX_OPsub __gp
|
||||
1e: R_RX_ABS16UL __gp
|
||||
20: ee f1 00 00 mov\.l \[r15\], r1
|
||||
20: ee f1 00 00 mov\.l 0\[r15\], r1
|
||||
22: R_RX_SYM _grill
|
||||
22: R_RX_SYM __gp
|
||||
22: R_RX_OPsub __gp
|
||||
|
|
|
|||
|
|
@ -6,7 +6,15 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 04 00 machi r0, r0
|
||||
3: fd 04 0f machi r0, r15
|
||||
6: fd 04 f0 machi r15, r0
|
||||
9: fd 04 ff machi r15, r15
|
||||
0: fd 04 00 machi r0, r0, a0
|
||||
3: fd 04 0f machi r0, r15, a0
|
||||
6: fd 04 f0 machi r15, r0, a0
|
||||
9: fd 04 ff machi r15, r15, a0
|
||||
c: fd 04 00 machi r0, r0, a0
|
||||
f: fd 04 0f machi r0, r15, a0
|
||||
12: fd 04 f0 machi r15, r0, a0
|
||||
15: fd 04 ff machi r15, r15, a0
|
||||
18: fd 0c 00 machi r0, r0, a1
|
||||
1b: fd 0c 0f machi r0, r15, a1
|
||||
1e: fd 0c f0 machi r15, r0, a1
|
||||
21: fd 0c ff machi r15, r15, a1
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
machi {reg},{reg}
|
||||
machi {reg},{reg},a0
|
||||
machi {reg},{reg},a1
|
||||
|
|
|
|||
16
gas/testsuite/gas/rx/maclh.d
Normal file
16
gas/testsuite/gas/rx/maclh.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 06 00 maclh r0, r0, a0
|
||||
3: fd 06 0f maclh r0, r15, a0
|
||||
6: fd 06 f0 maclh r15, r0, a0
|
||||
9: fd 06 ff maclh r15, r15, a0
|
||||
c: fd 0e 00 maclh r0, r0, a1
|
||||
f: fd 0e 0f maclh r0, r15, a1
|
||||
12: fd 0e f0 maclh r15, r0, a1
|
||||
15: fd 0e ff maclh r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/maclh.sm
Normal file
2
gas/testsuite/gas/rx/maclh.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
maclh {reg},{reg},a0
|
||||
maclh {reg},{reg},a1
|
||||
|
|
@ -6,7 +6,15 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 05 00 maclo r0, r0
|
||||
3: fd 05 0f maclo r0, r15
|
||||
6: fd 05 f0 maclo r15, r0
|
||||
9: fd 05 ff maclo r15, r15
|
||||
0: fd 05 00 maclo r0, r0, a0
|
||||
3: fd 05 0f maclo r0, r15, a0
|
||||
6: fd 05 f0 maclo r15, r0, a0
|
||||
9: fd 05 ff maclo r15, r15, a0
|
||||
c: fd 05 00 maclo r0, r0, a0
|
||||
f: fd 05 0f maclo r0, r15, a0
|
||||
12: fd 05 f0 maclo r15, r0, a0
|
||||
15: fd 05 ff maclo r15, r15, a0
|
||||
18: fd 0d 00 maclo r0, r0, a1
|
||||
1b: fd 0d 0f maclo r0, r15, a1
|
||||
1e: fd 0d f0 maclo r15, r0, a1
|
||||
21: fd 0d ff maclo r15, r15, a1
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
maclo {reg},{reg}
|
||||
maclo {reg},{reg},a0
|
||||
maclo {reg},{reg},a1
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@ macro reg2 {r0;r14}
|
|||
macro reg7 {r0;r7}
|
||||
macro regPlo {r1;r7}
|
||||
macro regPhi {r8;r14}
|
||||
macro creg {psw;fpsw;usp;isp;intb;bpsw;bpc;fintv}
|
||||
macro creg {psw;fpsw;usp;isp;intb;bpsw;bpc;fintv;extb}
|
||||
macro pswf {U;I;O;S;Z;C}
|
||||
|
||||
macro simm8 {-128;127}
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@
|
|||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \..*:
|
||||
Disassembly of section .*:
|
||||
|
||||
00000000 <\..*>:
|
||||
00000000 <.*>:
|
||||
0: fd 74 40 80 max #-128, r0
|
||||
4: fd 74 4f 80 max #-128, r15
|
||||
8: fd 74 40 7f max #127, r0
|
||||
|
|
|
|||
|
|
@ -5,7 +5,7 @@ dump\.o: file format .*
|
|||
|
||||
Disassembly of section .*:
|
||||
|
||||
00000000 <\..*>:
|
||||
00000000 <.*>:
|
||||
[0-9a-f]+: c3 00[ ]+mov\.b r0, \[r0\]
|
||||
[0-9a-f]+: c3 70[ ]+mov\.b r0, \[r7\]
|
||||
[0-9a-f]+: c3 07[ ]+mov\.b r7, \[r0\]
|
||||
|
|
|
|||
12
gas/testsuite/gas/rx/movco.d
Normal file
12
gas/testsuite/gas/rx/movco.d
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 27 00 movco r0, \[r0\]
|
||||
3: fd 27 f0 movco r0, \[r15\]
|
||||
6: fd 27 0f movco r15, \[r0\]
|
||||
9: fd 27 ff movco r15, \[r15\]
|
||||
1
gas/testsuite/gas/rx/movco.sm
Normal file
1
gas/testsuite/gas/rx/movco.sm
Normal file
|
|
@ -0,0 +1 @@
|
|||
movco {reg},[{reg}]
|
||||
12
gas/testsuite/gas/rx/movli.d
Normal file
12
gas/testsuite/gas/rx/movli.d
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 2f 00 movli \[r0\], r0
|
||||
3: fd 2f 0f movli \[r0\], r15
|
||||
6: fd 2f f0 movli \[r15\], r0
|
||||
9: fd 2f ff movli \[r15\], r15
|
||||
1
gas/testsuite/gas/rx/movli.sm
Normal file
1
gas/testsuite/gas/rx/movli.sm
Normal file
|
|
@ -0,0 +1 @@
|
|||
movli [{reg}],{reg}
|
||||
16
gas/testsuite/gas/rx/msbhi.d
Normal file
16
gas/testsuite/gas/rx/msbhi.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 44 00 msbhi r0, r0, a0
|
||||
3: fd 44 0f msbhi r0, r15, a0
|
||||
6: fd 44 f0 msbhi r15, r0, a0
|
||||
9: fd 44 ff msbhi r15, r15, a0
|
||||
c: fd 4c 00 msbhi r0, r0, a1
|
||||
f: fd 4c 0f msbhi r0, r15, a1
|
||||
12: fd 4c f0 msbhi r15, r0, a1
|
||||
15: fd 4c ff msbhi r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/msbhi.sm
Normal file
2
gas/testsuite/gas/rx/msbhi.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
msbhi {reg},{reg},a0
|
||||
msbhi {reg},{reg},a1
|
||||
16
gas/testsuite/gas/rx/msblh.d
Normal file
16
gas/testsuite/gas/rx/msblh.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 46 00 msblh r0, r0, a0
|
||||
3: fd 46 0f msblh r0, r15, a0
|
||||
6: fd 46 f0 msblh r15, r0, a0
|
||||
9: fd 46 ff msblh r15, r15, a0
|
||||
c: fd 4e 00 msblh r0, r0, a1
|
||||
f: fd 4e 0f msblh r0, r15, a1
|
||||
12: fd 4e f0 msblh r15, r0, a1
|
||||
15: fd 4e ff msblh r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/msblh.sm
Normal file
2
gas/testsuite/gas/rx/msblh.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
msblh {reg},{reg},a0
|
||||
msblh {reg},{reg},a1
|
||||
16
gas/testsuite/gas/rx/msblo.d
Normal file
16
gas/testsuite/gas/rx/msblo.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 45 00 msblo r0, r0, a0
|
||||
3: fd 45 0f msblo r0, r15, a0
|
||||
6: fd 45 f0 msblo r15, r0, a0
|
||||
9: fd 45 ff msblo r15, r15, a0
|
||||
c: fd 4d 00 msblo r0, r0, a1
|
||||
f: fd 4d 0f msblo r0, r15, a1
|
||||
12: fd 4d f0 msblo r15, r0, a1
|
||||
15: fd 4d ff msblo r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/msblo.sm
Normal file
2
gas/testsuite/gas/rx/msblo.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
msblo {reg},{reg},a0
|
||||
msblo {reg},{reg},a1
|
||||
|
|
@ -6,7 +6,15 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 00 00 mulhi r0, r0
|
||||
3: fd 00 0f mulhi r0, r15
|
||||
6: fd 00 f0 mulhi r15, r0
|
||||
9: fd 00 ff mulhi r15, r15
|
||||
0: fd 00 00 mulhi r0, r0, a0
|
||||
3: fd 00 0f mulhi r0, r15, a0
|
||||
6: fd 00 f0 mulhi r15, r0, a0
|
||||
9: fd 00 ff mulhi r15, r15, a0
|
||||
c: fd 00 00 mulhi r0, r0, a0
|
||||
f: fd 00 0f mulhi r0, r15, a0
|
||||
12: fd 00 f0 mulhi r15, r0, a0
|
||||
15: fd 00 ff mulhi r15, r15, a0
|
||||
18: fd 08 00 mulhi r0, r0, a1
|
||||
1b: fd 08 0f mulhi r0, r15, a1
|
||||
1e: fd 08 f0 mulhi r15, r0, a1
|
||||
21: fd 08 ff mulhi r15, r15, a1
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
mulhi {reg},{reg}
|
||||
mulhi {reg},{reg},a0
|
||||
mulhi {reg},{reg},a1
|
||||
|
|
|
|||
16
gas/testsuite/gas/rx/mullh.d
Normal file
16
gas/testsuite/gas/rx/mullh.d
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 02 00 mullh r0, r0, a0
|
||||
3: fd 02 0f mullh r0, r15, a0
|
||||
6: fd 02 f0 mullh r15, r0, a0
|
||||
9: fd 02 ff mullh r15, r15, a0
|
||||
c: fd 0a 00 mullh r0, r0, a1
|
||||
f: fd 0a 0f mullh r0, r15, a1
|
||||
12: fd 0a f0 mullh r15, r0, a1
|
||||
15: fd 0a ff mullh r15, r15, a1
|
||||
2
gas/testsuite/gas/rx/mullh.sm
Normal file
2
gas/testsuite/gas/rx/mullh.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
mullh {reg},{reg},a0
|
||||
mullh {reg},{reg},a1
|
||||
|
|
@ -6,7 +6,15 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 01 00 mullo r0, r0
|
||||
3: fd 01 0f mullo r0, r15
|
||||
6: fd 01 f0 mullo r15, r0
|
||||
9: fd 01 ff mullo r15, r15
|
||||
0: fd 01 00 mullo r0, r0, a0
|
||||
3: fd 01 0f mullo r0, r15, a0
|
||||
6: fd 01 f0 mullo r15, r0, a0
|
||||
9: fd 01 ff mullo r15, r15, a0
|
||||
c: fd 01 00 mullo r0, r0, a0
|
||||
f: fd 01 0f mullo r0, r15, a0
|
||||
12: fd 01 f0 mullo r15, r0, a0
|
||||
15: fd 01 ff mullo r15, r15, a0
|
||||
18: fd 09 00 mullo r0, r0, a1
|
||||
1b: fd 09 0f mullo r0, r15, a1
|
||||
1e: fd 09 f0 mullo r15, r0, a1
|
||||
21: fd 09 ff mullo r15, r15, a1
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
mullo {reg},{reg}
|
||||
mullo {reg},{reg},a0
|
||||
mullo {reg},{reg},a1
|
||||
|
|
|
|||
20
gas/testsuite/gas/rx/mvfacgu.d
Normal file
20
gas/testsuite/gas/rx/mvfacgu.d
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 1f 30 mvfacgu #0, a0, r0
|
||||
3: fd 1f 3f mvfacgu #0, a0, r15
|
||||
6: fd 1f 70 mvfacgu #1, a0, r0
|
||||
9: fd 1f 7f mvfacgu #1, a0, r15
|
||||
c: fd 1e 30 mvfacgu #2, a0, r0
|
||||
f: fd 1e 3f mvfacgu #2, a0, r15
|
||||
12: fd 1f b0 mvfacgu #0, a1, r0
|
||||
15: fd 1f bf mvfacgu #0, a1, r15
|
||||
18: fd 1f f0 mvfacgu #1, a1, r0
|
||||
1b: fd 1f ff mvfacgu #1, a1, r15
|
||||
1e: fd 1e b0 mvfacgu #2, a1, r0
|
||||
21: fd 1e bf mvfacgu #2, a1, r15
|
||||
6
gas/testsuite/gas/rx/mvfacgu.sm
Normal file
6
gas/testsuite/gas/rx/mvfacgu.sm
Normal file
|
|
@ -0,0 +1,6 @@
|
|||
mvfacgu #0,a0,{reg}
|
||||
mvfacgu #1,a0,{reg}
|
||||
mvfacgu #2,a0,{reg}
|
||||
mvfacgu #0,a1,{reg}
|
||||
mvfacgu #1,a1,{reg}
|
||||
mvfacgu #2,a1,{reg}
|
||||
|
|
@ -6,5 +6,17 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 1f 00 mvfachi r0
|
||||
3: fd 1f 0f mvfachi r15
|
||||
0: fd 1f 00 mvfachi #0, a0, r0
|
||||
3: fd 1f 0f mvfachi #0, a0, r15
|
||||
6: fd 1f 00 mvfachi #0, a0, r0
|
||||
9: fd 1f 0f mvfachi #0, a0, r15
|
||||
c: fd 1f 40 mvfachi #1, a0, r0
|
||||
f: fd 1f 4f mvfachi #1, a0, r15
|
||||
12: fd 1e 00 mvfachi #2, a0, r0
|
||||
15: fd 1e 0f mvfachi #2, a0, r15
|
||||
18: fd 1f 80 mvfachi #0, a1, r0
|
||||
1b: fd 1f 8f mvfachi #0, a1, r15
|
||||
1e: fd 1f c0 mvfachi #1, a1, r0
|
||||
21: fd 1f cf mvfachi #1, a1, r15
|
||||
24: fd 1e 80 mvfachi #2, a1, r0
|
||||
27: fd 1e 8f mvfachi #2, a1, r15
|
||||
|
|
|
|||
|
|
@ -1 +1,7 @@
|
|||
mvfachi {reg}
|
||||
mvfachi #0,a0,{reg}
|
||||
mvfachi #1,a0,{reg}
|
||||
mvfachi #2,a0,{reg}
|
||||
mvfachi #0,a1,{reg}
|
||||
mvfachi #1,a1,{reg}
|
||||
mvfachi #2,a1,{reg}
|
||||
|
|
|
|||
|
|
@ -6,5 +6,17 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 1f 10 mvfaclo r0
|
||||
3: fd 1f 1f mvfaclo r15
|
||||
0: fd 1f 10 mvfaclo #0, a0, r0
|
||||
3: fd 1f 1f mvfaclo #0, a0, r15
|
||||
6: fd 1f 10 mvfaclo #0, a0, r0
|
||||
9: fd 1f 1f mvfaclo #0, a0, r15
|
||||
c: fd 1f 50 mvfaclo #1, a0, r0
|
||||
f: fd 1f 5f mvfaclo #1, a0, r15
|
||||
12: fd 1e 10 mvfaclo #2, a0, r0
|
||||
15: fd 1e 1f mvfaclo #2, a0, r15
|
||||
18: fd 1f 90 mvfaclo #0, a1, r0
|
||||
1b: fd 1f 9f mvfaclo #0, a1, r15
|
||||
1e: fd 1f d0 mvfaclo #1, a1, r0
|
||||
21: fd 1f df mvfaclo #1, a1, r15
|
||||
24: fd 1e 90 mvfaclo #2, a1, r0
|
||||
27: fd 1e 9f mvfaclo #2, a1, r15
|
||||
|
|
|
|||
|
|
@ -1 +1,7 @@
|
|||
mvfaclo {reg}
|
||||
mvfaclo #0,a0,{reg}
|
||||
mvfaclo #1,a0,{reg}
|
||||
mvfaclo #2,a0,{reg}
|
||||
mvfaclo #0,a1,{reg}
|
||||
mvfaclo #1,a1,{reg}
|
||||
mvfaclo #2,a1,{reg}
|
||||
|
|
|
|||
|
|
@ -6,5 +6,17 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 1f 20 mvfacmi r0
|
||||
3: fd 1f 2f mvfacmi r15
|
||||
0: fd 1f 20 mvfacmi #0, a0, r0
|
||||
3: fd 1f 2f mvfacmi #0, a0, r15
|
||||
6: fd 1f 20 mvfacmi #0, a0, r0
|
||||
9: fd 1f 2f mvfacmi #0, a0, r15
|
||||
c: fd 1f 60 mvfacmi #1, a0, r0
|
||||
f: fd 1f 6f mvfacmi #1, a0, r15
|
||||
12: fd 1e 20 mvfacmi #2, a0, r0
|
||||
15: fd 1e 2f mvfacmi #2, a0, r15
|
||||
18: fd 1f a0 mvfacmi #0, a1, r0
|
||||
1b: fd 1f af mvfacmi #0, a1, r15
|
||||
1e: fd 1f e0 mvfacmi #1, a1, r0
|
||||
21: fd 1f ef mvfacmi #1, a1, r15
|
||||
24: fd 1e a0 mvfacmi #2, a1, r0
|
||||
27: fd 1e af mvfacmi #2, a1, r15
|
||||
|
|
|
|||
|
|
@ -1 +1,7 @@
|
|||
mvfacmi {reg}
|
||||
mvfacmi #0,a0,{reg}
|
||||
mvfacmi #1,a0,{reg}
|
||||
mvfacmi #2,a0,{reg}
|
||||
mvfacmi #0,a1,{reg}
|
||||
mvfacmi #1,a1,{reg}
|
||||
mvfacmi #2,a1,{reg}
|
||||
|
|
|
|||
|
|
@ -22,4 +22,6 @@ Disassembly of section \.text:
|
|||
27: fd 6a 9f mvfc bpc, r15
|
||||
2a: fd 6a b0 mvfc fintv, r0
|
||||
2d: fd 6a bf mvfc fintv, r15
|
||||
30: fd 6a d0 mvfc extb, r0
|
||||
33: fd 6a df mvfc extb, r15
|
||||
|
||||
|
|
|
|||
12
gas/testsuite/gas/rx/mvtacgu.d
Normal file
12
gas/testsuite/gas/rx/mvtacgu.d
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 17 30 mvtacgu r0, a0
|
||||
3: fd 17 3f mvtacgu r15, a0
|
||||
6: fd 17 b0 mvtacgu r0, a1
|
||||
9: fd 17 bf mvtacgu r15, a1
|
||||
2
gas/testsuite/gas/rx/mvtacgu.sm
Normal file
2
gas/testsuite/gas/rx/mvtacgu.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
mvtacgu {reg},a0
|
||||
mvtacgu {reg},a1
|
||||
|
|
@ -6,5 +6,9 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 17 00 mvtachi r0
|
||||
3: fd 17 0f mvtachi r15
|
||||
0: fd 17 00 mvtachi r0, a0
|
||||
3: fd 17 0f mvtachi r15, a0
|
||||
6: fd 17 00 mvtachi r0, a0
|
||||
9: fd 17 0f mvtachi r15, a0
|
||||
c: fd 17 80 mvtachi r0, a1
|
||||
f: fd 17 8f mvtachi r15, a1
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
mvtachi {reg}
|
||||
mvtachi {reg},a0
|
||||
mvtachi {reg},a1
|
||||
|
|
|
|||
|
|
@ -6,5 +6,9 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 17 10 mvtaclo r0
|
||||
3: fd 17 1f mvtaclo r15
|
||||
0: fd 17 10 mvtaclo r0, a0
|
||||
3: fd 17 1f mvtaclo r15, a0
|
||||
6: fd 17 10 mvtaclo r0, a0
|
||||
9: fd 17 1f mvtaclo r15, a0
|
||||
c: fd 17 90 mvtaclo r0, a1
|
||||
f: fd 17 9f mvtaclo r15, a1
|
||||
|
|
|
|||
|
|
@ -1 +1,3 @@
|
|||
mvtaclo {reg}
|
||||
mvtaclo {reg},a0
|
||||
mvtaclo {reg},a1
|
||||
|
|
|
|||
|
|
@ -14,14 +14,16 @@ Disassembly of section \.text:
|
|||
14: fd 77 08 80 mvtc #-128, bpsw
|
||||
18: fd 77 09 80 mvtc #-128, bpc
|
||||
1c: fd 77 0b 80 mvtc #-128, fintv
|
||||
20: fd 77 00 7f mvtc #127, psw
|
||||
24: fd 77 03 7f mvtc #127, fpsw
|
||||
28: fd 77 02 7f mvtc #127, usp
|
||||
2c: fd 77 0a 7f mvtc #127, isp
|
||||
30: fd 77 0c 7f mvtc #127, intb
|
||||
34: fd 77 08 7f mvtc #127, bpsw
|
||||
38: fd 77 09 7f mvtc #127, bpc
|
||||
3c: fd 77 0b 7f mvtc #127, fintv
|
||||
20: fd 77 0d 80 mvtc #-128, extb
|
||||
24: fd 77 00 7f mvtc #127, psw
|
||||
28: fd 77 03 7f mvtc #127, fpsw
|
||||
2c: fd 77 02 7f mvtc #127, usp
|
||||
30: fd 77 0a 7f mvtc #127, isp
|
||||
34: fd 77 0c 7f mvtc #127, intb
|
||||
38: fd 77 08 7f mvtc #127, bpsw
|
||||
3c: fd 77 09 7f mvtc #127, bpc
|
||||
40: fd 77 0b 7f mvtc #127, fintv
|
||||
44: fd 77 0d 7f mvtc #127, extb
|
||||
..: fd 7b 00 00 80 mvtc #0xffff8000, psw
|
||||
..: fd 7b 03 00 80 mvtc #0xffff8000, fpsw
|
||||
..: fd 7b 02 00 80 mvtc #0xffff8000, usp
|
||||
|
|
@ -30,6 +32,7 @@ Disassembly of section \.text:
|
|||
..: fd 7b 08 00 80 mvtc #0xffff8000, bpsw
|
||||
..: fd 7b 09 00 80 mvtc #0xffff8000, bpc
|
||||
..: fd 7b 0b 00 80 mvtc #0xffff8000, fintv
|
||||
..: fd 7b 0d 00 80 mvtc #0xffff8000, extb
|
||||
..: fd 7f 00 00 80 00 mvtc #0x8000, psw
|
||||
..: fd 7f 03 00 80 00 mvtc #0x8000, fpsw
|
||||
..: fd 7f 02 00 80 00 mvtc #0x8000, usp
|
||||
|
|
@ -38,6 +41,7 @@ Disassembly of section \.text:
|
|||
..: fd 7f 08 00 80 00 mvtc #0x8000, bpsw
|
||||
..: fd 7f 09 00 80 00 mvtc #0x8000, bpc
|
||||
..: fd 7f 0b 00 80 00 mvtc #0x8000, fintv
|
||||
..: fd 7f 0d 00 80 00 mvtc #0x8000, extb
|
||||
..: fd 7f 00 00 00 80 mvtc #0xff800000, psw
|
||||
..: fd 7f 03 00 00 80 mvtc #0xff800000, fpsw
|
||||
..: fd 7f 02 00 00 80 mvtc #0xff800000, usp
|
||||
|
|
@ -46,14 +50,16 @@ Disassembly of section \.text:
|
|||
..: fd 7f 08 00 00 80 mvtc #0xff800000, bpsw
|
||||
..: fd 7f 09 00 00 80 mvtc #0xff800000, bpc
|
||||
..: fd 7f 0b 00 00 80 mvtc #0xff800000, fintv
|
||||
..: fd 7f 0d 00 00 80 mvtc #0xff800000, extb
|
||||
..: fd 7f 00 ff ff 7f mvtc #0x7fffff, psw
|
||||
..: fd 7f 03 ff ff 7f mvtc #0x7fffff, fpsw
|
||||
..: fd 7f 02 ff ff 7f mvtc #0x7fffff, usp
|
||||
..: fd 7f 0a ff ff 7f mvtc #0x7fffff, isp
|
||||
..: fd 7f 0c ff ff 7f mvtc #0x7fffff, intb
|
||||
..: fd 7f 08 ff ff 7f mvtc #0x7fffff, bpsw
|
||||
...: fd 7f 08 ff ff 7f mvtc #0x7fffff, bpsw
|
||||
...: fd 7f 09 ff ff 7f mvtc #0x7fffff, bpc
|
||||
...: fd 7f 0b ff ff 7f mvtc #0x7fffff, fintv
|
||||
...: fd 7f 0d ff ff 7f mvtc #0x7fffff, extb
|
||||
...: fd 73 00 00 00 00 80 mvtc #0x80000000, psw
|
||||
...: fd 73 03 00 00 00 80 mvtc #0x80000000, fpsw
|
||||
...: fd 73 02 00 00 00 80 mvtc #0x80000000, usp
|
||||
|
|
@ -62,6 +68,7 @@ Disassembly of section \.text:
|
|||
...: fd 73 08 00 00 00 80 mvtc #0x80000000, bpsw
|
||||
...: fd 73 09 00 00 00 80 mvtc #0x80000000, bpc
|
||||
...: fd 73 0b 00 00 00 80 mvtc #0x80000000, fintv
|
||||
...: fd 73 0d 00 00 00 80 mvtc #0x80000000, extb
|
||||
...: fd 73 00 ff ff ff 7f mvtc #0x7fffffff, psw
|
||||
...: fd 73 03 ff ff ff 7f mvtc #0x7fffffff, fpsw
|
||||
...: fd 73 02 ff ff ff 7f mvtc #0x7fffffff, usp
|
||||
|
|
@ -70,6 +77,7 @@ Disassembly of section \.text:
|
|||
...: fd 73 08 ff ff ff 7f mvtc #0x7fffffff, bpsw
|
||||
...: fd 73 09 ff ff ff 7f mvtc #0x7fffffff, bpc
|
||||
...: fd 73 0b ff ff ff 7f mvtc #0x7fffffff, fintv
|
||||
...: fd 73 0d ff ff ff 7f mvtc #0x7fffffff, extb
|
||||
...: fd 68 00 mvtc r0, psw
|
||||
...: fd 68 03 mvtc r0, fpsw
|
||||
...: fd 68 02 mvtc r0, usp
|
||||
|
|
@ -78,6 +86,7 @@ Disassembly of section \.text:
|
|||
...: fd 68 08 mvtc r0, bpsw
|
||||
...: fd 68 09 mvtc r0, bpc
|
||||
...: fd 68 0b mvtc r0, fintv
|
||||
...: fd 68 0d mvtc r0, extb
|
||||
...: fd 68 f0 mvtc r15, psw
|
||||
...: fd 68 f3 mvtc r15, fpsw
|
||||
...: fd 68 f2 mvtc r15, usp
|
||||
|
|
@ -86,4 +95,5 @@ Disassembly of section \.text:
|
|||
...: fd 68 f8 mvtc r15, bpsw
|
||||
...: fd 68 f9 mvtc r15, bpc
|
||||
...: fd 68 fb mvtc r15, fintv
|
||||
...: fd 68 fd mvtc r15, extb
|
||||
|
||||
|
|
|
|||
|
|
@ -3,9 +3,9 @@
|
|||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \..*:
|
||||
Disassembly of section .*:
|
||||
|
||||
00000000 <\..*>:
|
||||
00000000 <.*>:
|
||||
0: 03 nop
|
||||
1: ef 00 nop ; mov.l r0, r0
|
||||
3: 63 10 nop ; mul #1, r0
|
||||
|
|
|
|||
|
|
@ -14,4 +14,5 @@ Disassembly of section \.text:
|
|||
a: 7e e8 popc bpsw
|
||||
c: 7e e9 popc bpc
|
||||
e: 7e eb popc fintv
|
||||
10: 7e ed popc extb
|
||||
|
||||
|
|
|
|||
|
|
@ -14,4 +14,5 @@ Disassembly of section \.text:
|
|||
a: 7e c8 pushc bpsw
|
||||
c: 7e c9 pushc bpc
|
||||
e: 7e cb pushc fintv
|
||||
10: 7e cd pushc extb
|
||||
|
||||
|
|
|
|||
12
gas/testsuite/gas/rx/racl.d
Normal file
12
gas/testsuite/gas/rx/racl.d
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 19 00 racl #1, a0
|
||||
3: fd 19 10 racl #2, a0
|
||||
6: fd 19 80 racl #1, a1
|
||||
9: fd 19 90 racl #2, a1
|
||||
4
gas/testsuite/gas/rx/racl.sm
Normal file
4
gas/testsuite/gas/rx/racl.sm
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
racl #1,a0
|
||||
racl #2,a0
|
||||
racl #1,a1
|
||||
racl #2,a1
|
||||
|
|
@ -6,5 +6,9 @@ dump\.o: file format .*
|
|||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 18 00 racw #1
|
||||
3: fd 18 10 racw #2
|
||||
0: fd 18 00 racw #1, a0
|
||||
3: fd 18 10 racw #2, a0
|
||||
6: fd 18 00 racw #1, a0
|
||||
9: fd 18 10 racw #2, a0
|
||||
c: fd 18 80 racw #1, a1
|
||||
f: fd 18 90 racw #2, a1
|
||||
|
|
|
|||
|
|
@ -1,2 +1,6 @@
|
|||
racw #1
|
||||
racw #2
|
||||
racw #1,a0
|
||||
racw #2,a0
|
||||
racw #1,a1
|
||||
racw #2,a1
|
||||
|
|
|
|||
12
gas/testsuite/gas/rx/rdacl.d
Normal file
12
gas/testsuite/gas/rx/rdacl.d
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 19 40 rdacl #1, a0
|
||||
3: fd 19 50 rdacl #2, a0
|
||||
6: fd 19 c0 rdacl #1, a1
|
||||
9: fd 19 d0 rdacl #2, a1
|
||||
4
gas/testsuite/gas/rx/rdacl.sm
Normal file
4
gas/testsuite/gas/rx/rdacl.sm
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
rdacl #1,a0
|
||||
rdacl #2,a0
|
||||
rdacl #1,a1
|
||||
rdacl #2,a1
|
||||
12
gas/testsuite/gas/rx/rdacw.d
Normal file
12
gas/testsuite/gas/rx/rdacw.d
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fd 18 40 rdacw #1, a0
|
||||
3: fd 18 50 rdacw #2, a0
|
||||
6: fd 18 c0 rdacw #1, a1
|
||||
9: fd 18 d0 rdacw #2, a1
|
||||
4
gas/testsuite/gas/rx/rdacw.sm
Normal file
4
gas/testsuite/gas/rx/rdacw.sm
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
rdacw #1,a0
|
||||
rdacw #2,a0
|
||||
rdacw #1,a1
|
||||
rdacw #2,a1
|
||||
|
|
@ -21,6 +21,9 @@ if { ! [istarget rx-*-*] } {
|
|||
return
|
||||
}
|
||||
|
||||
global ASFLAGS
|
||||
set ASFLAGS "--mcpu=rxv2"
|
||||
|
||||
foreach test [lsort [glob $srcdir/$subdir/*.sm]] {
|
||||
regexp ".*/(.*)\.sm" $test rxjunk rxbase
|
||||
exec "$srcdir/$subdir/explode" "-I" "$srcdir/$subdir" "$test" "$srcdir/$subdir/$rxbase.s"
|
||||
|
|
|
|||
|
|
@ -22,3 +22,7 @@ Disassembly of section \.text:
|
|||
45: fd 70 ff 00 00 00 80 stnz #0x80000000, r15
|
||||
4c: fd 70 f0 ff ff ff 7f stnz #0x7fffffff, r0
|
||||
53: fd 70 ff ff ff ff 7f stnz #0x7fffffff, r15
|
||||
5a: fc 4f 00 stnz r0, r0
|
||||
5d: fc 4f 0f stnz r0, r15
|
||||
60: fc 4f f0 stnz r15, r0
|
||||
63: fc 4f ff stnz r15, r15
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
stnz #{imm},{reg}
|
||||
stnz {reg},{reg}
|
||||
|
|
|
|||
|
|
@ -22,3 +22,7 @@ Disassembly of section \.text:
|
|||
45: fd 70 ef 00 00 00 80 stz #0x80000000, r15
|
||||
4c: fd 70 e0 ff ff ff 7f stz #0x7fffffff, r0
|
||||
53: fd 70 ef ff ff ff 7f stz #0x7fffffff, r15
|
||||
5a: fc 4b 00 stz r0, r0
|
||||
5d: fc 4b 0f stz r0, r15
|
||||
60: fc 4b f0 stz r15, r0
|
||||
63: fc 4b ff stz r15, r15
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
stz #{imm},{reg}
|
||||
stz {reg},{reg}
|
||||
|
|
|
|||
72
gas/testsuite/gas/rx/utof.d
Normal file
72
gas/testsuite/gas/rx/utof.d
Normal file
|
|
@ -0,0 +1,72 @@
|
|||
#objdump: -dr
|
||||
|
||||
dump\.o: file format .*
|
||||
|
||||
|
||||
Disassembly of section \.text:
|
||||
|
||||
00000000 <\.text>:
|
||||
0: fc 57 00 utof r0, r0
|
||||
3: fc 57 0f utof r0, r15
|
||||
6: fc 57 f0 utof r15, r0
|
||||
9: fc 57 ff utof r15, r15
|
||||
c: fc 54 00 utof \[r0\]\.ub, r0
|
||||
f: fc 54 0f utof \[r0\]\.ub, r15
|
||||
12: 06 20 15 00 utof \[r0\]\.b, r0
|
||||
16: 06 20 15 0f utof \[r0\]\.b, r15
|
||||
1a: 06 e0 15 00 utof \[r0\]\.uw, r0
|
||||
1e: 06 e0 15 0f utof \[r0\]\.uw, r15
|
||||
22: 06 60 15 00 utof \[r0\]\.w, r0
|
||||
26: 06 60 15 0f utof \[r0\]\.w, r15
|
||||
2a: 06 a0 15 00 utof \[r0\]\.l, r0
|
||||
2e: 06 a0 15 0f utof \[r0\]\.l, r15
|
||||
32: fc 54 f0 utof \[r15\]\.ub, r0
|
||||
35: fc 54 ff utof \[r15\]\.ub, r15
|
||||
38: 06 20 15 f0 utof \[r15\]\.b, r0
|
||||
3c: 06 20 15 ff utof \[r15\]\.b, r15
|
||||
40: 06 e0 15 f0 utof \[r15\]\.uw, r0
|
||||
44: 06 e0 15 ff utof \[r15\]\.uw, r15
|
||||
48: 06 60 15 f0 utof \[r15\]\.w, r0
|
||||
4c: 06 60 15 ff utof \[r15\]\.w, r15
|
||||
50: 06 a0 15 f0 utof \[r15\]\.l, r0
|
||||
54: 06 a0 15 ff utof \[r15\]\.l, r15
|
||||
58: fc 55 00 fc utof 252\[r0\]\.ub, r0
|
||||
5c: fc 55 0f fc utof 252\[r0\]\.ub, r15
|
||||
60: 06 21 15 00 fc utof 252\[r0\]\.b, r0
|
||||
65: 06 21 15 0f fc utof 252\[r0\]\.b, r15
|
||||
6a: 06 e1 15 00 7e utof 252\[r0\]\.uw, r0
|
||||
6f: 06 e1 15 0f 7e utof 252\[r0\]\.uw, r15
|
||||
74: 06 61 15 00 7e utof 252\[r0\]\.w, r0
|
||||
79: 06 61 15 0f 7e utof 252\[r0\]\.w, r15
|
||||
7e: 06 a1 15 00 3f utof 252\[r0\]\.l, r0
|
||||
83: 06 a1 15 0f 3f utof 252\[r0\]\.l, r15
|
||||
88: fc 55 f0 fc utof 252\[r15\]\.ub, r0
|
||||
8c: fc 55 ff fc utof 252\[r15\]\.ub, r15
|
||||
90: 06 21 15 f0 fc utof 252\[r15\]\.b, r0
|
||||
95: 06 21 15 ff fc utof 252\[r15\]\.b, r15
|
||||
9a: 06 e1 15 f0 7e utof 252\[r15\]\.uw, r0
|
||||
9f: 06 e1 15 ff 7e utof 252\[r15\]\.uw, r15
|
||||
a4: 06 61 15 f0 7e utof 252\[r15\]\.w, r0
|
||||
a9: 06 61 15 ff 7e utof 252\[r15\]\.w, r15
|
||||
ae: 06 a1 15 f0 3f utof 252\[r15\]\.l, r0
|
||||
b3: 06 a1 15 ff 3f utof 252\[r15\]\.l, r15
|
||||
b8: fc 56 00 fc ff utof 65532\[r0\]\.ub, r0
|
||||
bd: fc 56 0f fc ff utof 65532\[r0\]\.ub, r15
|
||||
c2: 06 22 15 00 fc ff utof 65532\[r0\]\.b, r0
|
||||
c8: 06 22 15 0f fc ff utof 65532\[r0\]\.b, r15
|
||||
ce: 06 e2 15 00 fe 7f utof 65532\[r0\]\.uw, r0
|
||||
d4: 06 e2 15 0f fe 7f utof 65532\[r0\]\.uw, r15
|
||||
da: 06 62 15 00 fe 7f utof 65532\[r0\]\.w, r0
|
||||
e0: 06 62 15 0f fe 7f utof 65532\[r0\]\.w, r15
|
||||
e6: 06 a2 15 00 ff 3f utof 65532\[r0\]\.l, r0
|
||||
ec: 06 a2 15 0f ff 3f utof 65532\[r0\]\.l, r15
|
||||
f2: fc 56 f0 fc ff utof 65532\[r15\]\.ub, r0
|
||||
f7: fc 56 ff fc ff utof 65532\[r15\]\.ub, r15
|
||||
fc: 06 22 15 f0 fc ff utof 65532\[r15\]\.b, r0
|
||||
102: 06 22 15 ff fc ff utof 65532\[r15\]\.b, r15
|
||||
108: 06 e2 15 f0 fe 7f utof 65532\[r15\]\.uw, r0
|
||||
10e: 06 e2 15 ff fe 7f utof 65532\[r15\]\.uw, r15
|
||||
114: 06 62 15 f0 fe 7f utof 65532\[r15\]\.w, r0
|
||||
11a: 06 62 15 ff fe 7f utof 65532\[r15\]\.w, r15
|
||||
120: 06 a2 15 f0 ff 3f utof 65532\[r15\]\.l, r0
|
||||
126: 06 a2 15 ff ff 3f utof 65532\[r15\]\.l, r15
|
||||
2
gas/testsuite/gas/rx/utof.sm
Normal file
2
gas/testsuite/gas/rx/utof.sm
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
utof {reg},{reg}
|
||||
utof {memx},{reg}
|
||||
|
|
@ -1,3 +1,7 @@
|
|||
2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
|
||||
|
||||
* rx.h (E_FLAG_RX_V2): New RXv2 type.
|
||||
|
||||
2015-12-07 Alan Modra <amodra@gmail.com>
|
||||
|
||||
* ppc64.h (R_PPC64_ENTRY): Define.
|
||||
|
|
|
|||
|
|
@ -119,11 +119,11 @@ END_RELOC_NUMBERS (R_RX_max)
|
|||
#define E_FLAG_RX_DSP (1 << 1) /* Defined in the RX CPU Object file specification, but not explained. */
|
||||
#define E_FLAG_RX_PID (1 << 2) /* Unofficial - DJ */
|
||||
#define E_FLAG_RX_ABI (1 << 3) /* Binary passes stacked arguments using natural alignment. Unofficial - NC. */
|
||||
|
||||
#define E_FLAG_RX_SINSNS_SET (1 << 6) /* Set if bit-5 is significant. */
|
||||
#define E_FLAG_RX_SINSNS_YES (1 << 7) /* Set if string instructions are used in the binary. */
|
||||
#define E_FLAG_RX_SINSNS_NO 0 /* Bit-5 if this binary must not be linked with a string instruction using binary. */
|
||||
#define E_FLAG_RX_SINSNS_MASK (3 << 6) /* Mask of bits used to determine string instruction use. */
|
||||
#define E_FLAG_RX_V2 (1 << 8) /* RX v2 instructions */
|
||||
|
||||
/* These define the addend field of R_RX_RH_RELAX relocations. */
|
||||
#define RX_RELAXA_IMM6 0x00000010 /* Imm8/16/24/32 at bit offset 6. */
|
||||
|
|
|
|||
|
|
@ -3,6 +3,10 @@
|
|||
* aarch64.h (enum aarch64_opnd_qualifier): Add
|
||||
AARCH64_OPND_QLF_V_2H.
|
||||
|
||||
2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
|
||||
|
||||
* rx.h: Add new instructions.
|
||||
|
||||
2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
|
||||
|
||||
* aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
|
||||
|
|
|
|||
|
|
@ -161,6 +161,25 @@ typedef enum
|
|||
RXO_wait,
|
||||
|
||||
RXO_sccnd, /* d = cond(s) ? 1 : 0 */
|
||||
|
||||
RXO_fsqrt,
|
||||
RXO_ftou,
|
||||
RXO_utof,
|
||||
RXO_movco,
|
||||
RXO_movli,
|
||||
RXO_emaca,
|
||||
RXO_emsba,
|
||||
RXO_emula,
|
||||
RXO_maclh,
|
||||
RXO_msbhi,
|
||||
RXO_msblh,
|
||||
RXO_msblo,
|
||||
RXO_mullh,
|
||||
RXO_mvfacgu,
|
||||
RXO_mvtacgu,
|
||||
RXO_racl,
|
||||
RXO_rdacl,
|
||||
RXO_rdacw,
|
||||
} RX_Opcode_ID;
|
||||
|
||||
/* Condition bitpatterns, as registers. */
|
||||
|
|
|
|||
|
|
@ -1,3 +1,9 @@
|
|||
2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
|
||||
|
||||
* rx-deocde.opc: Add new instructions pattern.
|
||||
* rx-deocde.c: Regenerate.
|
||||
* rx-dis.c (register_name): Add new register.
|
||||
|
||||
2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
|
||||
|
||||
* aarch64-asm-2.c: Regenerate.
|
||||
|
|
|
|||
4021
opcodes/rx-decode.c
4021
opcodes/rx-decode.c
File diff suppressed because it is too large
Load diff
|
|
@ -844,35 +844,35 @@ rx_decode_opcode (unsigned long pc AU,
|
|||
/*----------------------------------------------------------------------*/
|
||||
/* HI/LO stuff */
|
||||
|
||||
/** 1111 1101 0000 0000 srca srcb mulhi %1, %2 */
|
||||
ID(mulhi); SR(srca); S2R(srcb); F_____;
|
||||
/** 1111 1101 0000 a000 srca srcb mulhi %1, %2, %0 */
|
||||
ID(mulhi); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0000 0001 srca srcb mullo %1, %2 */
|
||||
ID(mullo); SR(srca); S2R(srcb); F_____;
|
||||
/** 1111 1101 0000 a001 srca srcb mullo %1, %2, %0 */
|
||||
ID(mullo); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0000 0100 srca srcb machi %1, %2 */
|
||||
ID(machi); SR(srca); S2R(srcb); F_____;
|
||||
/** 1111 1101 0000 a100 srca srcb machi %1, %2, %0 */
|
||||
ID(machi); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0000 0101 srca srcb maclo %1, %2 */
|
||||
ID(maclo); SR(srca); S2R(srcb); F_____;
|
||||
/** 1111 1101 0000 a101 srca srcb maclo %1, %2, %0 */
|
||||
ID(maclo); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0001 0111 0000 rsrc mvtachi %1 */
|
||||
ID(mvtachi); SR(rsrc); F_____;
|
||||
/** 1111 1101 0001 0111 a000 rsrc mvtachi %1, %0 */
|
||||
ID(mvtachi); DR(a+32); SR(rsrc); F_____;
|
||||
|
||||
/** 1111 1101 0001 0111 0001 rsrc mvtaclo %1 */
|
||||
ID(mvtaclo); SR(rsrc); F_____;
|
||||
/** 1111 1101 0001 0111 a001 rsrc mvtaclo %1, %0 */
|
||||
ID(mvtaclo); DR(a+32); SR(rsrc); F_____;
|
||||
|
||||
/** 1111 1101 0001 1111 0000 rdst mvfachi %0 */
|
||||
ID(mvfachi); DR(rdst); F_____;
|
||||
/** 1111 1101 0001 111i a m00 rdst mvfachi #%2, %1, %0 */
|
||||
ID(mvfachi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1101 0001 1111 0010 rdst mvfacmi %0 */
|
||||
ID(mvfacmi); DR(rdst); F_____;
|
||||
/** 1111 1101 0001 111i a m10 rdst mvfacmi #%2, %1, %0 */
|
||||
ID(mvfacmi); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1101 0001 1111 0001 rdst mvfaclo %0 */
|
||||
ID(mvfaclo); DR(rdst); F_____;
|
||||
/** 1111 1101 0001 111i a m01 rdst mvfaclo #%2, %1, %0 */
|
||||
ID(mvfaclo); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1101 0001 1000 000i 0000 racw #%1 */
|
||||
ID(racw); SC(i+1); F_____;
|
||||
/** 1111 1101 0001 1000 a00i 0000 racw #%1, %0 */
|
||||
ID(racw); SC(i+1); DR(a+32); F_____;
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* SAT */
|
||||
|
|
@ -1039,6 +1039,81 @@ rx_decode_opcode (unsigned long pc AU,
|
|||
/** 1111 1100 1101 sz sd rdst cond sc%1%s %0 */
|
||||
ID(sccnd); BWL(sz); DD (sd, rdst, sz); Scc(cond);
|
||||
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* RXv2 enhanced */
|
||||
|
||||
/** 1111 1101 0010 0111 rdst rsrc movco %1, [%0] */
|
||||
ID(mov); SR(rsrc); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1101 0010 1111 rsrc rdst movli [%1], %0 */
|
||||
ID(mov); SR(rsrc); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1100 0100 1011 rsrc rdst stz %1, %0 */
|
||||
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
|
||||
|
||||
/** 1111 1100 0100 1111 rsrc rdst stnz %1, %0 */
|
||||
ID(stcc); SR(rsrc); DR(rdst); S2cc(RXC_z);
|
||||
|
||||
/** 1111 1101 0000 a111 srca srcb emaca %1, %2, %0 */
|
||||
ID(emaca); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0100 a111 srca srcb emsba %1, %2, %0 */
|
||||
ID(emsba); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0000 a011 srca srcb emula %1, %2, %0 */
|
||||
ID(emula); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0000 a110 srca srcb maclh %1, %2, %0 */
|
||||
ID(maclh); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0100 a100 srca srcb msbhi %1, %2, %0 */
|
||||
ID(msbhi); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0100 a110 srca srcb msblh %1, %2, %0 */
|
||||
ID(msblh); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0100 a101 srca srcb msblo %1, %2, %0 */
|
||||
ID(msblo); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0000 a010 srca srcb mullh %1, %2, %0 */
|
||||
ID(mullh); DR(a+32); SR(srca); S2R(srcb); F_____;
|
||||
|
||||
/** 1111 1101 0001 111i a m11 rdst mvfacgu #%2, %1, %0 */
|
||||
ID(mvfacgu); S2C(((i^1)<<1)|m); SR(a+32); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1101 0001 0111 a011 rdst mvtacgu %0, %1 */
|
||||
ID(mvtacgu); SR(a+32); DR(rdst); F_____;
|
||||
|
||||
/** 1111 1101 0001 1001 a00i 0000 racl #%1, %0 */
|
||||
ID(racl); SC(i+1); DR(a+32); F_____;
|
||||
|
||||
/** 1111 1101 0001 1001 a10i 0000 rdacl #%1, %0 */
|
||||
ID(rdacl); SC(i+1); DR(a+32); F_____;
|
||||
|
||||
/** 1111 1101 0001 1000 a10i 0000 rdacw #%1, %0 */
|
||||
ID(rdacw); SC(i+1); DR(a+32); F_____;
|
||||
|
||||
/** 1111 1111 1010 rdst srca srcb fadd %2, %1, %0 */
|
||||
ID(fadd); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
|
||||
|
||||
/** 1111 1111 1000 rdst srca srcb fsub %2, %1, %0 */
|
||||
ID(fsub); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
|
||||
|
||||
/** 1111 1111 1011 rdst srca srcb fmul %2, %1, %0 */
|
||||
ID(fmul); DR(rdst); SR(srcb); S2R(srca); F__SZ_;
|
||||
|
||||
/** 1111 1100 1010 00sd rsrc rdst fsqrt %1%S1, %0 */
|
||||
ID(fsqrt); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
|
||||
|
||||
/** 1111 1100 1010 01sd rsrc rdst ftou %1%S1, %0 */
|
||||
ID(ftou); DR(rdst); SD(sd, rsrc, LSIZE); F__SZ_;
|
||||
|
||||
/** 1111 1100 0101 01sd rsrc rdst utof %1%S1, %0 */
|
||||
ID(utof); DR (rdst); SP(sd, rsrc); F__SZ_;
|
||||
|
||||
/** 0000 0110 mx10 00sd 0001 0101 rsrc rdst utof %1%S1, %0 */
|
||||
ID(utof); DR (rdst); SPm(sd, rsrc, mx); F__SZ_;
|
||||
|
||||
/** */
|
||||
|
||||
return rx->n_bytes;
|
||||
|
|
|
|||
|
|
@ -65,9 +65,9 @@ static char const * register_names[] =
|
|||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
|
||||
/* control register */
|
||||
"psw", "pc", "usp", "fpsw", NULL, NULL, NULL, NULL,
|
||||
"bpsw", "bpc", "isp", "fintv", "intb", NULL, NULL, NULL,
|
||||
"bpsw", "bpc", "isp", "fintv", "intb", "extb", NULL, NULL,
|
||||
"a0", "a1", NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
|
||||
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL
|
||||
};
|
||||
|
||||
static char const * condition_names[] =
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue