gdb/ChangeLog:
2004-07-20 Jim Blandy <jimb@redhat.com> Use a fixed register numbering when communicating with the PowerPC simulator. * ppc-tdep.h (struct gdbarch_tdep): New member: 'sim_regno'. * rs6000-tdep.c: #include "sim-regno.h" and "gdb/sim-ppc.h". (set_sim_regno, init_sim_regno_table, rs6000_register_sim_regno): New functions. (rs6000_gdbarch_init): Register rs6000_register_sim_regno. Call init_sim_regno_table. * Makefile.in (gdb_sim_ppc_h): New variable. (rs6000-tdep.o): Update dependencies. include/gdb/ChangeLog: 2004-07-20 Jim Blandy <jimb@redhat.com> * sim-ppc.h: New file. sim/ppc/ChangeLog: 2004-07-20 Jim Blandy <jimb@redhat.com> Use a fixed register numbering when communicating with the PowerPC simulator. * sim_calls.c: #include "registers.h" and "gdb/sim-ppc.h"; do not include GDB's "defs.h". (gdb_register_name_table): New variable. (gdb_register_name_table_size): New enum constant. (gdb_register_name): New function. (sim_fetch_register, sim_store_register): Use gdb_register_name, instead of calling gdbarch_register_name. * Makefile.in (GDB_SIM_PPC_H): New variable. (DEFS_H): Delete variable. (sim_calls.o): Update dependencies.
This commit is contained in:
Jim Blandy
parent
df4a695802
commit
9f64376872
8 changed files with 485 additions and 39 deletions
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@ -1,3 +1,16 @@
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2004-08-04 Jim Blandy <jimb@redhat.com>
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Use a fixed register numbering when communicating with the PowerPC
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simulator.
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* ppc-tdep.h (struct gdbarch_tdep): New member: 'sim_regno'.
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* rs6000-tdep.c: #include "sim-regno.h" and "gdb/sim-ppc.h".
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(set_sim_regno, init_sim_regno_table, rs6000_register_sim_regno):
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New functions.
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(rs6000_gdbarch_init): Register rs6000_register_sim_regno. Call
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init_sim_regno_table.
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* Makefile.in (gdb_sim_ppc_h): New variable.
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(rs6000-tdep.o): Update dependencies.
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2004-08-02 Andrew Cagney <cagney@gnu.org>
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* cris-tdep.c (cris_register_size): Restore function, still used
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@ -593,6 +593,7 @@ gdb_callback_h = $(INCLUDE_DIR)/gdb/callback.h
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gdb_sim_arm_h = $(INCLUDE_DIR)/gdb/sim-arm.h
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gdb_sim_d10v_h = $(INCLUDE_DIR)/gdb/sim-d10v.h
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gdb_sim_frv_h = $(INCLUDE_DIR)/gdb/sim-frv.h
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gdb_sim_ppc_h = $(INCLUDE_DIR)/gdb/sim-ppc.h
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gdb_sim_sh_h = $(INCLUDE_DIR)/gdb/sim-sh.h
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splay_tree_h = $(INCLUDE_DIR)/splay-tree.h
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hashtab_h = $(INCLUDE_DIR)/hashtab.h
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@ -2400,7 +2401,8 @@ rs6000-tdep.o: rs6000-tdep.c $(defs_h) $(frame_h) $(inferior_h) $(symtab_h) \
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$(osabi_h) $(libbfd_h) $(coff_internal_h) $(libcoff_h) \
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$(coff_xcoff_h) $(libxcoff_h) $(elf_bfd_h) $(solib_svr4_h) \
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$(ppc_tdep_h) $(gdb_assert_h) $(dis_asm_h) $(trad_frame_h) \
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$(frame_unwind_h) $(frame_base_h) $(infcall_h)
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$(frame_unwind_h) $(frame_base_h) $(infcall_h) $(sim_regno_h) \
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$(gdb_sim_ppc_h)
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s390-nat.o: s390-nat.c $(defs_h) $(tm_h) $(regcache_h) $(inferior_h) \
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$(s390_tdep_h)
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s390-tdep.o: s390-tdep.c $(defs_h) $(arch_utils_h) $(frame_h) $(inferior_h) \
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@ -171,6 +171,11 @@ struct gdbarch_tdep
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int ppc_spefscr_regnum; /* SPE 'spefscr' register */
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int lr_frame_offset; /* Offset to ABI specific location where
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link register is saved. */
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/* An array of integers, such that sim_regno[I] is the simulator
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register number for GDB register number I, or -1 if the
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simulator does not implement that register. */
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int *sim_regno;
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};
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@ -37,6 +37,8 @@
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#include "parser-defs.h"
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#include "osabi.h"
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#include "infcall.h"
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#include "sim-regno.h"
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#include "gdb/sim-ppc.h"
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#include "libbfd.h" /* for bfd_default_set_arch_mach */
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#include "coff/internal.h" /* for libcoff.h */
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@ -182,6 +184,106 @@ ppc_floating_point_unit_p (struct gdbarch *gdbarch)
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return (tdep->ppc_fp0_regnum >= 0
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&& tdep->ppc_fpscr_regnum >= 0);
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}
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static void
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set_sim_regno (int *table, int gdb_regno, int sim_regno)
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{
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/* Make sure we don't try to assign any given GDB register a sim
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register number more than once. */
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gdb_assert (table[gdb_regno] == -1);
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table[gdb_regno] = sim_regno;
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}
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static void
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init_sim_regno_table (struct gdbarch *arch)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
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int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
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const struct reg *regs = tdep->regs;
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int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
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int i;
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/* Presume that all registers not explicitly mentioned below are
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unavailable from the sim. */
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for (i = 0; i < total_regs; i++)
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sim_regno[i] = -1;
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/* General-purpose registers. */
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for (i = 0; i < ppc_num_gprs; i++)
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set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
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/* Floating-point registers. */
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if (tdep->ppc_fp0_regnum >= 0)
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for (i = 0; i < ppc_num_fprs; i++)
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set_sim_regno (sim_regno,
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tdep->ppc_fp0_regnum + i,
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sim_ppc_f0_regnum + i);
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if (tdep->ppc_fpscr_regnum >= 0)
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set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
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set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
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set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
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set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
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/* Segment registers. */
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if (tdep->ppc_sr0_regnum >= 0)
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for (i = 0; i < ppc_num_srs; i++)
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set_sim_regno (sim_regno,
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tdep->ppc_sr0_regnum + i,
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sim_ppc_sr0_regnum + i);
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/* Altivec registers. */
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if (tdep->ppc_vr0_regnum >= 0)
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{
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for (i = 0; i < ppc_num_vrs; i++)
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set_sim_regno (sim_regno,
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tdep->ppc_vr0_regnum + i,
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sim_ppc_vr0_regnum + i);
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/* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
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we can treat this more like the other cases. */
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set_sim_regno (sim_regno,
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tdep->ppc_vr0_regnum + ppc_num_vrs,
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sim_ppc_vscr_regnum);
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}
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/* vsave is a special-purpose register, so the code below handles it. */
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/* SPE APU (E500) registers. */
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if (tdep->ppc_ev0_regnum >= 0)
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for (i = 0; i < ppc_num_gprs; i++)
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set_sim_regno (sim_regno,
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tdep->ppc_ev0_regnum + i,
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sim_ppc_ev0_regnum + i);
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if (tdep->ppc_acc_regnum >= 0)
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set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
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/* spefscr is a special-purpose register, so the code below handles it. */
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/* Now handle all special-purpose registers. Verify that they
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haven't mistakenly been assigned numbers by any of the above
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code). */
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for (i = 0; i < total_regs; i++)
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if (regs[i].spr_num >= 0)
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set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
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/* Drop the initialized array into place. */
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tdep->sim_regno = sim_regno;
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}
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static int
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rs6000_register_sim_regno (int reg)
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{
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struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
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int sim_regno;
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gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
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sim_regno = tdep->sim_regno[reg];
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if (sim_regno >= 0)
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return sim_regno;
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else
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return LEGACY_SIM_REGNO_IGNORE;
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}
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/* Register set support functions. */
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@ -2911,6 +3013,7 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_pc_regnum (gdbarch, 64);
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set_gdbarch_sp_regnum (gdbarch, 1);
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set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
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set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
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if (sysv_abi && wordsize == 8)
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set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
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else if (sysv_abi && wordsize == 4)
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@ -3106,6 +3209,8 @@ rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
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set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
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}
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init_sim_regno_table (gdbarch);
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return gdbarch;
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}
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254
include/gdb/sim-ppc.h
Normal file
254
include/gdb/sim-ppc.h
Normal file
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@ -0,0 +1,254 @@
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/* sim-ppc.h --- interface between PowerPC simulator and GDB.
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Copyright 2004 Free Software Foundation, Inc.
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Contributed by Red Hat.
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This file is part of GDB.
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
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02111-1307, USA. */
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#if !defined (SIM_PPC_H)
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#define SIM_PPC_H
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/* The register access functions, sim_fetch_register and
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sim_store_register, use the following numbering for PowerPC
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registers. */
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enum sim_ppc_regnum
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{
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/* General-purpose registers, r0 -- r31. */
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sim_ppc_r0_regnum,
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sim_ppc_r1_regnum,
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sim_ppc_r2_regnum,
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sim_ppc_r3_regnum,
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sim_ppc_r4_regnum,
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sim_ppc_r5_regnum,
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sim_ppc_r6_regnum,
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sim_ppc_r7_regnum,
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sim_ppc_r8_regnum,
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sim_ppc_r9_regnum,
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sim_ppc_r10_regnum,
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sim_ppc_r11_regnum,
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sim_ppc_r12_regnum,
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sim_ppc_r13_regnum,
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sim_ppc_r14_regnum,
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sim_ppc_r15_regnum,
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sim_ppc_r16_regnum,
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sim_ppc_r17_regnum,
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sim_ppc_r18_regnum,
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sim_ppc_r19_regnum,
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sim_ppc_r20_regnum,
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sim_ppc_r21_regnum,
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sim_ppc_r22_regnum,
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sim_ppc_r23_regnum,
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sim_ppc_r24_regnum,
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sim_ppc_r25_regnum,
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sim_ppc_r26_regnum,
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sim_ppc_r27_regnum,
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sim_ppc_r28_regnum,
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sim_ppc_r29_regnum,
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sim_ppc_r30_regnum,
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sim_ppc_r31_regnum,
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/* Floating-point registers, f0 -- f31. */
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sim_ppc_f0_regnum,
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sim_ppc_f1_regnum,
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sim_ppc_f2_regnum,
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sim_ppc_f3_regnum,
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sim_ppc_f4_regnum,
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sim_ppc_f5_regnum,
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sim_ppc_f6_regnum,
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sim_ppc_f7_regnum,
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sim_ppc_f8_regnum,
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sim_ppc_f9_regnum,
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sim_ppc_f10_regnum,
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sim_ppc_f11_regnum,
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sim_ppc_f12_regnum,
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sim_ppc_f13_regnum,
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sim_ppc_f14_regnum,
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sim_ppc_f15_regnum,
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sim_ppc_f16_regnum,
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sim_ppc_f17_regnum,
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sim_ppc_f18_regnum,
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sim_ppc_f19_regnum,
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sim_ppc_f20_regnum,
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sim_ppc_f21_regnum,
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sim_ppc_f22_regnum,
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sim_ppc_f23_regnum,
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sim_ppc_f24_regnum,
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sim_ppc_f25_regnum,
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sim_ppc_f26_regnum,
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sim_ppc_f27_regnum,
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sim_ppc_f28_regnum,
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sim_ppc_f29_regnum,
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sim_ppc_f30_regnum,
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sim_ppc_f31_regnum,
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/* Altivec vector registers, vr0 -- vr31. */
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sim_ppc_vr0_regnum,
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sim_ppc_vr1_regnum,
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sim_ppc_vr2_regnum,
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sim_ppc_vr3_regnum,
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sim_ppc_vr4_regnum,
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sim_ppc_vr5_regnum,
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sim_ppc_vr6_regnum,
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sim_ppc_vr7_regnum,
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sim_ppc_vr8_regnum,
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sim_ppc_vr9_regnum,
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sim_ppc_vr10_regnum,
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sim_ppc_vr11_regnum,
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sim_ppc_vr12_regnum,
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sim_ppc_vr13_regnum,
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sim_ppc_vr14_regnum,
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sim_ppc_vr15_regnum,
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sim_ppc_vr16_regnum,
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sim_ppc_vr17_regnum,
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sim_ppc_vr18_regnum,
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sim_ppc_vr19_regnum,
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sim_ppc_vr20_regnum,
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sim_ppc_vr21_regnum,
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sim_ppc_vr22_regnum,
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sim_ppc_vr23_regnum,
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sim_ppc_vr24_regnum,
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sim_ppc_vr25_regnum,
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sim_ppc_vr26_regnum,
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sim_ppc_vr27_regnum,
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sim_ppc_vr28_regnum,
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sim_ppc_vr29_regnum,
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sim_ppc_vr30_regnum,
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sim_ppc_vr31_regnum,
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/* SPE APU GPR upper halves. These are the upper 32 bits of the
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gprs; there is one upper-half register for each gpr, so it is
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appropriate to use sim_ppc_num_gprs for iterating through
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these. */
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sim_ppc_rh0_regnum,
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sim_ppc_rh1_regnum,
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sim_ppc_rh2_regnum,
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sim_ppc_rh3_regnum,
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sim_ppc_rh4_regnum,
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sim_ppc_rh5_regnum,
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sim_ppc_rh6_regnum,
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sim_ppc_rh7_regnum,
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sim_ppc_rh8_regnum,
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sim_ppc_rh9_regnum,
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sim_ppc_rh10_regnum,
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sim_ppc_rh11_regnum,
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sim_ppc_rh12_regnum,
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sim_ppc_rh13_regnum,
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sim_ppc_rh14_regnum,
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sim_ppc_rh15_regnum,
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sim_ppc_rh16_regnum,
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sim_ppc_rh17_regnum,
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sim_ppc_rh18_regnum,
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sim_ppc_rh19_regnum,
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sim_ppc_rh20_regnum,
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sim_ppc_rh21_regnum,
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sim_ppc_rh22_regnum,
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sim_ppc_rh23_regnum,
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sim_ppc_rh24_regnum,
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sim_ppc_rh25_regnum,
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sim_ppc_rh26_regnum,
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sim_ppc_rh27_regnum,
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sim_ppc_rh28_regnum,
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sim_ppc_rh29_regnum,
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sim_ppc_rh30_regnum,
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sim_ppc_rh31_regnum,
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/* SPE APU GPR full registers. Each of these registers is the
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64-bit concatenation of a 32-bit GPR (providing the lower bits)
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and a 32-bit upper-half register (providing the higher bits).
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As for the upper-half registers, it is appropriate to use
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sim_ppc_num_gprs with these. */
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sim_ppc_ev0_regnum,
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sim_ppc_ev1_regnum,
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sim_ppc_ev2_regnum,
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sim_ppc_ev3_regnum,
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sim_ppc_ev4_regnum,
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sim_ppc_ev5_regnum,
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sim_ppc_ev6_regnum,
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sim_ppc_ev7_regnum,
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sim_ppc_ev8_regnum,
|
||||
sim_ppc_ev9_regnum,
|
||||
sim_ppc_ev10_regnum,
|
||||
sim_ppc_ev11_regnum,
|
||||
sim_ppc_ev12_regnum,
|
||||
sim_ppc_ev13_regnum,
|
||||
sim_ppc_ev14_regnum,
|
||||
sim_ppc_ev15_regnum,
|
||||
sim_ppc_ev16_regnum,
|
||||
sim_ppc_ev17_regnum,
|
||||
sim_ppc_ev18_regnum,
|
||||
sim_ppc_ev19_regnum,
|
||||
sim_ppc_ev20_regnum,
|
||||
sim_ppc_ev21_regnum,
|
||||
sim_ppc_ev22_regnum,
|
||||
sim_ppc_ev23_regnum,
|
||||
sim_ppc_ev24_regnum,
|
||||
sim_ppc_ev25_regnum,
|
||||
sim_ppc_ev26_regnum,
|
||||
sim_ppc_ev27_regnum,
|
||||
sim_ppc_ev28_regnum,
|
||||
sim_ppc_ev29_regnum,
|
||||
sim_ppc_ev30_regnum,
|
||||
sim_ppc_ev31_regnum,
|
||||
|
||||
/* Segment registers, sr0 -- sr15. */
|
||||
sim_ppc_sr0_regnum,
|
||||
sim_ppc_sr1_regnum,
|
||||
sim_ppc_sr2_regnum,
|
||||
sim_ppc_sr3_regnum,
|
||||
sim_ppc_sr4_regnum,
|
||||
sim_ppc_sr5_regnum,
|
||||
sim_ppc_sr6_regnum,
|
||||
sim_ppc_sr7_regnum,
|
||||
sim_ppc_sr8_regnum,
|
||||
sim_ppc_sr9_regnum,
|
||||
sim_ppc_sr10_regnum,
|
||||
sim_ppc_sr11_regnum,
|
||||
sim_ppc_sr12_regnum,
|
||||
sim_ppc_sr13_regnum,
|
||||
sim_ppc_sr14_regnum,
|
||||
sim_ppc_sr15_regnum,
|
||||
|
||||
/* Miscellaneous --- but non-SPR --- registers. */
|
||||
sim_ppc_pc_regnum,
|
||||
sim_ppc_ps_regnum,
|
||||
sim_ppc_cr_regnum,
|
||||
sim_ppc_fpscr_regnum,
|
||||
sim_ppc_acc_regnum,
|
||||
sim_ppc_vscr_regnum,
|
||||
|
||||
/* Special-purpose registers. Each SPR is given a number equal to
|
||||
its number in the ISA --- the number that appears in the mtspr
|
||||
/ mfspr instructions --- plus this constant. */
|
||||
sim_ppc_spr0_regnum
|
||||
};
|
||||
|
||||
|
||||
/* Sizes of various register sets. */
|
||||
enum
|
||||
{
|
||||
sim_ppc_num_gprs = 32,
|
||||
sim_ppc_num_fprs = 32,
|
||||
sim_ppc_num_vrs = 32,
|
||||
sim_ppc_num_srs = 16,
|
||||
sim_ppc_num_sprs = 1024,
|
||||
};
|
||||
|
||||
#endif /* SIM_PPC_H */
|
||||
|
|
@ -1,3 +1,18 @@
|
|||
2004-08-04 Jim Blandy <jimb@redhat.com>
|
||||
|
||||
Use a fixed register numbering when communicating with the PowerPC
|
||||
simulator.
|
||||
* sim_calls.c: #include "registers.h" and "gdb/sim-ppc.h"; do not
|
||||
include GDB's "defs.h".
|
||||
(gdb_register_name_table): New variable.
|
||||
(gdb_register_name_table_size): New enum constant.
|
||||
(gdb_register_name): New function.
|
||||
(sim_fetch_register, sim_store_register): Use gdb_register_name,
|
||||
instead of calling gdbarch_register_name.
|
||||
* Makefile.in (GDB_SIM_PPC_H): New variable.
|
||||
(DEFS_H): Delete variable.
|
||||
(sim_calls.o): Update dependencies.
|
||||
|
||||
2004-07-26 Andrew Cagney <cagney@gnu.org>
|
||||
|
||||
Problem from Olaf Hering <olh@suse.de>.
|
||||
|
|
|
|||
|
|
@ -172,9 +172,9 @@ all: run $(TARGETLIB) $(GDB_OBJ)
|
|||
# Headers outside sim/ppc.
|
||||
ANSIDECL_H = $(srcroot)/include/ansidecl.h
|
||||
BFD_H = ../../bfd/bfd.h
|
||||
DEFS_H = $(srcroot)/gdb/defs.h
|
||||
GDB_CALLBACK_H = $(srcroot)/include/gdb/callback.h
|
||||
GDB_REMOTE_SIM_H = $(srcroot)/include/gdb/remote-sim.h
|
||||
GDB_SIM_PPC_H = $(srcroot)/include/gdb/sim-ppc.h
|
||||
COMMON_SIM_BASE_H = $(srcroot)/sim/common/sim-base.h
|
||||
COMMON_SIM_BASICS_H = $(srcroot)/sim/common/sim-basics.h
|
||||
COMMON_SIM_FPU_H = $(srcroot)/sim/common/sim-fpu.h
|
||||
|
|
@ -597,7 +597,7 @@ model.o: model.c $(CPU_H) $(MON_H)
|
|||
|
||||
events.o: events.c $(BASICS_H) $(EVENTS_H)
|
||||
|
||||
sim_calls.o: sim_calls.c $(PSIM_H) $(OPTIONS_H) $(DEFS_H) $(BFD_H) $(GDB_CALLBACK_H) $(GDB_REMOTE_SIM_H)
|
||||
sim_calls.o: sim_calls.c $(PSIM_H) $(OPTIONS_H) $(REGISTERS_H) $(BFD_H) $(GDB_CALLBACK_H) $(GDB_REMOTE_SIM_H) $(GDB_SIM_PPC_H)
|
||||
|
||||
spreg.o: spreg.c $(BASICS_H) $(SPREG_H)
|
||||
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
|
||||
#include "psim.h"
|
||||
#include "options.h"
|
||||
#include "registers.h"
|
||||
|
||||
#undef printf_filtered /* blow away the mapping */
|
||||
|
||||
|
|
@ -40,10 +41,10 @@
|
|||
#endif
|
||||
#endif
|
||||
|
||||
#include "defs.h"
|
||||
#include "bfd.h"
|
||||
#include "gdb/callback.h"
|
||||
#include "gdb/remote-sim.h"
|
||||
#include "gdb/sim-ppc.h"
|
||||
|
||||
/* Define the rate at which the simulator should poll the host
|
||||
for a quit. */
|
||||
|
|
@ -59,29 +60,6 @@ static psim *simulator;
|
|||
static device *root_device;
|
||||
static host_callback *callbacks;
|
||||
|
||||
/* We use GDB's gdbarch_register_name function to map GDB register
|
||||
numbers onto names, which we can then look up in the register
|
||||
table. Since the `set architecture' command can select a new
|
||||
processor variant at run-time, the meanings of the register numbers
|
||||
can change, so we need to make sure the sim uses the same
|
||||
name/number mapping that GDB uses.
|
||||
|
||||
(We don't use the REGISTER_NAME macro, which is a wrapper for
|
||||
gdbarch_register_name. We #include GDB's "defs.h", which tries to
|
||||
#include GDB's "config.h", but gets ours instead, and REGISTER_NAME
|
||||
ends up not getting defined. Simpler to just use
|
||||
gdbarch_register_name directly.)
|
||||
|
||||
We used to just use the REGISTER_NAMES macro from GDB's
|
||||
target-dependent header files, which expanded into an initializer
|
||||
for an array of strings. That was kind of nice, because it meant
|
||||
that libsim.a had only a compile-time dependency on GDB; using
|
||||
gdbarch_register_name directly means that there are now link-time
|
||||
and run-time dependencies too.
|
||||
|
||||
Perhaps the host_callback structure could provide a function for
|
||||
retrieving register names; that would be cleaner. */
|
||||
|
||||
SIM_DESC
|
||||
sim_open (SIM_OPEN_KIND kind,
|
||||
host_callback *callback,
|
||||
|
|
@ -177,6 +155,82 @@ sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
|
|||
}
|
||||
|
||||
|
||||
/* A table mapping register numbers (as received from GDB) to register
|
||||
names. This table does not handle special-purpose registers: the
|
||||
SPR whose number is N is assigned the register number
|
||||
sim_ppc_spr0_regnum + N. */
|
||||
static const char *gdb_register_name_table[] = {
|
||||
|
||||
/* General-purpose registers: 0 .. 31. */
|
||||
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
|
||||
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
|
||||
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
|
||||
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
|
||||
|
||||
/* Floating-point registers: 32 .. 63. */
|
||||
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
|
||||
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
|
||||
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
|
||||
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
|
||||
|
||||
/* Altivec registers: 64 .. 95. */
|
||||
"vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
|
||||
"vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
|
||||
"vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
|
||||
"vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
|
||||
|
||||
/* SPE APU GPR upper halves: 96 .. 127. */
|
||||
"rh0", "rh1", "rh2", "rh3", "rh4", "rh5", "rh6", "rh7",
|
||||
"rh8", "rh9", "rh10", "rh11", "rh12", "rh13", "rh14", "rh15",
|
||||
"rh16", "rh17", "rh18", "rh19", "rh20", "rh21", "rh22", "rh23",
|
||||
"rh24", "rh25", "rh26", "rh27", "rh28", "rh29", "rh30", "rh31",
|
||||
|
||||
/* SPE APU full 64-bit vector registers: 128 .. 159. */
|
||||
"ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
|
||||
"ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
|
||||
"ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
|
||||
"ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
|
||||
|
||||
/* Segment registers: 160 .. 175. */
|
||||
"sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
|
||||
"sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
|
||||
|
||||
/* Miscellaneous (not special-purpose!) registers: 176 .. 181. */
|
||||
"pc", "ps", "cr", "fpscr", "acc", "vscr"
|
||||
};
|
||||
|
||||
enum {
|
||||
gdb_register_name_table_size = (sizeof (gdb_register_name_table)
|
||||
/ sizeof (gdb_register_name_table[0])),
|
||||
};
|
||||
|
||||
|
||||
/* Return the name of the register whose number is REGNUM, or zero if
|
||||
REGNUM is an invalid register number. */
|
||||
static const char *
|
||||
gdb_register_name (int regnum)
|
||||
{
|
||||
/* Is it a special-purpose register? */
|
||||
if (sim_ppc_spr0_regnum <= regnum
|
||||
&& regnum < sim_ppc_spr0_regnum + sim_ppc_num_sprs)
|
||||
{
|
||||
int spr = regnum - sim_ppc_spr0_regnum;
|
||||
if (spr_is_valid (spr))
|
||||
return spr_name (spr);
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* Is it a valid non-SPR register number? */
|
||||
else if (0 <= regnum && regnum < gdb_register_name_table_size)
|
||||
return gdb_register_name_table[regnum];
|
||||
|
||||
/* Not a valid register number at all. */
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
|
||||
{
|
||||
|
|
@ -186,15 +240,11 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
|
|||
return 0;
|
||||
}
|
||||
|
||||
/* GDB will sometimes ask for the contents of a register named "";
|
||||
we ignore such requests, and leave garbage in *BUF. In GDB
|
||||
terms, the empty string means "the register with this number is
|
||||
not present in the currently selected architecture variant."
|
||||
That's following the kludge we're using for the MIPS processors.
|
||||
But there are loops that just walk through the entire list of
|
||||
names and try to get everything. */
|
||||
regname = gdbarch_register_name (current_gdbarch, regno);
|
||||
if (! regname || regname[0] == '\0')
|
||||
regname = gdb_register_name (regno);
|
||||
|
||||
/* Occasionally, GDB will pass invalid register numbers to us; it
|
||||
wants us to ignore them. */
|
||||
if (! regname)
|
||||
return -1;
|
||||
|
||||
TRACE(trace_gdb, ("sim_fetch_register(regno=%d(%s), buf=0x%lx)\n",
|
||||
|
|
@ -212,9 +262,11 @@ sim_store_register (SIM_DESC sd, int regno, unsigned char *buf, int length)
|
|||
if (simulator == NULL)
|
||||
return 0;
|
||||
|
||||
/* See comments in sim_fetch_register, above. */
|
||||
regname = gdbarch_register_name (current_gdbarch, regno);
|
||||
if (! regname || regname[0] == '\0')
|
||||
regname = gdb_register_name (regno);
|
||||
|
||||
/* Occasionally, GDB will pass invalid register numbers to us; it
|
||||
wants us to ignore them. */
|
||||
if (! regname)
|
||||
return -1;
|
||||
|
||||
TRACE(trace_gdb, ("sim_store_register(regno=%d(%s), buf=0x%lx)\n",
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue