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[AArch64] Support for ARMv8.1a Adv.SIMD instructions

Browse source 
2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

gas/
  * config/tc-aarch64.c (aarch64_features): Add "rdma".
  * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".

gas/testsuite/
  * rdma-directive.d: New.
  * rdma.d: New.
  * rdma.s: New.

include/opcode/
  * aarch64.h (AARCH64_FEATURE_RDMA): New.

opcode/
  * aarch64-tbl.h (aarch64_feature_rdma): New.
  (RDMA): New.
  (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
  * aarch64-asm-2.c: Regenerate.
  * aarch64-dis-2.c: Regenerate.
  * aarch64-opc-2.c: Regenerate.
This commit is contained in:
Matthew Wahab 2015-06-02 12:20:00 +01:00 • committed by Jiong Wang
parent 290806fd94
commit 9e1f0fa7f3
14 changed files with 1628 additions and 1281 deletions
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5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "rdma".
* doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "lor".

2
gas/config/tc-aarch64.c
View file

@ -7401,6 +7401,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"simd", AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
{"pan", AARCH64_FEATURE (AARCH64_FEATURE_PAN, 0)},
{"lor", AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0)},
{"rdma", AARCH64_FEATURE (AARCH64_FEATURE_SIMD
| AARCH64_FEATURE_RDMA, 0)},
{NULL, AARCH64_ARCH_NONE}
};

2
gas/doc/c-aarch64.texi
View file

@ -137,6 +137,8 @@ automatically cause those extensions to be disabled.
@tab Enable Privileged Access Never support.
@item @code{lor} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable Limited Ordering Regions extensions.
@item @code{rdma} @tab ARMv8-A @tab ARMv8-A or later
@tab Enable ARMv8.1 Advanced SIMD extensions. This implies @code{simd}.
@end multitable
@node AArch64 Syntax

6
gas/testsuite/ChangeLog
View file

@ -1,3 +1,9 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* rdma-directive.d: New.
* rdma.d: New.
* rdma.s: New.
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* lor-directive.d: New.

70
gas/testsuite/gas/aarch64/rdma-directive.d Normal file
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@ -0,0 +1,70 @@
#objdump: -dr
#as: --defsym DIRECTIVE=1
#source: rdma.s
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
20: 7e828420 sqrdmlah s0, s1, s2
24: 7e428420 sqrdmlah h0, h1, h2
28: 7e828c20 sqrdmlsh s0, s1, s2
2c: 7e428c20 sqrdmlsh h0, h1, h2
30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
38: 2f62d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[2\]
3c: 2f72d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[3\]
40: 6f42d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[0\]
44: 6f52d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[1\]
48: 6f62d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[2\]
4c: 6f72d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[3\]
50: 2f82d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[0\]
54: 2fa2d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[1\]
58: 2f82d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[2\]
5c: 2fa2d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[3\]
60: 6f82d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[0\]
64: 6fa2d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[1\]
68: 6f82d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[2\]
6c: 6fa2d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[3\]
70: 2f42f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[0\]
74: 2f52f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[1\]
78: 2f62f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[2\]
7c: 2f72f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[3\]
80: 6f42f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[0\]
84: 6f52f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[1\]
88: 6f62f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[2\]
8c: 6f72f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[3\]
90: 2f82f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[0\]
94: 2fa2f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[1\]
98: 2f82f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[2\]
9c: 2fa2f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[3\]
a0: 6f82f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[0\]
a4: 6fa2f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[1\]
a8: 6f82f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[2\]
ac: 6fa2f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[3\]
b0: 7f42d020 sqrdmlah h0, h1, v2\.h\[0\]
b4: 7f52d020 sqrdmlah h0, h1, v2\.h\[1\]
b8: 7f62d020 sqrdmlah h0, h1, v2\.h\[2\]
bc: 7f72d020 sqrdmlah h0, h1, v2\.h\[3\]
c0: 7f82d020 sqrdmlah s0, s1, v2\.s\[0\]
c4: 7fa2d020 sqrdmlah s0, s1, v2\.s\[1\]
c8: 7f82d820 sqrdmlah s0, s1, v2\.s\[2\]
cc: 7fa2d820 sqrdmlah s0, s1, v2\.s\[3\]
d0: 7f42f020 sqrdmlsh h0, h1, v2\.h\[0\]
d4: 7f52f020 sqrdmlsh h0, h1, v2\.h\[1\]
d8: 7f62f020 sqrdmlsh h0, h1, v2\.h\[2\]
dc: 7f72f020 sqrdmlsh h0, h1, v2\.h\[3\]
e0: 7f82f020 sqrdmlsh s0, s1, v2\.s\[0\]
e4: 7fa2f020 sqrdmlsh s0, s1, v2\.s\[1\]
e8: 7f82f820 sqrdmlsh s0, s1, v2\.s\[2\]
ec: 7fa2f820 sqrdmlsh s0, s1, v2\.s\[3\]

69
gas/testsuite/gas/aarch64/rdma.d Normal file
View file

@ -0,0 +1,69 @@
#objdump: -dr
#as: -march=armv8-a+rdma
.*: file format .*
Disassembly of section \.text:
0000000000000000 <.*>:
0: 2e428420 sqrdmlah v0\.4h, v1\.4h, v2\.4h
4: 6e428420 sqrdmlah v0\.8h, v1\.8h, v2\.8h
8: 2e828420 sqrdmlah v0\.2s, v1\.2s, v2\.2s
c: 6e828420 sqrdmlah v0\.4s, v1\.4s, v2\.4s
10: 2e428c20 sqrdmlsh v0\.4h, v1\.4h, v2\.4h
14: 6e428c20 sqrdmlsh v0\.8h, v1\.8h, v2\.8h
18: 2e828c20 sqrdmlsh v0\.2s, v1\.2s, v2\.2s
1c: 6e828c20 sqrdmlsh v0\.4s, v1\.4s, v2\.4s
20: 7e828420 sqrdmlah s0, s1, s2
24: 7e428420 sqrdmlah h0, h1, h2
28: 7e828c20 sqrdmlsh s0, s1, s2
2c: 7e428c20 sqrdmlsh h0, h1, h2
30: 2f42d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[0\]
34: 2f52d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[1\]
38: 2f62d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[2\]
3c: 2f72d020 sqrdmlah v0\.4h, v1\.4h, v2\.h\[3\]
40: 6f42d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[0\]
44: 6f52d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[1\]
48: 6f62d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[2\]
4c: 6f72d020 sqrdmlah v0\.8h, v1\.8h, v2\.h\[3\]
50: 2f82d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[0\]
54: 2fa2d020 sqrdmlah v0\.2s, v1\.2s, v2\.s\[1\]
58: 2f82d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[2\]
5c: 2fa2d820 sqrdmlah v0\.2s, v1\.2s, v2\.s\[3\]
60: 6f82d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[0\]
64: 6fa2d020 sqrdmlah v0\.4s, v1\.4s, v2\.s\[1\]
68: 6f82d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[2\]
6c: 6fa2d820 sqrdmlah v0\.4s, v1\.4s, v2\.s\[3\]
70: 2f42f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[0\]
74: 2f52f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[1\]
78: 2f62f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[2\]
7c: 2f72f020 sqrdmlsh v0\.4h, v1\.4h, v2\.h\[3\]
80: 6f42f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[0\]
84: 6f52f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[1\]
88: 6f62f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[2\]
8c: 6f72f020 sqrdmlsh v0\.8h, v1\.8h, v2\.h\[3\]
90: 2f82f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[0\]
94: 2fa2f020 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[1\]
98: 2f82f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[2\]
9c: 2fa2f820 sqrdmlsh v0\.2s, v1\.2s, v2\.s\[3\]
a0: 6f82f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[0\]
a4: 6fa2f020 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[1\]
a8: 6f82f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[2\]
ac: 6fa2f820 sqrdmlsh v0\.4s, v1\.4s, v2\.s\[3\]
b0: 7f42d020 sqrdmlah h0, h1, v2\.h\[0\]
b4: 7f52d020 sqrdmlah h0, h1, v2\.h\[1\]
b8: 7f62d020 sqrdmlah h0, h1, v2\.h\[2\]
bc: 7f72d020 sqrdmlah h0, h1, v2\.h\[3\]
c0: 7f82d020 sqrdmlah s0, s1, v2\.s\[0\]
c4: 7fa2d020 sqrdmlah s0, s1, v2\.s\[1\]
c8: 7f82d820 sqrdmlah s0, s1, v2\.s\[2\]
cc: 7fa2d820 sqrdmlah s0, s1, v2\.s\[3\]
d0: 7f42f020 sqrdmlsh h0, h1, v2\.h\[0\]
d4: 7f52f020 sqrdmlsh h0, h1, v2\.h\[1\]
d8: 7f62f020 sqrdmlsh h0, h1, v2\.h\[2\]
dc: 7f72f020 sqrdmlsh h0, h1, v2\.h\[3\]
e0: 7f82f020 sqrdmlsh s0, s1, v2\.s\[0\]
e4: 7fa2f020 sqrdmlsh s0, s1, v2\.s\[1\]
e8: 7f82f820 sqrdmlsh s0, s1, v2\.s\[2\]
ec: 7fa2f820 sqrdmlsh s0, s1, v2\.s\[3\]

78
gas/testsuite/gas/aarch64/rdma.s Normal file
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@ -0,0 +1,78 @@
/* rdma.s Test file for AArch64 v8.1 Advanced-SIMD instructions.
Copyright (C) 2012-2015 Free Software Foundation, Inc. Contributed by ARM Ltd.
This file is part of GAS.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the license, or
(at your option) any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; see the file COPYING3. If not,
see <http://www.gnu.org/licenses/>. */
.text
.ifdef DIRECTIVE
.arch_extension rdma
.endif
.macro vect_inst I T
\I v0.\()\T, v1.\()\T, v2.\()\T
.endm
.text
.irp inst, sqrdmlah, sqrdmlsh
.irp type, 4h, 8h, 2s, 4s
vect_inst \inst \type
.endr
.endr
.macro scalar_inst I R
\I \R\()0, \R\()1, \R\()2
.endm
.text
.irp inst, sqrdmlah, sqrdmlsh
.irp reg, s,h
scalar_inst \inst \reg
.endr
.endr
.macro vect_indexed_inst I S T N
\I v0.\S\T, v1.\S\T, v2.\T[\N]
.endm
.text
.irp inst, sqrdmlah, sqrdmlsh
.irp size, 4, 8
.irp index 0,1,2,3
vect_indexed_inst \inst \size h \index
.endr
.endr
.irp size, 2, 4
.irp index 0,1,2,3
vect_indexed_inst \inst \size s \index
.endr
.endr
.endr
.macro scalar_indexed_inst I T N
\I \T\()0, \T\()1, v2.\T[\N]
.endm
.text
.irp inst, sqrdmlah, sqrdmlsh
.irp type h,s
.irp index 0,1,2,3
scalar_indexed_inst \inst \type \index
.endr
.endr
.endr

4
include/opcode/ChangeLog
View file

@ -1,3 +1,7 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_RDMA): New.
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (AARCH64_FEATURE_LOR): New.

1
include/opcode/aarch64.h
View file

@ -41,6 +41,7 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
/* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \

9
opcodes/ChangeLog
View file

@ -1,3 +1,12 @@
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_rdma): New.
(RDMA): New.
(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-tbl.h (aarch64_feature_lor): New.

380
opcodes/aarch64-asm-2.c
View file

@ -61,282 +61,282 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 25: /* cmp */
value = 24; /* --> subs. */
break;
case 139: /* mov */
value = 138; /* --> umov. */
break;
case 141: /* mov */
value = 140; /* --> ins. */
value = 140; /* --> umov. */
break;
case 143: /* mov */
value = 142; /* --> ins. */
break;
case 204: /* mvn */
value = 203; /* --> not. */
case 145: /* mov */
value = 144; /* --> ins. */
break;
case 259: /* mov */
value = 258; /* --> orr. */
case 206: /* mvn */
value = 205; /* --> not. */
break;
case 314: /* sxtl */
value = 313; /* --> sshll. */
case 261: /* mov */
value = 260; /* --> orr. */
break;
case 316: /* sxtl2 */
value = 315; /* --> sshll2. */
case 318: /* sxtl */
value = 317; /* --> sshll. */
break;
case 336: /* uxtl */
value = 335; /* --> ushll. */
case 320: /* sxtl2 */
value = 319; /* --> sshll2. */
break;
case 338: /* uxtl2 */
value = 337; /* --> ushll2. */
case 340: /* uxtl */
value = 339; /* --> ushll. */
break;
case 431: /* mov */
value = 430; /* --> dup. */
case 342: /* uxtl2 */
value = 341; /* --> ushll2. */
break;
case 498: /* sxtw */
case 497: /* sxth */
case 496: /* sxtb */
case 499: /* asr */
case 495: /* sbfx */
case 494: /* sbfiz */
value = 493; /* --> sbfm. */
case 437: /* mov */
value = 436; /* --> dup. */
break;
case 502: /* bfxil */
case 501: /* bfi */
value = 500; /* --> bfm. */
case 506: /* sxtw */
case 505: /* sxth */
case 504: /* sxtb */
case 507: /* asr */
case 503: /* sbfx */
case 502: /* sbfiz */
value = 501; /* --> sbfm. */
break;
case 507: /* uxth */
case 506: /* uxtb */
case 509: /* lsr */
case 508: /* lsl */
case 505: /* ubfx */
case 504: /* ubfiz */
value = 503; /* --> ubfm. */
case 510: /* bfxil */
case 509: /* bfi */
value = 508; /* --> bfm. */
break;
case 527: /* cset */
case 526: /* cinc */
value = 525; /* --> csinc. */
case 515: /* uxth */
case 514: /* uxtb */
case 517: /* lsr */
case 516: /* lsl */
case 513: /* ubfx */
case 512: /* ubfiz */
value = 511; /* --> ubfm. */
break;
case 530: /* csetm */
case 529: /* cinv */
value = 528; /* --> csinv. */
case 535: /* cset */
case 534: /* cinc */
value = 533; /* --> csinc. */
break;
case 532: /* cneg */
value = 531; /* --> csneg. */
case 538: /* csetm */
case 537: /* cinv */
value = 536; /* --> csinv. */
break;
case 557: /* lsl */
value = 556; /* --> lslv. */
case 540: /* cneg */
value = 539; /* --> csneg. */
break;
case 559: /* lsr */
value = 558; /* --> lsrv. */
case 565: /* lsl */
value = 564; /* --> lslv. */
break;
case 561: /* asr */
value = 560; /* --> asrv. */
case 567: /* lsr */
value = 566; /* --> lsrv. */
break;
case 563: /* ror */
value = 562; /* --> rorv. */
case 569: /* asr */
value = 568; /* --> asrv. */
break;
case 573: /* mul */
value = 572; /* --> madd. */
case 571: /* ror */
value = 570; /* --> rorv. */
break;
case 575: /* mneg */
value = 574; /* --> msub. */
case 581: /* mul */
value = 580; /* --> madd. */
break;
case 577: /* smull */
value = 576; /* --> smaddl. */
case 583: /* mneg */
value = 582; /* --> msub. */
break;
case 579: /* smnegl */
value = 578; /* --> smsubl. */
case 585: /* smull */
value = 584; /* --> smaddl. */
break;
case 582: /* umull */
value = 581; /* --> umaddl. */
case 587: /* smnegl */
value = 586; /* --> smsubl. */
break;
case 584: /* umnegl */
value = 583; /* --> umsubl. */
case 590: /* umull */
value = 589; /* --> umaddl. */
break;
case 595: /* ror */
value = 594; /* --> extr. */
case 592: /* umnegl */
value = 591; /* --> umsubl. */
break;
case 752: /* bic */
value = 751; /* --> and. */
case 603: /* ror */
value = 602; /* --> extr. */
break;
case 754: /* mov */
value = 753; /* --> orr. */
case 760: /* bic */
value = 759; /* --> and. */
break;
case 757: /* tst */
value = 756; /* --> ands. */
case 762: /* mov */
value = 761; /* --> orr. */
break;
case 762: /* uxtw */
case 761: /* mov */
value = 760; /* --> orr. */
case 765: /* tst */
value = 764; /* --> ands. */
break;
case 764: /* mvn */
value = 763; /* --> orn. */
case 770: /* uxtw */
case 769: /* mov */
value = 768; /* --> orr. */
break;
case 768: /* tst */
value = 767; /* --> ands. */
case 772: /* mvn */
value = 771; /* --> orn. */
break;
case 894: /* staddb */
value = 798; /* --> ldaddb. */
case 776: /* tst */
value = 775; /* --> ands. */
break;
case 895: /* staddh */
value = 799; /* --> ldaddh. */
case 902: /* staddb */
value = 806; /* --> ldaddb. */
break;
case 896: /* stadd */
value = 800; /* --> ldadd. */
case 903: /* staddh */
value = 807; /* --> ldaddh. */
break;
case 897: /* staddlb */
value = 802; /* --> ldaddlb. */
case 904: /* stadd */
value = 808; /* --> ldadd. */
break;
case 898: /* staddlh */
value = 805; /* --> ldaddlh. */
case 905: /* staddlb */
value = 810; /* --> ldaddlb. */
break;
case 899: /* staddl */
value = 808; /* --> ldaddl. */
case 906: /* staddlh */
value = 813; /* --> ldaddlh. */
break;
case 900: /* stclrb */
value = 810; /* --> ldclrb. */
case 907: /* staddl */
value = 816; /* --> ldaddl. */
break;
case 901: /* stclrh */
value = 811; /* --> ldclrh. */
case 908: /* stclrb */
value = 818; /* --> ldclrb. */
break;
case 902: /* stclr */
value = 812; /* --> ldclr. */
case 909: /* stclrh */
value = 819; /* --> ldclrh. */
break;
case 903: /* stclrlb */
value = 814; /* --> ldclrlb. */
case 910: /* stclr */
value = 820; /* --> ldclr. */
break;
case 904: /* stclrlh */
value = 817; /* --> ldclrlh. */
case 911: /* stclrlb */
value = 822; /* --> ldclrlb. */
break;
case 905: /* stclrl */
value = 820; /* --> ldclrl. */
case 912: /* stclrlh */
value = 825; /* --> ldclrlh. */
break;
case 906: /* steorb */
value = 822; /* --> ldeorb. */
case 913: /* stclrl */
value = 828; /* --> ldclrl. */
break;
case 907: /* steorh */
value = 823; /* --> ldeorh. */
case 914: /* steorb */
value = 830; /* --> ldeorb. */
break;
case 908: /* steor */
value = 824; /* --> ldeor. */
case 915: /* steorh */
value = 831; /* --> ldeorh. */
break;
case 909: /* steorlb */
value = 826; /* --> ldeorlb. */
case 916: /* steor */
value = 832; /* --> ldeor. */
break;
case 910: /* steorlh */
value = 829; /* --> ldeorlh. */
case 917: /* steorlb */
value = 834; /* --> ldeorlb. */
break;
case 911: /* steorl */
value = 832; /* --> ldeorl. */
case 918: /* steorlh */
value = 837; /* --> ldeorlh. */
break;
case 912: /* stsetb */
value = 834; /* --> ldsetb. */
case 919: /* steorl */
value = 840; /* --> ldeorl. */
break;
case 913: /* stseth */
value = 835; /* --> ldseth. */
case 920: /* stsetb */
value = 842; /* --> ldsetb. */
break;
case 914: /* stset */
value = 836; /* --> ldset. */
case 921: /* stseth */
value = 843; /* --> ldseth. */
break;
case 915: /* stsetlb */
value = 838; /* --> ldsetlb. */
case 922: /* stset */
value = 844; /* --> ldset. */
break;
case 916: /* stsetlh */
value = 841; /* --> ldsetlh. */
case 923: /* stsetlb */
value = 846; /* --> ldsetlb. */
break;
case 917: /* stsetl */
value = 844; /* --> ldsetl. */
case 924: /* stsetlh */
value = 849; /* --> ldsetlh. */
break;
case 918: /* stsmaxb */
value = 846; /* --> ldsmaxb. */
case 925: /* stsetl */
value = 852; /* --> ldsetl. */
break;
case 919: /* stsmaxh */
value = 847; /* --> ldsmaxh. */
case 926: /* stsmaxb */
value = 854; /* --> ldsmaxb. */
break;
case 920: /* stsmax */
value = 848; /* --> ldsmax. */
case 927: /* stsmaxh */
value = 855; /* --> ldsmaxh. */
break;
case 921: /* stsmaxlb */
value = 850; /* --> ldsmaxlb. */
case 928: /* stsmax */
value = 856; /* --> ldsmax. */
break;
case 922: /* stsmaxlh */
value = 853; /* --> ldsmaxlh. */
case 929: /* stsmaxlb */
value = 858; /* --> ldsmaxlb. */
break;
case 923: /* stsmaxl */
value = 856; /* --> ldsmaxl. */
case 930: /* stsmaxlh */
value = 861; /* --> ldsmaxlh. */
break;
case 924: /* stsminb */
value = 858; /* --> ldsminb. */
case 931: /* stsmaxl */
value = 864; /* --> ldsmaxl. */
break;
case 925: /* stsminh */
value = 859; /* --> ldsminh. */
case 932: /* stsminb */
value = 866; /* --> ldsminb. */
break;
case 926: /* stsmin */
value = 860; /* --> ldsmin. */
case 933: /* stsminh */
value = 867; /* --> ldsminh. */
break;
case 927: /* stsminlb */
value = 862; /* --> ldsminlb. */
case 934: /* stsmin */
value = 868; /* --> ldsmin. */
break;
case 928: /* stsminlh */
value = 865; /* --> ldsminlh. */
case 935: /* stsminlb */
value = 870; /* --> ldsminlb. */
break;
case 929: /* stsminl */
value = 868; /* --> ldsminl. */
case 936: /* stsminlh */
value = 873; /* --> ldsminlh. */
break;
case 930: /* stumaxb */
value = 870; /* --> ldumaxb. */
case 937: /* stsminl */
value = 876; /* --> ldsminl. */
break;
case 931: /* stumaxh */
value = 871; /* --> ldumaxh. */
case 938: /* stumaxb */
value = 878; /* --> ldumaxb. */
break;
case 932: /* stumax */
value = 872; /* --> ldumax. */
case 939: /* stumaxh */
value = 879; /* --> ldumaxh. */
break;
case 933: /* stumaxlb */
value = 874; /* --> ldumaxlb. */
case 940: /* stumax */
value = 880; /* --> ldumax. */
break;
case 934: /* stumaxlh */
value = 877; /* --> ldumaxlh. */
case 941: /* stumaxlb */
value = 882; /* --> ldumaxlb. */
break;
case 935: /* stumaxl */
value = 880; /* --> ldumaxl. */
case 942: /* stumaxlh */
value = 885; /* --> ldumaxlh. */
break;
case 936: /* stuminb */
value = 882; /* --> lduminb. */
case 943: /* stumaxl */
value = 888; /* --> ldumaxl. */
break;
case 937: /* stuminh */
value = 883; /* --> lduminh. */
case 944: /* stuminb */
value = 890; /* --> lduminb. */
break;
case 938: /* stumin */
value = 884; /* --> ldumin. */
case 945: /* stuminh */
value = 891; /* --> lduminh. */
break;
case 939: /* stuminlb */
value = 886; /* --> lduminlb. */
case 946: /* stumin */
value = 892; /* --> ldumin. */
break;
case 940: /* stuminlh */
value = 889; /* --> lduminlh. */
case 947: /* stuminlb */
value = 894; /* --> lduminlb. */
break;
case 941: /* stuminl */
value = 892; /* --> lduminl. */
case 948: /* stuminlh */
value = 897; /* --> lduminlh. */
break;
case 943: /* mov */
value = 942; /* --> movn. */
case 949: /* stuminl */
value = 900; /* --> lduminl. */
break;
case 945: /* mov */
value = 944; /* --> movz. */
case 951: /* mov */
value = 950; /* --> movn. */
break;
case 956: /* sevl */
case 955: /* sev */
case 954: /* wfi */
case 953: /* wfe */
case 952: /* yield */
case 951: /* nop */
value = 950; /* --> hint. */
case 953: /* mov */
value = 952; /* --> movz. */
break;
case 965: /* tlbi */
case 964: /* ic */
case 963: /* dc */
case 962: /* at */
value = 961; /* --> sys. */
case 964: /* sevl */
case 963: /* sev */
case 962: /* wfi */
case 961: /* wfe */
case 960: /* yield */
case 959: /* nop */
value = 958; /* --> hint. */
break;
case 973: /* tlbi */
case 972: /* ic */
case 971: /* dc */
case 970: /* at */
value = 969; /* --> sys. */
break;
default: return NULL;
}

2160
opcodes/aarch64-dis-2.c
View file

File diff suppressed because it is too large Load diff

110
opcodes/aarch64-opc-2.c
View file

@ -121,73 +121,73 @@ const struct aarch64_operand aarch64_operands[] =
static const unsigned op_enum_table [] =
{
0,
660,
661,
662,
665,
666,
667,
668,
669,
663,
664,
670,
673,
674,
675,
676,
677,
671,
693,
694,
695,
698,
699,
700,
672,
678,
679,
701,
702,
696,
697,
703,
706,
707,
708,
709,
710,
704,
747,
748,
749,
750,
705,
711,
712,
755,
756,
757,
758,
12,
510,
511,
942,
944,
946,
754,
945,
943,
259,
499,
509,
508,
752,
505,
502,
495,
494,
501,
504,
506,
507,
518,
519,
950,
952,
954,
762,
526,
529,
532,
527,
530,
626,
160,
161,
953,
951,
261,
507,
517,
516,
760,
513,
510,
503,
502,
509,
512,
514,
515,
770,
534,
537,
540,
535,
538,
634,
162,
163,
420,
595,
314,
316,
336,
338,
164,
165,
426,
603,
318,
320,
340,
342,
};
/* Given the opcode enumerator OP, return the pointer to the corresponding

13
opcodes/aarch64-tbl.h
View file

@ -1224,6 +1224,8 @@ static const aarch64_feature_set aarch64_feature_lse =
AARCH64_FEATURE (AARCH64_FEATURE_LSE, 0);
static const aarch64_feature_set aarch64_feature_lor =
AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
static const aarch64_feature_set aarch64_feature_rdma =
AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@ -1232,6 +1234,7 @@ static const aarch64_feature_set aarch64_feature_lor =
#define CRC &aarch64_feature_crc
#define LSE &aarch64_feature_lse
#define LOR &aarch64_feature_lor
#define RDMA &aarch64_feature_rdma
struct aarch64_opcode aarch64_opcode_table[] =
{
@ -1361,6 +1364,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"umull", 0x2f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ},
{"umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ},
{"fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, SIMD, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ},
{"sqrdmlah", 0x2f00d000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
{"sqrdmlsh", 0x2f00f000, 0xbf00f400, asimdelem, 0, RDMA, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ},
/* AdvSIMD EXT. */
{"ext", 0x2e000000, 0xbfe0c400, asimdext, 0, SIMD, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ},
/* AdvSIMD modified immediate. */
@ -1547,6 +1552,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"fminp", 0x2ea0f400, 0xbfa0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMESD, F_SIZEQ},
{"bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
{"bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, SIMD, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ},
/* AdvSIMD three same extension. */
{"sqrdmlah", 0x2e008400, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
{"sqrdmlsh", 0x2e008c00, 0xbf20fe00, asimdsame, 0, RDMA, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ},
/* AdvSIMD shift by immediate. */
{"sshr", 0xf000400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
{"ssra", 0xf001400, 0xbf80fc00, asimdshf, 0, SIMD, OP3 (Vd, Vn, IMM_VLSR), QL_VSHIFT, 0},
@ -1607,6 +1615,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"fmls", 0x5f805000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"fmul", 0x5f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, SIMD, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE},
{"sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
{"sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, 0, RDMA, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE},
/* AdvSIMD load/store multiple structures. */
{"st4", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)},
{"st1", 0xc000000, 0xbfff0000, asisdlse, 0, SIMD, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)},
@ -1729,6 +1739,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"urshl", 0x7ee05400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
{"sub", 0x7ee08400, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
{"cmeq", 0x7ee08c00, 0xffe0fc00, asisdsame, 0, SIMD, OP3 (Sd, Sn, Sm), QL_S_3SAMED, F_SSIZE},
/* AdvSIMDs scalar three same extension. */
{"sqrdmlah", 0x7e008400, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
{"sqrdmlsh", 0x7e008c00, 0xff20fc00, asimdsame, 0, RDMA, OP3 (Sd, Sn, Sm), QL_SISD_HS, F_SSIZE},
/* AdvSIMD scalar shift by immediate. */
{"sshr", 0x5f000400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},
{"ssra", 0x5f001400, 0xff80fc00, asisdshf, 0, SIMD, OP3 (Sd, Sn, IMM_VLSR), QL_SSHIFT_D, 0},