2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
* gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx. * gas/i386/sse-noavx.d: New. * gas/i386/sse-noavx.s: Likewise. * gas/i386/x86-64-sse-noavx.d: Likewise. * gas/i386/x86-64-sse-noavx.s: Likewise.
This commit is contained in:
H.J. Lu
parent
084076b886
commit
9ba52a267b
6 changed files with 229 additions and 0 deletions
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@ -1,3 +1,12 @@
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2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run sse-noavx and x86-64-sse-noavx.
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* gas/i386/sse-noavx.d: New.
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* gas/i386/sse-noavx.s: Likewise.
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* gas/i386/x86-64-sse-noavx.d: Likewise.
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* gas/i386/x86-64-sse-noavx.s: Likewise.
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2008-04-23 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/sse2.s: Add tests for pmuludq, paddq and psubq.
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@ -127,6 +127,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
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run_dump_test "sse-check"
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run_dump_test "sse-check-warn"
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run_list_test "sse-check-error" "-msse-check=error -I${srcdir}/$subdir -al"
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run_dump_test "sse-noavx"
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# These tests require support for 8 and 16 bit relocs,
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# so we only run them for ELF and COFF targets.
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@ -256,6 +257,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-sse-check"
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run_dump_test "x86-64-sse-check-warn"
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run_list_test "x86-64-sse-check-error" "-msse-check=error -I${srcdir}/$subdir -al"
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run_dump_test "x86-64-sse-noavx"
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if { ![istarget "*-*-aix*"]
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&& ![istarget "*-*-beos*"]
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57
gas/testsuite/gas/i386/sse-noavx.d
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57
gas/testsuite/gas/i386/sse-noavx.d
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@ -0,0 +1,57 @@
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#as: -msse-check=error
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#objdump: -dw
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#name: i386 SSE without AVX equivalent
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.*: file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: f2 0f 38 f0 d9 crc32b %cl,%ebx
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[ ]*[a-f0-9]+: 0f 2a d3 cvtpi2ps %mm3,%xmm2
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[ ]*[a-f0-9]+: 0f 2d f7 cvtps2pi %xmm7,%mm6
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[ ]*[a-f0-9]+: 0f 2c dc cvttps2pi %xmm4,%mm3
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[ ]*[a-f0-9]+: df 08 fisttp \(%eax\)
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[ ]*[a-f0-9]+: dd 08 fisttpll \(%eax\)
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[ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0
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[ ]*[a-f0-9]+: 0f 01 c8 monitor %eax,%ecx,%edx
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[ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%eax\)
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[ ]*[a-f0-9]+: 0f 01 c9 mwait %eax,%ecx
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[ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 1d c1 pabsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f d4 c1 paddq %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 3a 0f c1 02 palignr \$0x2,%mm1,%mm0
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[ ]*[a-f0-9]+: 0f e0 c1 pavgb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f e3 d3 pavgw %mm3,%mm2
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[ ]*[a-f0-9]+: 0f c5 c1 00 pextrw \$0x0,%mm1,%eax
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[ ]*[a-f0-9]+: 0f 38 02 c1 phaddd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 03 c1 phaddsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 01 c1 phaddw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 06 c1 phsubd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 07 c1 phsubsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 05 c1 phsubw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f c4 d2 02 pinsrw \$0x2,%edx,%mm2
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[ ]*[a-f0-9]+: 0f 38 04 c1 pmaddubsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f ee c1 pmaxsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f de d2 pmaxub %mm2,%mm2
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[ ]*[a-f0-9]+: 0f ea e5 pminsw %mm5,%mm4
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[ ]*[a-f0-9]+: 0f da f7 pminub %mm7,%mm6
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[ ]*[a-f0-9]+: 0f d7 c5 pmovmskb %mm5,%eax
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[ ]*[a-f0-9]+: 0f 38 0b c1 pmulhrsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f e4 e5 pmulhuw %mm5,%mm4
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[ ]*[a-f0-9]+: 0f f4 c8 pmuludq %mm0,%mm1
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[ ]*[a-f0-9]+: f3 0f b8 cb popcnt %ebx,%ecx
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[ ]*[a-f0-9]+: 0f 18 00 prefetchnta \(%eax\)
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[ ]*[a-f0-9]+: 0f 18 08 prefetcht0 \(%eax\)
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[ ]*[a-f0-9]+: 0f 18 10 prefetcht1 \(%eax\)
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[ ]*[a-f0-9]+: 0f 18 18 prefetcht2 \(%eax\)
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[ ]*[a-f0-9]+: 0f f6 f7 psadbw %mm7,%mm6
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[ ]*[a-f0-9]+: 0f 38 00 c1 pshufb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 70 da 01 pshufw \$0x1,%mm2,%mm3
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[ ]*[a-f0-9]+: 0f 38 08 c1 psignb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 0a c1 psignd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 09 c1 psignw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f fb c1 psubq %mm1,%mm0
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[ ]*[a-f0-9]+: 0f ae f8 sfence
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#pass
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51
gas/testsuite/gas/i386/sse-noavx.s
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51
gas/testsuite/gas/i386/sse-noavx.s
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@ -0,0 +1,51 @@
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# Check SSE instructions without AVX equivalent
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.text
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_start:
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crc32 %cl,%ebx
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cvtpi2ps %mm3,%xmm2
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cvtps2pi %xmm7,%mm6
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cvttps2pi %xmm4,%mm3
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fisttp (%eax)
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fisttpll (%eax)
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maskmovq %mm7,%mm0
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monitor
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movntq %mm2,(%eax)
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mwait
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pabsb %mm1,%mm0
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pabsd %mm1,%mm0
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pabsw %mm1,%mm0
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paddq %mm1,%mm0
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palignr $0x2,%mm1,%mm0
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pavgb %mm1,%mm0
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pavgw %mm3,%mm2
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pextrw $0x0,%mm1,%eax
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phaddd %mm1,%mm0
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phaddsw %mm1,%mm0
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phaddw %mm1,%mm0
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phsubd %mm1,%mm0
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phsubsw %mm1,%mm0
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phsubw %mm1,%mm0
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pinsrw $0x2,%edx,%mm2
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pmaddubsw %mm1,%mm0
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pmaxsw %mm1,%mm0
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pmaxub %mm2,%mm2
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pminsw %mm5,%mm4
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pminub %mm7,%mm6
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pmovmskb %mm5,%eax
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pmulhrsw %mm1,%mm0
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pmulhuw %mm5,%mm4
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pmuludq %mm0, %mm1
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popcnt %ebx,%ecx
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prefetchnta (%eax)
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prefetcht0 (%eax)
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prefetcht1 (%eax)
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prefetcht2 (%eax)
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psadbw %mm7,%mm6
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pshufb %mm1,%mm0
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pshufw $0x1,%mm2,%mm3
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psignb %mm1,%mm0
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psignd %mm1,%mm0
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psignw %mm1,%mm0
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psubq %mm1,%mm0
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sfence
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58
gas/testsuite/gas/i386/x86-64-sse-noavx.d
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58
gas/testsuite/gas/i386/x86-64-sse-noavx.d
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@ -0,0 +1,58 @@
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#as: -msse-check=error
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#objdump: -dw
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#name: x86-64 SSE without AVX equivalent
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.*: file format .*
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Disassembly of section .text:
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0+ <_start>:
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[ ]*[a-f0-9]+: 48 0f c7 08 cmpxchg16b \(%rax\)
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[ ]*[a-f0-9]+: f2 0f 38 f0 d9 crc32b %cl,%ebx
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[ ]*[a-f0-9]+: 0f 2a d3 cvtpi2ps %mm3,%xmm2
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[ ]*[a-f0-9]+: 0f 2d f7 cvtps2pi %xmm7,%mm6
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[ ]*[a-f0-9]+: 0f 2c dc cvttps2pi %xmm4,%mm3
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[ ]*[a-f0-9]+: df 08 fisttp \(%rax\)
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[ ]*[a-f0-9]+: dd 08 fisttpll \(%rax\)
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[ ]*[a-f0-9]+: 0f f7 c7 maskmovq %mm7,%mm0
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[ ]*[a-f0-9]+: 0f 01 c8 monitor %rax,%rcx,%rdx
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[ ]*[a-f0-9]+: 0f e7 10 movntq %mm2,\(%rax\)
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[ ]*[a-f0-9]+: 0f 01 c9 mwait %rax,%rcx
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[ ]*[a-f0-9]+: 0f 38 1c c1 pabsb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 1e c1 pabsd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 1d c1 pabsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f d4 c1 paddq %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 3a 0f c1 02 palignr \$0x2,%mm1,%mm0
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[ ]*[a-f0-9]+: 0f e0 c1 pavgb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f e3 d3 pavgw %mm3,%mm2
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[ ]*[a-f0-9]+: 0f c5 c1 00 pextrw \$0x0,%mm1,%eax
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[ ]*[a-f0-9]+: 0f 38 02 c1 phaddd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 03 c1 phaddsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 01 c1 phaddw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 06 c1 phsubd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 07 c1 phsubsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 05 c1 phsubw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f c4 d2 02 pinsrw \$0x2,%edx,%mm2
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[ ]*[a-f0-9]+: 0f 38 04 c1 pmaddubsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f ee c1 pmaxsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f de d2 pmaxub %mm2,%mm2
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[ ]*[a-f0-9]+: 0f ea e5 pminsw %mm5,%mm4
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[ ]*[a-f0-9]+: 0f da f7 pminub %mm7,%mm6
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[ ]*[a-f0-9]+: 0f d7 c5 pmovmskb %mm5,%eax
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[ ]*[a-f0-9]+: 0f 38 0b c1 pmulhrsw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f e4 e5 pmulhuw %mm5,%mm4
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[ ]*[a-f0-9]+: 0f f4 c8 pmuludq %mm0,%mm1
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[ ]*[a-f0-9]+: f3 0f b8 cb popcnt %ebx,%ecx
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[ ]*[a-f0-9]+: 0f 18 00 prefetchnta \(%rax\)
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[ ]*[a-f0-9]+: 0f 18 08 prefetcht0 \(%rax\)
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[ ]*[a-f0-9]+: 0f 18 10 prefetcht1 \(%rax\)
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[ ]*[a-f0-9]+: 0f 18 18 prefetcht2 \(%rax\)
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[ ]*[a-f0-9]+: 0f f6 f7 psadbw %mm7,%mm6
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[ ]*[a-f0-9]+: 0f 38 00 c1 pshufb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 70 da 01 pshufw \$0x1,%mm2,%mm3
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[ ]*[a-f0-9]+: 0f 38 08 c1 psignb %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 0a c1 psignd %mm1,%mm0
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[ ]*[a-f0-9]+: 0f 38 09 c1 psignw %mm1,%mm0
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[ ]*[a-f0-9]+: 0f fb c1 psubq %mm1,%mm0
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[ ]*[a-f0-9]+: 0f ae f8 sfence
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#pass
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52
gas/testsuite/gas/i386/x86-64-sse-noavx.s
Normal file
52
gas/testsuite/gas/i386/x86-64-sse-noavx.s
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@ -0,0 +1,52 @@
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# Check 64bit SSE instructions without AVX equivalent
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.text
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_start:
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cmpxchg16b (%rax)
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crc32 %cl,%ebx
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cvtpi2ps %mm3,%xmm2
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cvtps2pi %xmm7,%mm6
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cvttps2pi %xmm4,%mm3
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fisttp (%rax)
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fisttpll (%rax)
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maskmovq %mm7,%mm0
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monitor
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movntq %mm2,(%rax)
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mwait
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pabsb %mm1,%mm0
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pabsd %mm1,%mm0
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pabsw %mm1,%mm0
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paddq %mm1,%mm0
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palignr $0x2,%mm1,%mm0
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pavgb %mm1,%mm0
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pavgw %mm3,%mm2
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pextrw $0x0,%mm1,%eax
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phaddd %mm1,%mm0
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phaddsw %mm1,%mm0
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phaddw %mm1,%mm0
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phsubd %mm1,%mm0
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phsubsw %mm1,%mm0
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phsubw %mm1,%mm0
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pinsrw $0x2,%edx,%mm2
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pmaddubsw %mm1,%mm0
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pmaxsw %mm1,%mm0
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pmaxub %mm2,%mm2
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pminsw %mm5,%mm4
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pminub %mm7,%mm6
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pmovmskb %mm5,%eax
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pmulhrsw %mm1,%mm0
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pmulhuw %mm5,%mm4
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pmuludq %mm0, %mm1
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popcnt %ebx,%ecx
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prefetchnta (%rax)
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prefetcht0 (%rax)
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prefetcht1 (%rax)
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prefetcht2 (%rax)
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psadbw %mm7,%mm6
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pshufb %mm1,%mm0
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pshufw $0x1,%mm2,%mm3
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psignb %mm1,%mm0
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psignd %mm1,%mm0
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psignw %mm1,%mm0
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psubq %mm1,%mm0
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sfence
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