aarch64: Add the SME2 predicate-related instructions
Implementation-wise, the main things to note here are: - the WHILE* instructions have forms that return a pair of predicate registers. This is the first time that we've had lists of predicate registers, and they wrap around after register 15 rather than after register 31. - the predicate-as-counter WHILE* instructions have a fourth operand that specifies the vector length. We can treat this as an enumeration, except that immediate values aren't allowed. - PEXT takes an unsuffixed predicate index of the form PN<n>[<imm>]. This is the first instance of a vector/predicate index having no suffix.
This commit is contained in:
Richard Sandiford
parent
b408ebbf52
commit
99e01a66b4
37 changed files with 4022 additions and 906 deletions
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@ -474,6 +474,8 @@ get_reg_expected_msg (unsigned int mask, unsigned int seen)
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PN is expected, and vice versa, so the issue at this point is
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"predicate-like" vs. "not predicate-like". */
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return N_("expected an SVE predicate register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_PN])
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return N_("expected an SVE predicate-as-counter register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_VZ])
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return N_("expected a vector register at operand %d");
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if (mask == reg_type_masks[REG_TYPE_ZP])
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@ -1277,7 +1279,7 @@ parse_typed_reg (char **ccp, aarch64_reg_type type,
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if (!(flags & PTR_FULL_REG) && skip_past_char (&str, '['))
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{
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/* Reject Sn[index] syntax. */
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if (!is_typed_vecreg)
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if (reg->type != REG_TYPE_PN && !is_typed_vecreg)
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{
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first_error (_("this type of register can't be indexed"));
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return NULL;
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@ -1344,6 +1346,14 @@ eq_vector_type_el (struct vector_type_el e1, struct vector_type_el e2)
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&& e1.index == e2.index);
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}
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/* Return the register number mask for registers of type REG_TYPE. */
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static inline int
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reg_type_mask (aarch64_reg_type reg_type)
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{
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return reg_type == REG_TYPE_P ? 15 : 31;
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}
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/* This function parses a list of vector registers of type TYPE.
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On success, it returns the parsed register list information in the
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following encoded format:
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@ -1372,7 +1382,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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char *str = *ccp;
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int nb_regs;
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struct vector_type_el typeinfo, typeinfo_first;
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int val, val_range;
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int val, val_range, mask;
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int in_range;
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int ret_val;
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bool error = false;
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@ -1396,6 +1406,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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val = -1;
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val_range = -1;
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in_range = 0;
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mask = reg_type_mask (type);
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do
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{
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if (in_range)
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@ -1431,7 +1442,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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(_("invalid range in vector register list"));
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error = true;
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}
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val_range = (val_range + 1) & 0x1f;
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val_range = (val_range + 1) & mask;
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}
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else
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{
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@ -1452,7 +1463,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
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nb_regs++;
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if (val_range == val)
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break;
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val_range = (val_range + 1) & 0x1f;
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val_range = (val_range + 1) & mask;
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}
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in_range = 0;
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ptr_flags |= PTR_GOOD_MATCH;
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@ -4316,8 +4327,10 @@ parse_adrp (char **str)
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/* Parse a symbolic operand such as "pow2" at *STR. ARRAY is an array
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of SIZE tokens in which index I gives the token for field value I,
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or is null if field value I is invalid. REG_TYPE says which register
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names should be treated as registers rather than as symbolic immediates.
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or is null if field value I is invalid. If the symbolic operand
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can also be given as a 0-based integer, REG_TYPE says which register
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names should be treated as registers rather than as symbolic immediates
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while parsing that integer. REG_TYPE is REG_TYPE_MAX otherwise.
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Return true on success, moving *STR past the operand and storing the
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field value in *VAL. */
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@ -4345,6 +4358,9 @@ parse_enum_string (char **str, int64_t *val, const char *const *array,
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return true;
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}
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if (reg_type == REG_TYPE_MAX)
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return false;
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if (!parse_immediate_expression (&p, &exp, reg_type))
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return false;
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@ -4971,6 +4987,12 @@ parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
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goto failure; \
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} while (0)
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#define po_strict_enum_or_fail(array) do { \
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if (!parse_enum_string (&str, &val, array, \
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ARRAY_SIZE (array), REG_TYPE_MAX)) \
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goto failure; \
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} while (0)
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#define po_misc_or_fail(expr) do { \
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if (!expr) \
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goto failure; \
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@ -6445,16 +6467,18 @@ ldst_lo12_determine_real_reloc_type (void)
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return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
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}
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/* Check whether a register list REGINFO is valid. The registers must be
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numbered in increasing order (modulo 32). They must also have a
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consistent stride.
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/* Check whether a register list REGINFO is valid. The registers have type
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REG_TYPE and must be numbered in increasing order (modulo the register
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bank size). They must have a consistent stride.
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Return true if the list is valid, describing it in LIST if so. */
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static bool
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reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list)
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reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list,
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aarch64_reg_type reg_type)
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{
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uint32_t i, nb_regs, prev_regno, incr;
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uint32_t i, nb_regs, prev_regno, incr, mask;
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mask = reg_type_mask (reg_type);
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nb_regs = 1 + (reginfo & 0x3);
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reginfo >>= 2;
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@ -6469,7 +6493,7 @@ reg_list_valid_p (uint32_t reginfo, struct aarch64_reglist *list)
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uint32_t curr_regno, curr_incr;
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reginfo >>= 5;
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curr_regno = reginfo & 0x1f;
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curr_incr = (curr_regno - prev_regno) & 0x1f;
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curr_incr = (curr_regno - prev_regno) & mask;
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if (curr_incr == 0)
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return false;
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else if (i == 1)
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@ -6638,7 +6662,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_PNg4_10:
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case AARCH64_OPND_SVE_PNn:
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case AARCH64_OPND_SVE_PNt:
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case AARCH64_OPND_SME_PNd3:
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case AARCH64_OPND_SME_PNg3:
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case AARCH64_OPND_SME_PNn:
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reg_type = REG_TYPE_PN;
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goto vector_reg;
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@ -6723,6 +6749,8 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_ZtxN:
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case AARCH64_OPND_SME_Zdnx2:
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case AARCH64_OPND_SME_Zdnx4:
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case AARCH64_OPND_SME_Zmx2:
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case AARCH64_OPND_SME_Zmx4:
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case AARCH64_OPND_SME_Znx2:
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case AARCH64_OPND_SME_Znx4:
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case AARCH64_OPND_SME_Ztx2_STRIDED:
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@ -6730,6 +6758,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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reg_type = REG_TYPE_Z;
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goto vector_reg_list;
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case AARCH64_OPND_SME_Pdx2:
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case AARCH64_OPND_SME_PdxN:
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reg_type = REG_TYPE_P;
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goto vector_reg_list;
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case AARCH64_OPND_LVn:
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case AARCH64_OPND_LVt:
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case AARCH64_OPND_LVt_AL:
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@ -6753,7 +6786,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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if (val == PARSE_FAIL)
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goto failure;
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if (! reg_list_valid_p (val, &info->reglist))
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if (! reg_list_valid_p (val, &info->reglist, reg_type))
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{
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set_fatal_syntax_error (_("invalid register list"));
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goto failure;
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@ -6779,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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goto failure;
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if (!(vectype.defined & NTA_HASTYPE))
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{
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if (reg_type == REG_TYPE_Z)
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if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
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set_fatal_syntax_error (_("missing type suffix"));
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goto failure;
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}
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@ -7707,6 +7740,24 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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goto failure;
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break;
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case AARCH64_OPND_SME_PNn3_INDEX1:
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case AARCH64_OPND_SME_PNn3_INDEX2:
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reg = aarch64_reg_parse (&str, REG_TYPE_PN, &vectype);
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if (!reg)
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goto failure;
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if (!(vectype.defined & NTA_HASINDEX))
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{
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set_syntax_error (_("missing register index"));
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goto failure;
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}
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info->reglane.regno = reg->number;
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info->reglane.index = vectype.index;
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if (vectype.type == NT_invtype)
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info->qualifier = AARCH64_OPND_QLF_NIL;
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else
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info->qualifier = vectype_to_qualifier (&vectype);
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break;
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case AARCH64_OPND_BTI_TARGET:
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val = parse_bti_operand (&str, &(info->hint_option));
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if (val == PARSE_FAIL)
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@ -7753,6 +7804,12 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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info->qualifier = qualifier;
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break;
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case AARCH64_OPND_SME_VLxN_10:
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case AARCH64_OPND_SME_VLxN_13:
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po_strict_enum_or_fail (aarch64_sme_vlxn_array);
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info->imm.value = val;
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break;
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case AARCH64_OPND_MOPS_ADDR_Rd:
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case AARCH64_OPND_MOPS_ADDR_Rs:
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po_char_or_fail ('[');
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@ -3139,7 +3139,7 @@
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: usubwt z0\.s, z0\.s, z0\.h
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[^ :]+:[0-9]+: Info: usubwt z0\.d, z0\.d, z0\.s
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,x32,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,x0,x32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,x0,x0'
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@ -3165,7 +3165,7 @@
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[^ :]+:[0-9]+: Info: whilege p0\.h, x0, x0
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[^ :]+:[0-9]+: Info: whilege p0\.s, x0, x0
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[^ :]+:[0-9]+: Info: whilege p0\.d, x0, x0
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w32,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilege p0/m,w0,w0'
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@ -3177,7 +3177,7 @@
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[^ :]+:[0-9]+: Info: whilege p0\.d, w0, w0
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege p0\.b,w31,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege p0\.b,w0,w31'
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilegt p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,x32,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,x0,x32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,x0,x0'
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@ -3203,7 +3203,7 @@
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[^ :]+:[0-9]+: Info: whilegt p0\.h, x0, x0
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[^ :]+:[0-9]+: Info: whilegt p0\.s, x0, x0
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[^ :]+:[0-9]+: Info: whilegt p0\.d, x0, x0
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilegt p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilegt p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w32,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilegt p0/m,w0,w0'
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@ -3215,7 +3215,7 @@
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[^ :]+:[0-9]+: Info: whilegt p0\.d, w0, w0
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilegt p0\.b,w31,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilegt p0\.b,w0,w31'
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehi p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,x32,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,x0,x32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,x0,x0'
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@ -3241,7 +3241,7 @@
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[^ :]+:[0-9]+: Info: whilehi p0\.h, x0, x0
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[^ :]+:[0-9]+: Info: whilehi p0\.s, x0, x0
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[^ :]+:[0-9]+: Info: whilehi p0\.d, x0, x0
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehi p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehi p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w32,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilehi p0/m,w0,w0'
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@ -3253,7 +3253,7 @@
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[^ :]+:[0-9]+: Info: whilehi p0\.d, w0, w0
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehi p0\.b,w31,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehi p0\.b,w0,w31'
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehs p16\.b,x0,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,x32,x0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,x0,x32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,x0,x0'
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@ -3279,7 +3279,7 @@
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[^ :]+:[0-9]+: Info: whilehs p0\.h, x0, x0
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[^ :]+:[0-9]+: Info: whilehs p0\.s, x0, x0
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[^ :]+:[0-9]+: Info: whilehs p0\.d, x0, x0
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[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilehs p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilehs p16\.b,w0,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilehs p0\.b,w32,w0'
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[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilehs p0\.b,w0,w32'
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[^ :]+:[0-9]+: Error: operand mismatch -- `whilehs p0/m,w0,w0'
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@ -72,5 +72,5 @@ Disassembly of section \.text:
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f8: 25277c61 psel p1, p15, p3.b\[w15, 0\]
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fc: 252778a2 psel p2, p14, p5.b\[w15, 0\]
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100: 25244200 \.inst 0x25244200 ; undefined
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104: 25244010 \.inst 0x25244010 ; undefined
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108: 25244210 \.inst 0x25244210 ; undefined
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104: 25244010 whilege pn8.b, x0, x4, vlx2
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108: 25244210 whilege pn8.b, x16, x4, vlx2
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3
gas/testsuite/gas/aarch64/sme2-6-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-6-invalid.d
Normal file
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@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sme2-6-invalid.s
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#error_output: sme2-6-invalid.l
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139
gas/testsuite/gas/aarch64/sme2-6-invalid.l
Normal file
139
gas/testsuite/gas/aarch64/sme2-6-invalid.l
Normal file
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@ -0,0 +1,139 @@
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[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp 0,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `cntp x0,0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,0'
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp xsp,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 1 -- `cntp sp,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `cntp w0,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 3 -- `cntp x0,p0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 2 -- `cntp x0,pn16\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,#0'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,vl'
|
||||
[^ :]+:[0-9]+: Error: operand 3 must be VLx2 or VLx4 -- `cntp x0,pn0\.b,vlx3'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `cntp x0,pn0,vlx2'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `cntp x0,pn0\.q,vlx2'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.b, vlx2
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.h, vlx2
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.s, vlx2
|
||||
[^ :]+:[0-9]+: Info: cntp x0, pn0\.d, vlx2
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `pext 0,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p0\.b,0'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 1 -- `pext pn8\.b,pn0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `pext z0\.b,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p8\.b,z8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `pext p8\.b,x8'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `pext p8\.b,p8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: missing register index at operand 2 -- `pext p8\.b,pn8'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[4\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 2 -- `pext p8\.b,pn8\[1<<32\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `pext p8\.b,pn8\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: pext p8\.b, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: pext p8\.h, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: pext p8\.s, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: pext p8\.d, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `pext p8\.q,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: pext p8\.b, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: pext p8\.h, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: pext p8\.s, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: pext p8\.d, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `pext {p0\.b-p2\.b},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `pext {p0-p1},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `pext {p0\.b-p1\.b},pn7\[0\]'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `pext {p0\.b-p1\.b},pn0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: missing register index at operand 2 -- `pext {p0\.b-p1\.b},pn8'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `pext {p0\.b-p1\.b},p0\[0\]'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `pext {p0\.b-p1\.b},pn8\.b\[0\]'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: pext {p0\.b-p1\.b}, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: pext {p0\.h-p1\.h}, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: pext {p0\.s-p1\.s}, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Info: pext {p0\.d-p1\.d}, pn8\[0\]
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[-1\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[2\]'
|
||||
[^ :]+:[0-9]+: Error: register element index out of range 0 to 1 at operand 2 -- `pext {p0\.b-p1\.b},pn8\[1<<32\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `ptrue 0'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.b'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.b'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.h'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.h'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.s'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.s'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn0\.d'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `ptrue pn7\.d'
|
||||
[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `ptrue pn8\.b,all'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `ptrue pn8\.q'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: ptrue pn8\.b
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: ptrue pn8\.h
|
||||
[^ :]+:[0-9]+: Info: ptrue pn8\.s
|
||||
[^ :]+:[0-9]+: Info: ptrue pn8\.d
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `sel 0,pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `sel {z0\.b-z1\.b},0,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected '{' at operand 3 -- `sel {z0\.b-z1\.b},pn8,0,{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected '{' at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},0'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z1\.b-z2\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `sel {z0\.b-z1\.b},p8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `sel {z0\.b-z1\.b},pn7,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.b-z1\.b},pn8/z,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.b-z1\.b},pn8/m,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 2 -- `sel {z0\.b-z1\.b},pn0,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z11\.b-z12\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z17\.b-z18\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z1\.b-z4\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z10\.b-z13\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sel {z15\.b-z18\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z1\.b-z4\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z22\.b-z25\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z27\.b-z30\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z5\.b-z8\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z14\.b-z17\.b}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z19\.b-z22\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z1\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `sel {z0\.b-z2\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z2\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 4 -- `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z2\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `sel {z0\.b-z2\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z2\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 4 -- `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z0\.b-z2\.b}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `sel {z0\.q-z1\.q},pn8,{z0\.q-z1\.q},{z0\.q-z1\.q}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
92
gas/testsuite/gas/aarch64/sme2-6-invalid.s
Normal file
92
gas/testsuite/gas/aarch64/sme2-6-invalid.s
Normal file
|
|
@ -0,0 +1,92 @@
|
|||
cntp 0, pn0.b, vlx2
|
||||
cntp x0, 0, vlx2
|
||||
cntp x0, pn0.b, 0
|
||||
|
||||
cntp xsp, pn0.b, vlx2
|
||||
cntp sp, pn0.b, vlx2
|
||||
cntp w0, pn0.b, vlx2
|
||||
cntp x0, p0.b, vlx2
|
||||
cntp x0, pn16.b, vlx2
|
||||
cntp x0, pn0.b, #0
|
||||
cntp x0, pn0.b, vl
|
||||
cntp x0, pn0.b, vlx3
|
||||
|
||||
cntp x0, pn0, vlx2
|
||||
cntp x0, pn0.q, vlx2
|
||||
|
||||
pext 0, pn8[0]
|
||||
pext p0.b, 0
|
||||
|
||||
pext pn8.b, pn0[0]
|
||||
pext z0.b, pn8[0]
|
||||
pext p8.b, z8[0]
|
||||
pext p8.b, x8
|
||||
pext p8.b, p8[0]
|
||||
pext p8.b, pn8
|
||||
pext p8.b, pn8[-1]
|
||||
pext p8.b, pn8[4]
|
||||
pext p8.b, pn8[1 << 32]
|
||||
pext p8.b, pn8.b[0]
|
||||
pext p8.q, pn8[0]
|
||||
|
||||
pext { p0.b - p2.b }, pn8[0]
|
||||
pext { p0 - p1 }, pn8[0]
|
||||
pext { p0.b - p1.b }, pn7[0]
|
||||
pext { p0.b - p1.b }, pn0[0]
|
||||
pext { p0.b - p1.b }, pn8
|
||||
pext { p0.b - p1.b }, p0[0]
|
||||
pext { p0.b - p1.b }, pn8.b[0]
|
||||
pext { p0.b - p1.b }, pn8[-1]
|
||||
pext { p0.b - p1.b }, pn8[2]
|
||||
pext { p0.b - p1.b }, pn8[1 << 32]
|
||||
|
||||
ptrue 0
|
||||
|
||||
ptrue pn0.b
|
||||
ptrue pn7.b
|
||||
ptrue pn0.h
|
||||
ptrue pn7.h
|
||||
ptrue pn0.s
|
||||
ptrue pn7.s
|
||||
ptrue pn0.d
|
||||
ptrue pn7.d
|
||||
ptrue pn8.b, all
|
||||
ptrue pn8.q
|
||||
|
||||
sel 0, pn8, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, 0, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, 0, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, 0
|
||||
|
||||
sel { z1.b - z2.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, p8, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn7, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8/z, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8/m, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn0, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z11.b - z12.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z17.b - z18.b }
|
||||
|
||||
sel { z1.b - z4.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z10.b - z13.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z15.b - z18.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z1.b - z4.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z22.b - z25.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z27.b - z30.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z5.b - z8.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z14.b - z17.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z19.b - z22.b }
|
||||
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z1.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z1.b }
|
||||
|
||||
sel { z0.b - z2.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z2.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z2.b }
|
||||
|
||||
sel { z0.b - z2.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z2.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z0.b - z2.b }
|
||||
|
||||
sel { z0.q - z1.q }, pn8, { z0.q - z1.q }, { z0.q - z1.q }
|
||||
3
gas/testsuite/gas/aarch64/sme2-6-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-6-noarch.d
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
#as: -march=armv8-a+sme
|
||||
#source: sme2-6.s
|
||||
#error_output: sme2-6-noarch.l
|
||||
145
gas/testsuite/gas/aarch64/sme2-6-noarch.l
Normal file
145
gas/testsuite/gas/aarch64/sme2-6-noarch.l
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.B,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.b,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.b,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X11,PN13\.b,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.h,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.H,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.h,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.h,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.h,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.h,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X20,PN9\.h,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.s,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.s,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.s,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.s,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.s,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.s,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X15,PN8\.s,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.d,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X0,PN0\.d,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x30,pn0\.d,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp xzr,pn0\.d,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn15\.d,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp x0,pn0\.d,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `cntp X4,PN5\.d,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.B,PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.b,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.b,pn8\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p4\.b,pn11\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.H,PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.h,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.h,pn8\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p5\.h,pn14\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.S,PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.s,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.s,pn8\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p6\.s,pn10\[2\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext P0\.D,PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p15\.d,pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p0\.d,pn8\[3\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext p7\.d,pn9\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b,p1\.b},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.B-P1\.B},PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.b-p15\.b},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.b,p0\.b},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.b-p0\.b},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.b-p1\.b},pn8\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p7\.b-p8\.b},pn12\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h,p1\.h},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.H-P1\.H},PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.h-p15\.h},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.h,p0\.h},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.h-p0\.h},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.h-p1\.h},pn8\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p2\.h-p3\.h},pn14\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s,p1\.s},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.S-P1\.S},PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.s-p15\.s},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.s,p0\.s},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.s-p0\.s},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.s-p1\.s},pn8\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p5\.s-p6\.s},pn13\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d,p1\.d},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {P0\.D-P1\.D},PN8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p14\.d-p15\.d},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.d,p0\.d},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p15\.d-p0\.d},pn8\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn15\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p0\.d-p1\.d},pn8\[1\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `pext {p12\.d-p13\.d},pn9\[0\]'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn11\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn9\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn14\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn8\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn12\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `ptrue pn15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.b-z31\.b},pn8,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn15,{z0\.b-z1\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z30\.b-z31\.b},{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z1\.b},pn8,{z0\.b-z1\.b},{z30\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z2\.b-z3\.b},pn12,{z6\.b-z7\.b},{z10\.b-z11\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.h-z31\.h},pn8,{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn15,{z0\.h-z1\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z30\.h-z31\.h},{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z1\.h},pn8,{z0\.h-z1\.h},{z30\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z12\.h-z13\.h},pn9,{z14\.h-z15\.h},{z16\.h-z17\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.s-z31\.s},pn8,{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn15,{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z30\.s-z31\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z1\.s},pn8,{z0\.s-z1\.s},{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z18\.s-z19\.s},pn11,{z22\.s-z23\.s},{z24\.s-z25\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z30\.d-z31\.d},pn8,{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn15,{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z30\.d-z31\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z1\.d},pn8,{z0\.d-z1\.d},{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z8\.d-z9\.d},pn14,{z26\.d-z27\.d},{z28\.d-z29\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.b-z31\.b},pn8,{z0\.b-z3\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z28\.b-z31\.b},{z0\.b-z3\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.b-z3\.b},pn8,{z0\.b-z3\.b},{z28\.b-z31\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z4\.b-z7\.b},pn10,{z8\.b-z11\.b},{z12\.b-z15\.b}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.h-z31\.h},pn8,{z0\.h-z3\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z28\.h-z31\.h},{z0\.h-z3\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.h-z3\.h},pn8,{z0\.h-z3\.h},{z28\.h-z31\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z8\.h-z11\.h},pn10,{z16\.h-z19\.h},{z20\.h-z23\.h}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.s-z31\.s},pn8,{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z28\.s-z31\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.s-z3\.s},pn8,{z0\.s-z3\.s},{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z16\.s-z19\.s},pn10,{z20\.s-z23\.s},{z24\.s-z27\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z28\.d-z31\.d},pn8,{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z28\.d-z31\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z0\.d-z3\.d},pn8,{z0\.d-z3\.d},{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sel {z20\.d-z23\.d},pn10,{z4\.d-z7\.d},{z8\.d-z11\.d}'
|
||||
153
gas/testsuite/gas/aarch64/sme2-6.d
Normal file
153
gas/testsuite/gas/aarch64/sme2-6.d
Normal file
|
|
@ -0,0 +1,153 @@
|
|||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: 25208200 cntp x0, pn0\.b, vlx2
|
||||
[^:]+: 25208200 cntp x0, pn0\.b, vlx2
|
||||
[^:]+: 2520821e cntp x30, pn0\.b, vlx2
|
||||
[^:]+: 2520821f cntp xzr, pn0\.b, vlx2
|
||||
[^:]+: 252083e0 cntp x0, pn15\.b, vlx2
|
||||
[^:]+: 25208600 cntp x0, pn0\.b, vlx4
|
||||
[^:]+: 252087ab cntp x11, pn13\.b, vlx4
|
||||
[^:]+: 25608200 cntp x0, pn0\.h, vlx2
|
||||
[^:]+: 25608200 cntp x0, pn0\.h, vlx2
|
||||
[^:]+: 2560821e cntp x30, pn0\.h, vlx2
|
||||
[^:]+: 2560821f cntp xzr, pn0\.h, vlx2
|
||||
[^:]+: 256083e0 cntp x0, pn15\.h, vlx2
|
||||
[^:]+: 25608600 cntp x0, pn0\.h, vlx4
|
||||
[^:]+: 25608334 cntp x20, pn9\.h, vlx2
|
||||
[^:]+: 25a08200 cntp x0, pn0\.s, vlx2
|
||||
[^:]+: 25a08200 cntp x0, pn0\.s, vlx2
|
||||
[^:]+: 25a0821e cntp x30, pn0\.s, vlx2
|
||||
[^:]+: 25a0821f cntp xzr, pn0\.s, vlx2
|
||||
[^:]+: 25a083e0 cntp x0, pn15\.s, vlx2
|
||||
[^:]+: 25a08600 cntp x0, pn0\.s, vlx4
|
||||
[^:]+: 25a0870f cntp x15, pn8\.s, vlx4
|
||||
[^:]+: 25e08200 cntp x0, pn0\.d, vlx2
|
||||
[^:]+: 25e08200 cntp x0, pn0\.d, vlx2
|
||||
[^:]+: 25e0821e cntp x30, pn0\.d, vlx2
|
||||
[^:]+: 25e0821f cntp xzr, pn0\.d, vlx2
|
||||
[^:]+: 25e083e0 cntp x0, pn15\.d, vlx2
|
||||
[^:]+: 25e08600 cntp x0, pn0\.d, vlx4
|
||||
[^:]+: 25e082a4 cntp x4, pn5\.d, vlx2
|
||||
[^:]+: 25207010 pext p0\.b, pn8\[0\]
|
||||
[^:]+: 25207010 pext p0\.b, pn8\[0\]
|
||||
[^:]+: 2520701f pext p15\.b, pn8\[0\]
|
||||
[^:]+: 252070f0 pext p0\.b, pn15\[0\]
|
||||
[^:]+: 25207310 pext p0\.b, pn8\[3\]
|
||||
[^:]+: 25207274 pext p4\.b, pn11\[2\]
|
||||
[^:]+: 25607010 pext p0\.h, pn8\[0\]
|
||||
[^:]+: 25607010 pext p0\.h, pn8\[0\]
|
||||
[^:]+: 2560701f pext p15\.h, pn8\[0\]
|
||||
[^:]+: 256070f0 pext p0\.h, pn15\[0\]
|
||||
[^:]+: 25607310 pext p0\.h, pn8\[3\]
|
||||
[^:]+: 256071d5 pext p5\.h, pn14\[1\]
|
||||
[^:]+: 25a07010 pext p0\.s, pn8\[0\]
|
||||
[^:]+: 25a07010 pext p0\.s, pn8\[0\]
|
||||
[^:]+: 25a0701f pext p15\.s, pn8\[0\]
|
||||
[^:]+: 25a070f0 pext p0\.s, pn15\[0\]
|
||||
[^:]+: 25a07310 pext p0\.s, pn8\[3\]
|
||||
[^:]+: 25a07256 pext p6\.s, pn10\[2\]
|
||||
[^:]+: 25e07010 pext p0\.d, pn8\[0\]
|
||||
[^:]+: 25e07010 pext p0\.d, pn8\[0\]
|
||||
[^:]+: 25e0701f pext p15\.d, pn8\[0\]
|
||||
[^:]+: 25e070f0 pext p0\.d, pn15\[0\]
|
||||
[^:]+: 25e07310 pext p0\.d, pn8\[3\]
|
||||
[^:]+: 25e07137 pext p7\.d, pn9\[1\]
|
||||
[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
|
||||
[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
|
||||
[^:]+: 25207410 pext {p0\.b-p1\.b}, pn8\[0\]
|
||||
[^:]+: 2520741e pext {p14\.b-p15\.b}, pn8\[0\]
|
||||
[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\]
|
||||
[^:]+: 2520741f pext {p15\.b-p0\.b}, pn8\[0\]
|
||||
[^:]+: 252074f0 pext {p0\.b-p1\.b}, pn15\[0\]
|
||||
[^:]+: 25207510 pext {p0\.b-p1\.b}, pn8\[1\]
|
||||
[^:]+: 25207497 pext {p7\.b-p8\.b}, pn12\[0\]
|
||||
[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
|
||||
[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
|
||||
[^:]+: 25607410 pext {p0\.h-p1\.h}, pn8\[0\]
|
||||
[^:]+: 2560741e pext {p14\.h-p15\.h}, pn8\[0\]
|
||||
[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\]
|
||||
[^:]+: 2560741f pext {p15\.h-p0\.h}, pn8\[0\]
|
||||
[^:]+: 256074f0 pext {p0\.h-p1\.h}, pn15\[0\]
|
||||
[^:]+: 25607510 pext {p0\.h-p1\.h}, pn8\[1\]
|
||||
[^:]+: 256074d2 pext {p2\.h-p3\.h}, pn14\[0\]
|
||||
[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
|
||||
[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
|
||||
[^:]+: 25a07410 pext {p0\.s-p1\.s}, pn8\[0\]
|
||||
[^:]+: 25a0741e pext {p14\.s-p15\.s}, pn8\[0\]
|
||||
[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\]
|
||||
[^:]+: 25a0741f pext {p15\.s-p0\.s}, pn8\[0\]
|
||||
[^:]+: 25a074f0 pext {p0\.s-p1\.s}, pn15\[0\]
|
||||
[^:]+: 25a07510 pext {p0\.s-p1\.s}, pn8\[1\]
|
||||
[^:]+: 25a074b5 pext {p5\.s-p6\.s}, pn13\[0\]
|
||||
[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
|
||||
[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
|
||||
[^:]+: 25e07410 pext {p0\.d-p1\.d}, pn8\[0\]
|
||||
[^:]+: 25e0741e pext {p14\.d-p15\.d}, pn8\[0\]
|
||||
[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\]
|
||||
[^:]+: 25e0741f pext {p15\.d-p0\.d}, pn8\[0\]
|
||||
[^:]+: 25e074f0 pext {p0\.d-p1\.d}, pn15\[0\]
|
||||
[^:]+: 25e07510 pext {p0\.d-p1\.d}, pn8\[1\]
|
||||
[^:]+: 25e0743c pext {p12\.d-p13\.d}, pn9\[0\]
|
||||
[^:]+: 25207810 ptrue pn8\.b
|
||||
[^:]+: 25207813 ptrue pn11\.b
|
||||
[^:]+: 25207817 ptrue pn15\.b
|
||||
[^:]+: 25607810 ptrue pn8\.h
|
||||
[^:]+: 25607811 ptrue pn9\.h
|
||||
[^:]+: 25607817 ptrue pn15\.h
|
||||
[^:]+: 25a07810 ptrue pn8\.s
|
||||
[^:]+: 25a07816 ptrue pn14\.s
|
||||
[^:]+: 25a07817 ptrue pn15\.s
|
||||
[^:]+: 25e07810 ptrue pn8\.d
|
||||
[^:]+: 25e07814 ptrue pn12\.d
|
||||
[^:]+: 25e07817 ptrue pn15\.d
|
||||
[^:]+: c1208000 sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c120801e sel {z30\.b-z31\.b}, pn8, {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c1209c00 sel {z0\.b-z1\.b}, pn15, {z0\.b-z1\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c12083c0 sel {z0\.b-z1\.b}, pn8, {z30\.b-z31\.b}, {z0\.b-z1\.b}
|
||||
[^:]+: c13e8000 sel {z0\.b-z1\.b}, pn8, {z0\.b-z1\.b}, {z30\.b-z31\.b}
|
||||
[^:]+: c12a90c2 sel {z2\.b-z3\.b}, pn12, {z6\.b-z7\.b}, {z10\.b-z11\.b}
|
||||
[^:]+: c1608000 sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c160801e sel {z30\.h-z31\.h}, pn8, {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c1609c00 sel {z0\.h-z1\.h}, pn15, {z0\.h-z1\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c16083c0 sel {z0\.h-z1\.h}, pn8, {z30\.h-z31\.h}, {z0\.h-z1\.h}
|
||||
[^:]+: c17e8000 sel {z0\.h-z1\.h}, pn8, {z0\.h-z1\.h}, {z30\.h-z31\.h}
|
||||
[^:]+: c17085cc sel {z12\.h-z13\.h}, pn9, {z14\.h-z15\.h}, {z16\.h-z17\.h}
|
||||
[^:]+: c1a08000 sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a0801e sel {z30\.s-z31\.s}, pn8, {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a09c00 sel {z0\.s-z1\.s}, pn15, {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a083c0 sel {z0\.s-z1\.s}, pn8, {z30\.s-z31\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1be8000 sel {z0\.s-z1\.s}, pn8, {z0\.s-z1\.s}, {z30\.s-z31\.s}
|
||||
[^:]+: c1b88ed2 sel {z18\.s-z19\.s}, pn11, {z22\.s-z23\.s}, {z24\.s-z25\.s}
|
||||
[^:]+: c1e08000 sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e0801e sel {z30\.d-z31\.d}, pn8, {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e09c00 sel {z0\.d-z1\.d}, pn15, {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e083c0 sel {z0\.d-z1\.d}, pn8, {z30\.d-z31\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1fe8000 sel {z0\.d-z1\.d}, pn8, {z0\.d-z1\.d}, {z30\.d-z31\.d}
|
||||
[^:]+: c1fc9b48 sel {z8\.d-z9\.d}, pn14, {z26\.d-z27\.d}, {z28\.d-z29\.d}
|
||||
[^:]+: c1218000 sel {z0\.b-z3\.b}, pn8, {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c121801c sel {z28\.b-z31\.b}, pn8, {z0\.b-z3\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c1218380 sel {z0\.b-z3\.b}, pn8, {z28\.b-z31\.b}, {z0\.b-z3\.b}
|
||||
[^:]+: c13d8000 sel {z0\.b-z3\.b}, pn8, {z0\.b-z3\.b}, {z28\.b-z31\.b}
|
||||
[^:]+: c12d8904 sel {z4\.b-z7\.b}, pn10, {z8\.b-z11\.b}, {z12\.b-z15\.b}
|
||||
[^:]+: c1618000 sel {z0\.h-z3\.h}, pn8, {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c161801c sel {z28\.h-z31\.h}, pn8, {z0\.h-z3\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c1618380 sel {z0\.h-z3\.h}, pn8, {z28\.h-z31\.h}, {z0\.h-z3\.h}
|
||||
[^:]+: c17d8000 sel {z0\.h-z3\.h}, pn8, {z0\.h-z3\.h}, {z28\.h-z31\.h}
|
||||
[^:]+: c1758a08 sel {z8\.h-z11\.h}, pn10, {z16\.h-z19\.h}, {z20\.h-z23\.h}
|
||||
[^:]+: c1a18000 sel {z0\.s-z3\.s}, pn8, {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a1801c sel {z28\.s-z31\.s}, pn8, {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a18380 sel {z0\.s-z3\.s}, pn8, {z28\.s-z31\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1bd8000 sel {z0\.s-z3\.s}, pn8, {z0\.s-z3\.s}, {z28\.s-z31\.s}
|
||||
[^:]+: c1b98a90 sel {z16\.s-z19\.s}, pn10, {z20\.s-z23\.s}, {z24\.s-z27\.s}
|
||||
[^:]+: c1e18000 sel {z0\.d-z3\.d}, pn8, {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e1801c sel {z28\.d-z31\.d}, pn8, {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e18380 sel {z0\.d-z3\.d}, pn8, {z28\.d-z31\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1fd8000 sel {z0\.d-z3\.d}, pn8, {z0\.d-z3\.d}, {z28\.d-z31\.d}
|
||||
[^:]+: c1e98894 sel {z20\.d-z23\.d}, pn10, {z4\.d-z7\.d}, {z8\.d-z11\.d}
|
||||
164
gas/testsuite/gas/aarch64/sme2-6.s
Normal file
164
gas/testsuite/gas/aarch64/sme2-6.s
Normal file
|
|
@ -0,0 +1,164 @@
|
|||
cntp x0, pn0.b, vlx2
|
||||
CNTP X0, PN0.B, VLx2
|
||||
cntp x30, pn0.b, vlx2
|
||||
cntp xzr, pn0.b, vlx2
|
||||
cntp x0, pn15.b, vlx2
|
||||
cntp x0, pn0.b, vlx4
|
||||
CNTP X11, PN13.b, VLx4
|
||||
|
||||
cntp x0, pn0.h, vlx2
|
||||
CNTP X0, PN0.H, VLx2
|
||||
cntp x30, pn0.h, vlx2
|
||||
cntp xzr, pn0.h, vlx2
|
||||
cntp x0, pn15.h, vlx2
|
||||
cntp x0, pn0.h, vlx4
|
||||
CNTP X20, PN9.h, VLx2
|
||||
|
||||
cntp x0, pn0.s, vlx2
|
||||
CNTP X0, PN0.s, VLx2
|
||||
cntp x30, pn0.s, vlx2
|
||||
cntp xzr, pn0.s, vlx2
|
||||
cntp x0, pn15.s, vlx2
|
||||
cntp x0, pn0.s, vlx4
|
||||
CNTP X15, PN8.s, VLx4
|
||||
|
||||
cntp x0, pn0.d, vlx2
|
||||
CNTP X0, PN0.d, VLx2
|
||||
cntp x30, pn0.d, vlx2
|
||||
cntp xzr, pn0.d, vlx2
|
||||
cntp x0, pn15.d, vlx2
|
||||
cntp x0, pn0.d, vlx4
|
||||
CNTP X4, PN5.d, VLx2
|
||||
|
||||
pext p0.b, pn8[0]
|
||||
PEXT P0.B, PN8[0]
|
||||
pext p15.b, pn8[0]
|
||||
pext p0.b, pn15[0]
|
||||
pext p0.b, pn8[3]
|
||||
pext p4.b, pn11[2]
|
||||
|
||||
pext p0.h, pn8[0]
|
||||
PEXT P0.H, PN8[0]
|
||||
pext p15.h, pn8[0]
|
||||
pext p0.h, pn15[0]
|
||||
pext p0.h, pn8[3]
|
||||
pext p5.h, pn14[1]
|
||||
|
||||
pext p0.s, pn8[0]
|
||||
PEXT P0.S, PN8[0]
|
||||
pext p15.s, pn8[0]
|
||||
pext p0.s, pn15[0]
|
||||
pext p0.s, pn8[3]
|
||||
pext p6.s, pn10[2]
|
||||
|
||||
pext p0.d, pn8[0]
|
||||
PEXT P0.D, PN8[0]
|
||||
pext p15.d, pn8[0]
|
||||
pext p0.d, pn15[0]
|
||||
pext p0.d, pn8[3]
|
||||
pext p7.d, pn9[1]
|
||||
|
||||
pext { p0.b, p1.b }, pn8[0]
|
||||
pext { p0.b - p1.b }, pn8[0]
|
||||
PEXT { P0.B - P1.B }, PN8[0]
|
||||
pext { p14.b - p15.b }, pn8[0]
|
||||
pext { p15.b, p0.b }, pn8[0]
|
||||
pext { p15.b - p0.b }, pn8[0]
|
||||
pext { p0.b - p1.b }, pn15[0]
|
||||
pext { p0.b - p1.b }, pn8[1]
|
||||
pext { p7.b - p8.b }, pn12[0]
|
||||
|
||||
pext { p0.h, p1.h }, pn8[0]
|
||||
pext { p0.h - p1.h }, pn8[0]
|
||||
PEXT { P0.H - P1.H }, PN8[0]
|
||||
pext { p14.h - p15.h }, pn8[0]
|
||||
pext { p15.h, p0.h }, pn8[0]
|
||||
pext { p15.h - p0.h }, pn8[0]
|
||||
pext { p0.h - p1.h }, pn15[0]
|
||||
pext { p0.h - p1.h }, pn8[1]
|
||||
pext { p2.h - p3.h }, pn14[0]
|
||||
|
||||
pext { p0.s, p1.s }, pn8[0]
|
||||
pext { p0.s - p1.s }, pn8[0]
|
||||
PEXT { P0.S - P1.S }, PN8[0]
|
||||
pext { p14.s - p15.s }, pn8[0]
|
||||
pext { p15.s, p0.s }, pn8[0]
|
||||
pext { p15.s - p0.s }, pn8[0]
|
||||
pext { p0.s - p1.s }, pn15[0]
|
||||
pext { p0.s - p1.s }, pn8[1]
|
||||
pext { p5.s - p6.s }, pn13[0]
|
||||
|
||||
pext { p0.d, p1.d }, pn8[0]
|
||||
pext { p0.d - p1.d }, pn8[0]
|
||||
PEXT { P0.D - P1.D }, PN8[0]
|
||||
pext { p14.d - p15.d }, pn8[0]
|
||||
pext { p15.d, p0.d }, pn8[0]
|
||||
pext { p15.d - p0.d }, pn8[0]
|
||||
pext { p0.d - p1.d }, pn15[0]
|
||||
pext { p0.d - p1.d }, pn8[1]
|
||||
pext { p12.d - p13.d }, pn9[0]
|
||||
|
||||
ptrue pn8.b
|
||||
ptrue pn11.b
|
||||
ptrue pn15.b
|
||||
ptrue pn8.h
|
||||
ptrue pn9.h
|
||||
ptrue pn15.h
|
||||
ptrue pn8.s
|
||||
ptrue pn14.s
|
||||
ptrue pn15.s
|
||||
ptrue pn8.d
|
||||
ptrue pn12.d
|
||||
ptrue pn15.d
|
||||
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z30.b - z31.b }, pn8, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn15, { z0.b - z1.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z30.b - z31.b }, { z0.b - z1.b }
|
||||
sel { z0.b - z1.b }, pn8, { z0.b - z1.b }, { z30.b - z31.b }
|
||||
sel { z2.b - z3.b }, pn12, { z6.b - z7.b }, { z10.b - z11.b }
|
||||
|
||||
sel { z0.h - z1.h }, pn8, { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sel { z30.h - z31.h }, pn8, { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sel { z0.h - z1.h }, pn15, { z0.h - z1.h }, { z0.h - z1.h }
|
||||
sel { z0.h - z1.h }, pn8, { z30.h - z31.h }, { z0.h - z1.h }
|
||||
sel { z0.h - z1.h }, pn8, { z0.h - z1.h }, { z30.h - z31.h }
|
||||
sel { z12.h - z13.h }, pn9, { z14.h - z15.h }, { z16.h - z17.h }
|
||||
|
||||
sel { z0.s - z1.s }, pn8, { z0.s - z1.s }, { z0.s - z1.s }
|
||||
sel { z30.s - z31.s }, pn8, { z0.s - z1.s }, { z0.s - z1.s }
|
||||
sel { z0.s - z1.s }, pn15, { z0.s - z1.s }, { z0.s - z1.s }
|
||||
sel { z0.s - z1.s }, pn8, { z30.s - z31.s }, { z0.s - z1.s }
|
||||
sel { z0.s - z1.s }, pn8, { z0.s - z1.s }, { z30.s - z31.s }
|
||||
sel { z18.s - z19.s }, pn11, { z22.s - z23.s }, { z24.s - z25.s }
|
||||
|
||||
sel { z0.d - z1.d }, pn8, { z0.d - z1.d }, { z0.d - z1.d }
|
||||
sel { z30.d - z31.d }, pn8, { z0.d - z1.d }, { z0.d - z1.d }
|
||||
sel { z0.d - z1.d }, pn15, { z0.d - z1.d }, { z0.d - z1.d }
|
||||
sel { z0.d - z1.d }, pn8, { z30.d - z31.d }, { z0.d - z1.d }
|
||||
sel { z0.d - z1.d }, pn8, { z0.d - z1.d }, { z30.d - z31.d }
|
||||
sel { z8.d - z9.d }, pn14, { z26.d - z27.d }, { z28.d - z29.d }
|
||||
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z28.b - z31.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z28.b - z31.b }, { z0.b - z3.b }
|
||||
sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z28.b - z31.b }
|
||||
sel { z4.b - z7.b }, pn10, { z8.b - z11.b }, { z12.b - z15.b }
|
||||
|
||||
sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sel { z28.h - z31.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h }
|
||||
sel { z0.h - z3.h }, pn8, { z28.h - z31.h }, { z0.h - z3.h }
|
||||
sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z28.h - z31.h }
|
||||
sel { z8.h - z11.h }, pn10, { z16.h - z19.h }, { z20.h - z23.h }
|
||||
|
||||
sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s }
|
||||
sel { z28.s - z31.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s }
|
||||
sel { z0.s - z3.s }, pn8, { z28.s - z31.s }, { z0.s - z3.s }
|
||||
sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z28.s - z31.s }
|
||||
sel { z16.s - z19.s }, pn10, { z20.s - z23.s }, { z24.s - z27.s }
|
||||
|
||||
sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d }
|
||||
sel { z28.d - z31.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d }
|
||||
sel { z0.d - z3.d }, pn8, { z28.d - z31.d }, { z0.d - z3.d }
|
||||
sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z28.d - z31.d }
|
||||
sel { z20.d - z23.d }, pn10, { z4.d - z7.d }, { z8.d - z11.d }
|
||||
3
gas/testsuite/gas/aarch64/sme2-7-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-7-invalid.d
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
#as: -march=armv8-a
|
||||
#source: sme2-7-invalid.s
|
||||
#error_output: sme2-7-invalid.l
|
||||
20
gas/testsuite/gas/aarch64/sme2-7-invalid.l
Normal file
20
gas/testsuite/gas/aarch64/sme2-7-invalid.l
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `whilege 0,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege pn8\.b,0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege pn8\.b,x0,0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,0'
|
||||
[^ :]+:[0-9]+: Error: pn8-pn15 expected at operand 1 -- `whilege pn0\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: unexpected characters following instruction at operand 3 -- `whilege p8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `whilege z8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: comma expected between operands at operand 4 -- `whilege pn8\.b,x0,x0'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege pn8\.b,w0,w0,vlx2'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: whilege pn8\.b, x0, x0, vlx2
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: whilege pn8\.h, x0, x0, vlx2
|
||||
[^ :]+:[0-9]+: Info: whilege pn8\.s, x0, x0, vlx2
|
||||
[^ :]+:[0-9]+: Info: whilege pn8\.d, x0, x0, vlx2
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege pn8\.b,sp,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege pn8\.b,x0,sp,vlx2'
|
||||
[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,#0'
|
||||
[^ :]+:[0-9]+: Error: operand 4 must be VLx2 or VLx4 -- `whilege pn8\.b,x0,x0,1'
|
||||
14
gas/testsuite/gas/aarch64/sme2-7-invalid.s
Normal file
14
gas/testsuite/gas/aarch64/sme2-7-invalid.s
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
whilege 0, x0, x0, vlx2
|
||||
whilege pn8.b, 0, x0, vlx2
|
||||
whilege pn8.b, x0, 0, vlx2
|
||||
whilege pn8.b, x0, x0, 0
|
||||
|
||||
whilege pn0.b, x0, x0, vlx2
|
||||
whilege p8.b, x0, x0, vlx2
|
||||
whilege z8.b, x0, x0, vlx2
|
||||
whilege pn8.b, x0, x0
|
||||
whilege pn8.b, w0, w0, vlx2
|
||||
whilege pn8.b, sp, x0, vlx2
|
||||
whilege pn8.b, x0, sp, vlx2
|
||||
whilege pn8.b, x0, x0, #0
|
||||
whilege pn8.b, x0, x0, 1
|
||||
3
gas/testsuite/gas/aarch64/sme2-7-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sme2-7-noarch.d
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
#as: -march=armv8-a+sme
|
||||
#source: sme2-7.s
|
||||
#error_output: sme2-7-noarch.l
|
||||
321
gas/testsuite/gas/aarch64/sme2-7-noarch.l
Normal file
321
gas/testsuite/gas/aarch64/sme2-7-noarch.l
Normal file
|
|
@ -0,0 +1,321 @@
|
|||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo pn13\.d,x26,x9,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.B,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.B,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.b,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.b,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn11\.b,x20,x1,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.h,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.h,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.h,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.h,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn14\.h,x14,x25,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.s,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.s,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.s,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.s,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn9\.s,x4,x27,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x0,vlx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.d,X0,X0,VLx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels PN8\.d,X0,X0,VLx4'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn15\.d,x0,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x30,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,xzr,x0,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,x30,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn8\.d,x0,xzr,vlx2'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels pn13\.d,x26,x9,vlx4'
|
||||
329
gas/testsuite/gas/aarch64/sme2-7.d
Normal file
329
gas/testsuite/gas/aarch64/sme2-7.d
Normal file
|
|
@ -0,0 +1,329 @@
|
|||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: 25204010 whilege pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206010 whilege pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204010 whilege pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206010 whilege pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204017 whilege pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 252043d0 whilege pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 252043f0 whilege pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4010 whilege pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4010 whilege pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 25216293 whilege pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604010 whilege pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606010 whilege pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604010 whilege pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606010 whilege pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604017 whilege pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 256043d0 whilege pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 256043f0 whilege pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4010 whilege pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4010 whilege pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 257961d6 whilege pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04010 whilege pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06010 whilege pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04010 whilege pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06010 whilege pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04017 whilege pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a043d0 whilege pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a043f0 whilege pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4010 whilege pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4010 whilege pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4091 whilege pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04010 whilege pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06010 whilege pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04010 whilege pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06010 whilege pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04017 whilege pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e043d0 whilege pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e043f0 whilege pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4010 whilege pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4010 whilege pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e96355 whilege pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204018 whilegt pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206018 whilegt pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204018 whilegt pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206018 whilegt pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 2520401f whilegt pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 252043d8 whilegt pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 252043f8 whilegt pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4018 whilegt pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4018 whilegt pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 2521629b whilegt pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604018 whilegt pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606018 whilegt pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604018 whilegt pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606018 whilegt pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 2560401f whilegt pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 256043d8 whilegt pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 256043f8 whilegt pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4018 whilegt pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4018 whilegt pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 257961de whilegt pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04018 whilegt pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06018 whilegt pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04018 whilegt pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06018 whilegt pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a0401f whilegt pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a043d8 whilegt pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a043f8 whilegt pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4018 whilegt pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4018 whilegt pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4099 whilegt pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04018 whilegt pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06018 whilegt pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04018 whilegt pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06018 whilegt pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e0401f whilegt pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e043d8 whilegt pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e043f8 whilegt pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4018 whilegt pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4018 whilegt pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e9635d whilegt pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204818 whilehi pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206818 whilehi pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204818 whilehi pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206818 whilehi pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 2520481f whilehi pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 25204bd8 whilehi pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 25204bf8 whilehi pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4818 whilehi pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4818 whilehi pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 25216a9b whilehi pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604818 whilehi pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606818 whilehi pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604818 whilehi pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606818 whilehi pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 2560481f whilehi pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 25604bd8 whilehi pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 25604bf8 whilehi pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4818 whilehi pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4818 whilehi pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 257969de whilehi pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04818 whilehi pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06818 whilehi pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04818 whilehi pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06818 whilehi pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a0481f whilehi pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a04bd8 whilehi pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a04bf8 whilehi pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4818 whilehi pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4818 whilehi pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4899 whilehi pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04818 whilehi pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06818 whilehi pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04818 whilehi pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06818 whilehi pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e0481f whilehi pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e04bd8 whilehi pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e04bf8 whilehi pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4818 whilehi pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4818 whilehi pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e96b5d whilehi pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204810 whilehs pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206810 whilehs pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204810 whilehs pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206810 whilehs pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204817 whilehs pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 25204bd0 whilehs pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 25204bf0 whilehs pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4810 whilehs pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4810 whilehs pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 25216a93 whilehs pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604810 whilehs pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606810 whilehs pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604810 whilehs pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606810 whilehs pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604817 whilehs pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 25604bd0 whilehs pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 25604bf0 whilehs pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4810 whilehs pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4810 whilehs pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 257969d6 whilehs pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04810 whilehs pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06810 whilehs pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04810 whilehs pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06810 whilehs pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04817 whilehs pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a04bd0 whilehs pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a04bf0 whilehs pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4810 whilehs pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4810 whilehs pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4891 whilehs pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04810 whilehs pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06810 whilehs pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04810 whilehs pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06810 whilehs pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04817 whilehs pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e04bd0 whilehs pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e04bf0 whilehs pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4810 whilehs pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4810 whilehs pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e96b55 whilehs pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204418 whilele pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206418 whilele pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204418 whilele pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206418 whilele pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 2520441f whilele pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 252047d8 whilele pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 252047f8 whilele pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4418 whilele pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4418 whilele pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 2521669b whilele pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604418 whilele pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606418 whilele pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604418 whilele pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606418 whilele pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 2560441f whilele pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 256047d8 whilele pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 256047f8 whilele pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4418 whilele pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4418 whilele pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 257965de whilele pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04418 whilele pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06418 whilele pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04418 whilele pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06418 whilele pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a0441f whilele pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a047d8 whilele pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a047f8 whilele pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4418 whilele pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4418 whilele pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4499 whilele pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04418 whilele pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06418 whilele pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04418 whilele pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06418 whilele pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e0441f whilele pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e047d8 whilele pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e047f8 whilele pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4418 whilele pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4418 whilele pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e9675d whilele pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204410 whilelt pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206410 whilelt pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204410 whilelt pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206410 whilelt pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204417 whilelt pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 252047d0 whilelt pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 252047f0 whilelt pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4410 whilelt pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4410 whilelt pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 25216693 whilelt pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604410 whilelt pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606410 whilelt pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604410 whilelt pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606410 whilelt pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604417 whilelt pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 256047d0 whilelt pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 256047f0 whilelt pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4410 whilelt pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4410 whilelt pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 257965d6 whilelt pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04410 whilelt pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06410 whilelt pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04410 whilelt pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06410 whilelt pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04417 whilelt pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a047d0 whilelt pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a047f0 whilelt pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4410 whilelt pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4410 whilelt pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4491 whilelt pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04410 whilelt pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06410 whilelt pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04410 whilelt pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06410 whilelt pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04417 whilelt pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e047d0 whilelt pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e047f0 whilelt pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4410 whilelt pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4410 whilelt pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e96755 whilelt pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204c10 whilelo pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206c10 whilelo pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204c10 whilelo pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206c10 whilelo pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204c17 whilelo pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 25204fd0 whilelo pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 25204ff0 whilelo pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4c10 whilelo pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4c10 whilelo pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 25216e93 whilelo pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604c10 whilelo pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606c10 whilelo pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604c10 whilelo pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606c10 whilelo pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604c17 whilelo pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 25604fd0 whilelo pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 25604ff0 whilelo pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4c10 whilelo pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4c10 whilelo pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 25796dd6 whilelo pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04c10 whilelo pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06c10 whilelo pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04c10 whilelo pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06c10 whilelo pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04c17 whilelo pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a04fd0 whilelo pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a04ff0 whilelo pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4c10 whilelo pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4c10 whilelo pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4c91 whilelo pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04c10 whilelo pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06c10 whilelo pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04c10 whilelo pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06c10 whilelo pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04c17 whilelo pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e04fd0 whilelo pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e04ff0 whilelo pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4c10 whilelo pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4c10 whilelo pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e96f55 whilelo pn13\.d, x26, x9, vlx4
|
||||
[^:]+: 25204c18 whilels pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206c18 whilels pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204c18 whilels pn8\.b, x0, x0, vlx2
|
||||
[^:]+: 25206c18 whilels pn8\.b, x0, x0, vlx4
|
||||
[^:]+: 25204c1f whilels pn15\.b, x0, x0, vlx2
|
||||
[^:]+: 25204fd8 whilels pn8\.b, x30, x0, vlx2
|
||||
[^:]+: 25204ff8 whilels pn8\.b, xzr, x0, vlx2
|
||||
[^:]+: 253e4c18 whilels pn8\.b, x0, x30, vlx2
|
||||
[^:]+: 253f4c18 whilels pn8\.b, x0, xzr, vlx2
|
||||
[^:]+: 25216e9b whilels pn11\.b, x20, x1, vlx4
|
||||
[^:]+: 25604c18 whilels pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606c18 whilels pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604c18 whilels pn8\.h, x0, x0, vlx2
|
||||
[^:]+: 25606c18 whilels pn8\.h, x0, x0, vlx4
|
||||
[^:]+: 25604c1f whilels pn15\.h, x0, x0, vlx2
|
||||
[^:]+: 25604fd8 whilels pn8\.h, x30, x0, vlx2
|
||||
[^:]+: 25604ff8 whilels pn8\.h, xzr, x0, vlx2
|
||||
[^:]+: 257e4c18 whilels pn8\.h, x0, x30, vlx2
|
||||
[^:]+: 257f4c18 whilels pn8\.h, x0, xzr, vlx2
|
||||
[^:]+: 25796dde whilels pn14\.h, x14, x25, vlx4
|
||||
[^:]+: 25a04c18 whilels pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06c18 whilels pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04c18 whilels pn8\.s, x0, x0, vlx2
|
||||
[^:]+: 25a06c18 whilels pn8\.s, x0, x0, vlx4
|
||||
[^:]+: 25a04c1f whilels pn15\.s, x0, x0, vlx2
|
||||
[^:]+: 25a04fd8 whilels pn8\.s, x30, x0, vlx2
|
||||
[^:]+: 25a04ff8 whilels pn8\.s, xzr, x0, vlx2
|
||||
[^:]+: 25be4c18 whilels pn8\.s, x0, x30, vlx2
|
||||
[^:]+: 25bf4c18 whilels pn8\.s, x0, xzr, vlx2
|
||||
[^:]+: 25bb4c99 whilels pn9\.s, x4, x27, vlx2
|
||||
[^:]+: 25e04c18 whilels pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06c18 whilels pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04c18 whilels pn8\.d, x0, x0, vlx2
|
||||
[^:]+: 25e06c18 whilels pn8\.d, x0, x0, vlx4
|
||||
[^:]+: 25e04c1f whilels pn15\.d, x0, x0, vlx2
|
||||
[^:]+: 25e04fd8 whilels pn8\.d, x30, x0, vlx2
|
||||
[^:]+: 25e04ff8 whilels pn8\.d, xzr, x0, vlx2
|
||||
[^:]+: 25fe4c18 whilels pn8\.d, x0, x30, vlx2
|
||||
[^:]+: 25ff4c18 whilels pn8\.d, x0, xzr, vlx2
|
||||
[^:]+: 25e96f5d whilels pn13\.d, x26, x9, vlx4
|
||||
351
gas/testsuite/gas/aarch64/sme2-7.s
Normal file
351
gas/testsuite/gas/aarch64/sme2-7.s
Normal file
|
|
@ -0,0 +1,351 @@
|
|||
whilege pn8.b, x0, x0, vlx2
|
||||
whilege pn8.b, x0, x0, vlx4
|
||||
WHILEGE PN8.B, X0, X0, VLx2
|
||||
WHILEGE PN8.B, X0, X0, VLx4
|
||||
whilege pn15.b, x0, x0, vlx2
|
||||
whilege pn8.b, x30, x0, vlx2
|
||||
whilege pn8.b, xzr, x0, vlx2
|
||||
whilege pn8.b, x0, x30, vlx2
|
||||
whilege pn8.b, x0, xzr, vlx2
|
||||
whilege pn11.b, x20, x1, vlx4
|
||||
|
||||
whilege pn8.h, x0, x0, vlx2
|
||||
whilege pn8.h, x0, x0, vlx4
|
||||
WHILEGE PN8.h, X0, X0, VLx2
|
||||
WHILEGE PN8.h, X0, X0, VLx4
|
||||
whilege pn15.h, x0, x0, vlx2
|
||||
whilege pn8.h, x30, x0, vlx2
|
||||
whilege pn8.h, xzr, x0, vlx2
|
||||
whilege pn8.h, x0, x30, vlx2
|
||||
whilege pn8.h, x0, xzr, vlx2
|
||||
whilege pn14.h, x14, x25, vlx4
|
||||
|
||||
whilege pn8.s, x0, x0, vlx2
|
||||
whilege pn8.s, x0, x0, vlx4
|
||||
WHILEGE PN8.s, X0, X0, VLx2
|
||||
WHILEGE PN8.s, X0, X0, VLx4
|
||||
whilege pn15.s, x0, x0, vlx2
|
||||
whilege pn8.s, x30, x0, vlx2
|
||||
whilege pn8.s, xzr, x0, vlx2
|
||||
whilege pn8.s, x0, x30, vlx2
|
||||
whilege pn8.s, x0, xzr, vlx2
|
||||
whilege pn9.s, x4, x27, vlx2
|
||||
|
||||
whilege pn8.d, x0, x0, vlx2
|
||||
whilege pn8.d, x0, x0, vlx4
|
||||
WHILEGE PN8.d, X0, X0, VLx2
|
||||
WHILEGE PN8.d, X0, X0, VLx4
|
||||
whilege pn15.d, x0, x0, vlx2
|
||||
whilege pn8.d, x30, x0, vlx2
|
||||
whilege pn8.d, xzr, x0, vlx2
|
||||
whilege pn8.d, x0, x30, vlx2
|
||||
whilege pn8.d, x0, xzr, vlx2
|
||||
whilege pn13.d, x26, x9, vlx4
|
||||
|
||||
whilegt pn8.b, x0, x0, vlx2
|
||||
whilegt pn8.b, x0, x0, vlx4
|
||||
WHILEGT PN8.B, X0, X0, VLx2
|
||||
WHILEGT PN8.B, X0, X0, VLx4
|
||||
whilegt pn15.b, x0, x0, vlx2
|
||||
whilegt pn8.b, x30, x0, vlx2
|
||||
whilegt pn8.b, xzr, x0, vlx2
|
||||
whilegt pn8.b, x0, x30, vlx2
|
||||
whilegt pn8.b, x0, xzr, vlx2
|
||||
whilegt pn11.b, x20, x1, vlx4
|
||||
|
||||
whilegt pn8.h, x0, x0, vlx2
|
||||
whilegt pn8.h, x0, x0, vlx4
|
||||
WHILEGT PN8.h, X0, X0, VLx2
|
||||
WHILEGT PN8.h, X0, X0, VLx4
|
||||
whilegt pn15.h, x0, x0, vlx2
|
||||
whilegt pn8.h, x30, x0, vlx2
|
||||
whilegt pn8.h, xzr, x0, vlx2
|
||||
whilegt pn8.h, x0, x30, vlx2
|
||||
whilegt pn8.h, x0, xzr, vlx2
|
||||
whilegt pn14.h, x14, x25, vlx4
|
||||
|
||||
whilegt pn8.s, x0, x0, vlx2
|
||||
whilegt pn8.s, x0, x0, vlx4
|
||||
WHILEGT PN8.s, X0, X0, VLx2
|
||||
WHILEGT PN8.s, X0, X0, VLx4
|
||||
whilegt pn15.s, x0, x0, vlx2
|
||||
whilegt pn8.s, x30, x0, vlx2
|
||||
whilegt pn8.s, xzr, x0, vlx2
|
||||
whilegt pn8.s, x0, x30, vlx2
|
||||
whilegt pn8.s, x0, xzr, vlx2
|
||||
whilegt pn9.s, x4, x27, vlx2
|
||||
|
||||
whilegt pn8.d, x0, x0, vlx2
|
||||
whilegt pn8.d, x0, x0, vlx4
|
||||
WHILEGT PN8.d, X0, X0, VLx2
|
||||
WHILEGT PN8.d, X0, X0, VLx4
|
||||
whilegt pn15.d, x0, x0, vlx2
|
||||
whilegt pn8.d, x30, x0, vlx2
|
||||
whilegt pn8.d, xzr, x0, vlx2
|
||||
whilegt pn8.d, x0, x30, vlx2
|
||||
whilegt pn8.d, x0, xzr, vlx2
|
||||
whilegt pn13.d, x26, x9, vlx4
|
||||
|
||||
whilehi pn8.b, x0, x0, vlx2
|
||||
whilehi pn8.b, x0, x0, vlx4
|
||||
WHILEHI PN8.B, X0, X0, VLx2
|
||||
WHILEHI PN8.B, X0, X0, VLx4
|
||||
whilehi pn15.b, x0, x0, vlx2
|
||||
whilehi pn8.b, x30, x0, vlx2
|
||||
whilehi pn8.b, xzr, x0, vlx2
|
||||
whilehi pn8.b, x0, x30, vlx2
|
||||
whilehi pn8.b, x0, xzr, vlx2
|
||||
whilehi pn11.b, x20, x1, vlx4
|
||||
|
||||
whilehi pn8.h, x0, x0, vlx2
|
||||
whilehi pn8.h, x0, x0, vlx4
|
||||
WHILEHI PN8.h, X0, X0, VLx2
|
||||
WHILEHI PN8.h, X0, X0, VLx4
|
||||
whilehi pn15.h, x0, x0, vlx2
|
||||
whilehi pn8.h, x30, x0, vlx2
|
||||
whilehi pn8.h, xzr, x0, vlx2
|
||||
whilehi pn8.h, x0, x30, vlx2
|
||||
whilehi pn8.h, x0, xzr, vlx2
|
||||
whilehi pn14.h, x14, x25, vlx4
|
||||
|
||||
whilehi pn8.s, x0, x0, vlx2
|
||||
whilehi pn8.s, x0, x0, vlx4
|
||||
WHILEHI PN8.s, X0, X0, VLx2
|
||||
WHILEHI PN8.s, X0, X0, VLx4
|
||||
whilehi pn15.s, x0, x0, vlx2
|
||||
whilehi pn8.s, x30, x0, vlx2
|
||||
whilehi pn8.s, xzr, x0, vlx2
|
||||
whilehi pn8.s, x0, x30, vlx2
|
||||
whilehi pn8.s, x0, xzr, vlx2
|
||||
whilehi pn9.s, x4, x27, vlx2
|
||||
|
||||
whilehi pn8.d, x0, x0, vlx2
|
||||
whilehi pn8.d, x0, x0, vlx4
|
||||
WHILEHI PN8.d, X0, X0, VLx2
|
||||
WHILEHI PN8.d, X0, X0, VLx4
|
||||
whilehi pn15.d, x0, x0, vlx2
|
||||
whilehi pn8.d, x30, x0, vlx2
|
||||
whilehi pn8.d, xzr, x0, vlx2
|
||||
whilehi pn8.d, x0, x30, vlx2
|
||||
whilehi pn8.d, x0, xzr, vlx2
|
||||
whilehi pn13.d, x26, x9, vlx4
|
||||
|
||||
whilehs pn8.b, x0, x0, vlx2
|
||||
whilehs pn8.b, x0, x0, vlx4
|
||||
WHILEHS PN8.B, X0, X0, VLx2
|
||||
WHILEHS PN8.B, X0, X0, VLx4
|
||||
whilehs pn15.b, x0, x0, vlx2
|
||||
whilehs pn8.b, x30, x0, vlx2
|
||||
whilehs pn8.b, xzr, x0, vlx2
|
||||
whilehs pn8.b, x0, x30, vlx2
|
||||
whilehs pn8.b, x0, xzr, vlx2
|
||||
whilehs pn11.b, x20, x1, vlx4
|
||||
|
||||
whilehs pn8.h, x0, x0, vlx2
|
||||
whilehs pn8.h, x0, x0, vlx4
|
||||
WHILEHS PN8.h, X0, X0, VLx2
|
||||
WHILEHS PN8.h, X0, X0, VLx4
|
||||
whilehs pn15.h, x0, x0, vlx2
|
||||
whilehs pn8.h, x30, x0, vlx2
|
||||
whilehs pn8.h, xzr, x0, vlx2
|
||||
whilehs pn8.h, x0, x30, vlx2
|
||||
whilehs pn8.h, x0, xzr, vlx2
|
||||
whilehs pn14.h, x14, x25, vlx4
|
||||
|
||||
whilehs pn8.s, x0, x0, vlx2
|
||||
whilehs pn8.s, x0, x0, vlx4
|
||||
WHILEHS PN8.s, X0, X0, VLx2
|
||||
WHILEHS PN8.s, X0, X0, VLx4
|
||||
whilehs pn15.s, x0, x0, vlx2
|
||||
whilehs pn8.s, x30, x0, vlx2
|
||||
whilehs pn8.s, xzr, x0, vlx2
|
||||
whilehs pn8.s, x0, x30, vlx2
|
||||
whilehs pn8.s, x0, xzr, vlx2
|
||||
whilehs pn9.s, x4, x27, vlx2
|
||||
|
||||
whilehs pn8.d, x0, x0, vlx2
|
||||
whilehs pn8.d, x0, x0, vlx4
|
||||
WHILEHS PN8.d, X0, X0, VLx2
|
||||
WHILEHS PN8.d, X0, X0, VLx4
|
||||
whilehs pn15.d, x0, x0, vlx2
|
||||
whilehs pn8.d, x30, x0, vlx2
|
||||
whilehs pn8.d, xzr, x0, vlx2
|
||||
whilehs pn8.d, x0, x30, vlx2
|
||||
whilehs pn8.d, x0, xzr, vlx2
|
||||
whilehs pn13.d, x26, x9, vlx4
|
||||
|
||||
whilele pn8.b, x0, x0, vlx2
|
||||
whilele pn8.b, x0, x0, vlx4
|
||||
WHILELE PN8.B, X0, X0, VLx2
|
||||
WHILELE PN8.B, X0, X0, VLx4
|
||||
whilele pn15.b, x0, x0, vlx2
|
||||
whilele pn8.b, x30, x0, vlx2
|
||||
whilele pn8.b, xzr, x0, vlx2
|
||||
whilele pn8.b, x0, x30, vlx2
|
||||
whilele pn8.b, x0, xzr, vlx2
|
||||
whilele pn11.b, x20, x1, vlx4
|
||||
|
||||
whilele pn8.h, x0, x0, vlx2
|
||||
whilele pn8.h, x0, x0, vlx4
|
||||
WHILELE PN8.h, X0, X0, VLx2
|
||||
WHILELE PN8.h, X0, X0, VLx4
|
||||
whilele pn15.h, x0, x0, vlx2
|
||||
whilele pn8.h, x30, x0, vlx2
|
||||
whilele pn8.h, xzr, x0, vlx2
|
||||
whilele pn8.h, x0, x30, vlx2
|
||||
whilele pn8.h, x0, xzr, vlx2
|
||||
whilele pn14.h, x14, x25, vlx4
|
||||
|
||||
whilele pn8.s, x0, x0, vlx2
|
||||
whilele pn8.s, x0, x0, vlx4
|
||||
WHILELE PN8.s, X0, X0, VLx2
|
||||
WHILELE PN8.s, X0, X0, VLx4
|
||||
whilele pn15.s, x0, x0, vlx2
|
||||
whilele pn8.s, x30, x0, vlx2
|
||||
whilele pn8.s, xzr, x0, vlx2
|
||||
whilele pn8.s, x0, x30, vlx2
|
||||
whilele pn8.s, x0, xzr, vlx2
|
||||
whilele pn9.s, x4, x27, vlx2
|
||||
|
||||
whilele pn8.d, x0, x0, vlx2
|
||||
whilele pn8.d, x0, x0, vlx4
|
||||
WHILELE PN8.d, X0, X0, VLx2
|
||||
WHILELE PN8.d, X0, X0, VLx4
|
||||
whilele pn15.d, x0, x0, vlx2
|
||||
whilele pn8.d, x30, x0, vlx2
|
||||
whilele pn8.d, xzr, x0, vlx2
|
||||
whilele pn8.d, x0, x30, vlx2
|
||||
whilele pn8.d, x0, xzr, vlx2
|
||||
whilele pn13.d, x26, x9, vlx4
|
||||
|
||||
whilelt pn8.b, x0, x0, vlx2
|
||||
whilelt pn8.b, x0, x0, vlx4
|
||||
WHILELT PN8.B, X0, X0, VLx2
|
||||
WHILELT PN8.B, X0, X0, VLx4
|
||||
whilelt pn15.b, x0, x0, vlx2
|
||||
whilelt pn8.b, x30, x0, vlx2
|
||||
whilelt pn8.b, xzr, x0, vlx2
|
||||
whilelt pn8.b, x0, x30, vlx2
|
||||
whilelt pn8.b, x0, xzr, vlx2
|
||||
whilelt pn11.b, x20, x1, vlx4
|
||||
|
||||
whilelt pn8.h, x0, x0, vlx2
|
||||
whilelt pn8.h, x0, x0, vlx4
|
||||
WHILELT PN8.h, X0, X0, VLx2
|
||||
WHILELT PN8.h, X0, X0, VLx4
|
||||
whilelt pn15.h, x0, x0, vlx2
|
||||
whilelt pn8.h, x30, x0, vlx2
|
||||
whilelt pn8.h, xzr, x0, vlx2
|
||||
whilelt pn8.h, x0, x30, vlx2
|
||||
whilelt pn8.h, x0, xzr, vlx2
|
||||
whilelt pn14.h, x14, x25, vlx4
|
||||
|
||||
whilelt pn8.s, x0, x0, vlx2
|
||||
whilelt pn8.s, x0, x0, vlx4
|
||||
WHILELT PN8.s, X0, X0, VLx2
|
||||
WHILELT PN8.s, X0, X0, VLx4
|
||||
whilelt pn15.s, x0, x0, vlx2
|
||||
whilelt pn8.s, x30, x0, vlx2
|
||||
whilelt pn8.s, xzr, x0, vlx2
|
||||
whilelt pn8.s, x0, x30, vlx2
|
||||
whilelt pn8.s, x0, xzr, vlx2
|
||||
whilelt pn9.s, x4, x27, vlx2
|
||||
|
||||
whilelt pn8.d, x0, x0, vlx2
|
||||
whilelt pn8.d, x0, x0, vlx4
|
||||
WHILELT PN8.d, X0, X0, VLx2
|
||||
WHILELT PN8.d, X0, X0, VLx4
|
||||
whilelt pn15.d, x0, x0, vlx2
|
||||
whilelt pn8.d, x30, x0, vlx2
|
||||
whilelt pn8.d, xzr, x0, vlx2
|
||||
whilelt pn8.d, x0, x30, vlx2
|
||||
whilelt pn8.d, x0, xzr, vlx2
|
||||
whilelt pn13.d, x26, x9, vlx4
|
||||
|
||||
whilelo pn8.b, x0, x0, vlx2
|
||||
whilelo pn8.b, x0, x0, vlx4
|
||||
WHILELO PN8.B, X0, X0, VLx2
|
||||
WHILELO PN8.B, X0, X0, VLx4
|
||||
whilelo pn15.b, x0, x0, vlx2
|
||||
whilelo pn8.b, x30, x0, vlx2
|
||||
whilelo pn8.b, xzr, x0, vlx2
|
||||
whilelo pn8.b, x0, x30, vlx2
|
||||
whilelo pn8.b, x0, xzr, vlx2
|
||||
whilelo pn11.b, x20, x1, vlx4
|
||||
|
||||
whilelo pn8.h, x0, x0, vlx2
|
||||
whilelo pn8.h, x0, x0, vlx4
|
||||
WHILELO PN8.h, X0, X0, VLx2
|
||||
WHILELO PN8.h, X0, X0, VLx4
|
||||
whilelo pn15.h, x0, x0, vlx2
|
||||
whilelo pn8.h, x30, x0, vlx2
|
||||
whilelo pn8.h, xzr, x0, vlx2
|
||||
whilelo pn8.h, x0, x30, vlx2
|
||||
whilelo pn8.h, x0, xzr, vlx2
|
||||
whilelo pn14.h, x14, x25, vlx4
|
||||
|
||||
whilelo pn8.s, x0, x0, vlx2
|
||||
whilelo pn8.s, x0, x0, vlx4
|
||||
WHILELO PN8.s, X0, X0, VLx2
|
||||
WHILELO PN8.s, X0, X0, VLx4
|
||||
whilelo pn15.s, x0, x0, vlx2
|
||||
whilelo pn8.s, x30, x0, vlx2
|
||||
whilelo pn8.s, xzr, x0, vlx2
|
||||
whilelo pn8.s, x0, x30, vlx2
|
||||
whilelo pn8.s, x0, xzr, vlx2
|
||||
whilelo pn9.s, x4, x27, vlx2
|
||||
|
||||
whilelo pn8.d, x0, x0, vlx2
|
||||
whilelo pn8.d, x0, x0, vlx4
|
||||
WHILELO PN8.d, X0, X0, VLx2
|
||||
WHILELO PN8.d, X0, X0, VLx4
|
||||
whilelo pn15.d, x0, x0, vlx2
|
||||
whilelo pn8.d, x30, x0, vlx2
|
||||
whilelo pn8.d, xzr, x0, vlx2
|
||||
whilelo pn8.d, x0, x30, vlx2
|
||||
whilelo pn8.d, x0, xzr, vlx2
|
||||
whilelo pn13.d, x26, x9, vlx4
|
||||
|
||||
whilels pn8.b, x0, x0, vlx2
|
||||
whilels pn8.b, x0, x0, vlx4
|
||||
WHILELS PN8.B, X0, X0, VLx2
|
||||
WHILELS PN8.B, X0, X0, VLx4
|
||||
whilels pn15.b, x0, x0, vlx2
|
||||
whilels pn8.b, x30, x0, vlx2
|
||||
whilels pn8.b, xzr, x0, vlx2
|
||||
whilels pn8.b, x0, x30, vlx2
|
||||
whilels pn8.b, x0, xzr, vlx2
|
||||
whilels pn11.b, x20, x1, vlx4
|
||||
|
||||
whilels pn8.h, x0, x0, vlx2
|
||||
whilels pn8.h, x0, x0, vlx4
|
||||
WHILELS PN8.h, X0, X0, VLx2
|
||||
WHILELS PN8.h, X0, X0, VLx4
|
||||
whilels pn15.h, x0, x0, vlx2
|
||||
whilels pn8.h, x30, x0, vlx2
|
||||
whilels pn8.h, xzr, x0, vlx2
|
||||
whilels pn8.h, x0, x30, vlx2
|
||||
whilels pn8.h, x0, xzr, vlx2
|
||||
whilels pn14.h, x14, x25, vlx4
|
||||
|
||||
whilels pn8.s, x0, x0, vlx2
|
||||
whilels pn8.s, x0, x0, vlx4
|
||||
WHILELS PN8.s, X0, X0, VLx2
|
||||
WHILELS PN8.s, X0, X0, VLx4
|
||||
whilels pn15.s, x0, x0, vlx2
|
||||
whilels pn8.s, x30, x0, vlx2
|
||||
whilels pn8.s, xzr, x0, vlx2
|
||||
whilels pn8.s, x0, x30, vlx2
|
||||
whilels pn8.s, x0, xzr, vlx2
|
||||
whilels pn9.s, x4, x27, vlx2
|
||||
|
||||
whilels pn8.d, x0, x0, vlx2
|
||||
whilels pn8.d, x0, x0, vlx4
|
||||
WHILELS PN8.d, X0, X0, VLx2
|
||||
WHILELS PN8.d, X0, X0, VLx4
|
||||
whilels pn15.d, x0, x0, vlx2
|
||||
whilels pn8.d, x30, x0, vlx2
|
||||
whilels pn8.d, xzr, x0, vlx2
|
||||
whilels pn8.d, x0, x30, vlx2
|
||||
whilels pn8.d, x0, xzr, vlx2
|
||||
whilels pn13.d, x26, x9, vlx4
|
||||
|
|
@ -1,4 +1,7 @@
|
|||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel 0,pn0,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate-as-counter register at operand 2 -- `psel pn0,0,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 3 -- `psel pn0,pn0,0'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-counter rather than predicate-as-mask register at operand 2 -- `psel pn0,p0,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: expected an SVE predicate register at operand 1 -- `psel pn,pn0,p0\.b\[w12,0\]'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 3 -- `psel p0,p0,pn0\.b\[w12,0\]'
|
||||
|
|
|
|||
|
|
@ -1,3 +1,7 @@
|
|||
psel 0, pn0, p0.b[w12, 0]
|
||||
psel pn0, 0, p0.b[w12, 0]
|
||||
psel pn0, pn0, 0
|
||||
|
||||
psel pn0, p0, p0.b[w12, 0]
|
||||
psel pn, pn0, p0.b[w12, 0]
|
||||
psel p0, p0, pn0.b[w12, 0]
|
||||
|
|
|
|||
3
gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.d
Normal file
3
gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.d
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
#as: -march=armv8-a
|
||||
#source: sve2-sme2-2-invalid.s
|
||||
#error_output: sve2-sme2-2-invalid.l
|
||||
25
gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l
Normal file
25
gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.l
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `whilege {p1\.b-p2\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b-p2\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 1 -- `whilege {p0\.b-p3\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `whilege {p15\.b-p0\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: the register list must have a stride of 1 at operand 1 -- `whilege {p0\.b,p8\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: expected a predicate-as-mask rather than predicate-as-counter register at operand 1 -- `whilege {pn0\.b-pn1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 1 -- `whilege {p0-p1},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege {p0\.q-p1\.q},x0,x0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.b-p1\.b}, x0, x0
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.h-p1\.h}, x0, x0
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.s-p1\.s}, x0, x0
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.d-p1\.d}, x0, x0
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `whilege {p0\.b-p1\.b},w0,w0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.b-p1\.b}, x0, x0
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.h-p1\.h}, x0, x0
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.s-p1\.s}, x0, x0
|
||||
[^ :]+:[0-9]+: Info: whilege {p0\.d-p1\.d}, x0, x0
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 2 -- `whilege {p0\.b-p1\.b},sp,x0'
|
||||
[^ :]+:[0-9]+: Error: expected an integer or zero register at operand 3 -- `whilege {p0\.b-p1\.b},x0,sp'
|
||||
12
gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s
Normal file
12
gas/testsuite/gas/aarch64/sve2-sme2-2-invalid.s
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
whilege { p0.b }, x0, x0
|
||||
whilege { p1.b - p2.b }, x0, x0
|
||||
whilege { p0.b - p2.b }, x0, x0
|
||||
whilege { p0.b - p3.b }, x0, x0
|
||||
whilege { p15.b - p0.b }, x0, x0
|
||||
whilege { p0.b, p8.b }, x0, x0
|
||||
whilege { pn0.b - pn1.b }, x0, x0
|
||||
whilege { p0 - p1 }, x0, x0
|
||||
whilege { p0.q - p1.q }, x0, x0
|
||||
whilege { p0.b - p1.b }, w0, w0
|
||||
whilege { p0.b - p1.b }, sp, x0
|
||||
whilege { p0.b - p1.b }, x0, sp
|
||||
3
gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d
Normal file
3
gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.d
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
#as: -march=armv8-a+sme
|
||||
#source: sve2-sme2-2.s
|
||||
#error_output: sve2-sme2-2-noarch.l
|
||||
257
gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l
Normal file
257
gas/testsuite/gas/aarch64/sve2-sme2-2-noarch.l
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilege {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilegt {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehi {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilehs {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilele {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelo {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilels {p4\.d-p5\.d},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.B-P1\.B},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.b-p15\.b},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.b-p1\.b},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.b-p5\.b},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.h-P1\.h},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.h-p15\.h},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.h-p1\.h},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.h-p5\.h},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.s-P1\.s},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.s-p15\.s},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.s-p1\.s},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.s-p5\.s},x17,x19'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {P0\.d-P1\.d},X0,X0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p14\.d-p15\.d},x0,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x30,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},xzr,x0'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,x30'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p0\.d-p1\.d},x0,xzr'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `whilelt {p4\.d-p5\.d},x17,x19'
|
||||
265
gas/testsuite/gas/aarch64/sve2-sme2-2.d
Normal file
265
gas/testsuite/gas/aarch64/sve2-sme2-2.d
Normal file
|
|
@ -0,0 +1,265 @@
|
|||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: 25205010 whilege {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205010 whilege {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 2520501e whilege {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 252053d0 whilege {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 252053f0 whilege {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5010 whilege {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5010 whilege {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335234 whilege {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605010 whilege {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605010 whilege {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 2560501e whilege {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 256053d0 whilege {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 256053f0 whilege {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5010 whilege {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5010 whilege {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735234 whilege {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05010 whilege {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05010 whilege {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a0501e whilege {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a053d0 whilege {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a053f0 whilege {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5010 whilege {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5010 whilege {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35234 whilege {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05010 whilege {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05010 whilege {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e0501e whilege {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e053d0 whilege {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e053f0 whilege {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5010 whilege {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5010 whilege {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35234 whilege {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205011 whilegt {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205011 whilegt {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 2520501f whilegt {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 252053d1 whilegt {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 252053f1 whilegt {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5011 whilegt {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5011 whilegt {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335235 whilegt {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605011 whilegt {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605011 whilegt {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 2560501f whilegt {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 256053d1 whilegt {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 256053f1 whilegt {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5011 whilegt {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5011 whilegt {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735235 whilegt {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05011 whilegt {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05011 whilegt {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a0501f whilegt {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a053d1 whilegt {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a053f1 whilegt {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5011 whilegt {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5011 whilegt {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35235 whilegt {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05011 whilegt {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05011 whilegt {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e0501f whilegt {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e053d1 whilegt {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e053f1 whilegt {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5011 whilegt {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5011 whilegt {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35235 whilegt {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205811 whilehi {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205811 whilehi {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 2520581f whilehi {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 25205bd1 whilehi {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 25205bf1 whilehi {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5811 whilehi {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5811 whilehi {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335a35 whilehi {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605811 whilehi {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605811 whilehi {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 2560581f whilehi {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 25605bd1 whilehi {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 25605bf1 whilehi {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5811 whilehi {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5811 whilehi {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735a35 whilehi {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05811 whilehi {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05811 whilehi {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a0581f whilehi {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a05bd1 whilehi {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a05bf1 whilehi {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5811 whilehi {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5811 whilehi {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35a35 whilehi {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05811 whilehi {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05811 whilehi {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e0581f whilehi {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e05bd1 whilehi {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e05bf1 whilehi {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5811 whilehi {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5811 whilehi {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35a35 whilehi {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205810 whilehs {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205810 whilehs {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 2520581e whilehs {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 25205bd0 whilehs {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 25205bf0 whilehs {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5810 whilehs {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5810 whilehs {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335a34 whilehs {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605810 whilehs {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605810 whilehs {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 2560581e whilehs {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 25605bd0 whilehs {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 25605bf0 whilehs {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5810 whilehs {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5810 whilehs {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735a34 whilehs {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05810 whilehs {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05810 whilehs {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a0581e whilehs {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a05bd0 whilehs {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a05bf0 whilehs {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5810 whilehs {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5810 whilehs {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35a34 whilehs {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05810 whilehs {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05810 whilehs {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e0581e whilehs {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e05bd0 whilehs {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e05bf0 whilehs {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5810 whilehs {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5810 whilehs {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35a34 whilehs {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205411 whilele {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205411 whilele {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 2520541f whilele {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 252057d1 whilele {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 252057f1 whilele {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5411 whilele {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5411 whilele {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335635 whilele {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605411 whilele {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605411 whilele {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 2560541f whilele {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 256057d1 whilele {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 256057f1 whilele {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5411 whilele {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5411 whilele {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735635 whilele {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05411 whilele {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05411 whilele {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a0541f whilele {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a057d1 whilele {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a057f1 whilele {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5411 whilele {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5411 whilele {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35635 whilele {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05411 whilele {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05411 whilele {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e0541f whilele {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e057d1 whilele {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e057f1 whilele {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5411 whilele {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5411 whilele {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35635 whilele {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205c10 whilelo {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205c10 whilelo {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205c1e whilelo {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 25205fd0 whilelo {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 25205ff0 whilelo {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5c10 whilelo {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5c10 whilelo {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335e34 whilelo {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605c10 whilelo {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605c10 whilelo {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605c1e whilelo {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 25605fd0 whilelo {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 25605ff0 whilelo {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5c10 whilelo {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5c10 whilelo {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735e34 whilelo {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05c10 whilelo {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05c10 whilelo {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05c1e whilelo {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a05fd0 whilelo {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a05ff0 whilelo {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5c10 whilelo {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5c10 whilelo {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35e34 whilelo {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05c10 whilelo {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05c10 whilelo {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05c1e whilelo {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e05fd0 whilelo {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e05ff0 whilelo {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5c10 whilelo {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5c10 whilelo {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35e34 whilelo {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205c11 whilels {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205c11 whilels {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205c1f whilels {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 25205fd1 whilels {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 25205ff1 whilels {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5c11 whilels {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5c11 whilels {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335e35 whilels {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605c11 whilels {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605c11 whilels {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605c1f whilels {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 25605fd1 whilels {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 25605ff1 whilels {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5c11 whilels {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5c11 whilels {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735e35 whilels {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05c11 whilels {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05c11 whilels {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05c1f whilels {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a05fd1 whilels {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a05ff1 whilels {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5c11 whilels {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5c11 whilels {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35e35 whilels {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05c11 whilels {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05c11 whilels {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05c1f whilels {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e05fd1 whilels {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e05ff1 whilels {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5c11 whilels {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5c11 whilels {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35e35 whilels {p4\.d-p5\.d}, x17, x19
|
||||
[^:]+: 25205410 whilelt {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 25205410 whilelt {p0\.b-p1\.b}, x0, x0
|
||||
[^:]+: 2520541e whilelt {p14\.b-p15\.b}, x0, x0
|
||||
[^:]+: 252057d0 whilelt {p0\.b-p1\.b}, x30, x0
|
||||
[^:]+: 252057f0 whilelt {p0\.b-p1\.b}, xzr, x0
|
||||
[^:]+: 253e5410 whilelt {p0\.b-p1\.b}, x0, x30
|
||||
[^:]+: 253f5410 whilelt {p0\.b-p1\.b}, x0, xzr
|
||||
[^:]+: 25335634 whilelt {p4\.b-p5\.b}, x17, x19
|
||||
[^:]+: 25605410 whilelt {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 25605410 whilelt {p0\.h-p1\.h}, x0, x0
|
||||
[^:]+: 2560541e whilelt {p14\.h-p15\.h}, x0, x0
|
||||
[^:]+: 256057d0 whilelt {p0\.h-p1\.h}, x30, x0
|
||||
[^:]+: 256057f0 whilelt {p0\.h-p1\.h}, xzr, x0
|
||||
[^:]+: 257e5410 whilelt {p0\.h-p1\.h}, x0, x30
|
||||
[^:]+: 257f5410 whilelt {p0\.h-p1\.h}, x0, xzr
|
||||
[^:]+: 25735634 whilelt {p4\.h-p5\.h}, x17, x19
|
||||
[^:]+: 25a05410 whilelt {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a05410 whilelt {p0\.s-p1\.s}, x0, x0
|
||||
[^:]+: 25a0541e whilelt {p14\.s-p15\.s}, x0, x0
|
||||
[^:]+: 25a057d0 whilelt {p0\.s-p1\.s}, x30, x0
|
||||
[^:]+: 25a057f0 whilelt {p0\.s-p1\.s}, xzr, x0
|
||||
[^:]+: 25be5410 whilelt {p0\.s-p1\.s}, x0, x30
|
||||
[^:]+: 25bf5410 whilelt {p0\.s-p1\.s}, x0, xzr
|
||||
[^:]+: 25b35634 whilelt {p4\.s-p5\.s}, x17, x19
|
||||
[^:]+: 25e05410 whilelt {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e05410 whilelt {p0\.d-p1\.d}, x0, x0
|
||||
[^:]+: 25e0541e whilelt {p14\.d-p15\.d}, x0, x0
|
||||
[^:]+: 25e057d0 whilelt {p0\.d-p1\.d}, x30, x0
|
||||
[^:]+: 25e057f0 whilelt {p0\.d-p1\.d}, xzr, x0
|
||||
[^:]+: 25fe5410 whilelt {p0\.d-p1\.d}, x0, x30
|
||||
[^:]+: 25ff5410 whilelt {p0\.d-p1\.d}, x0, xzr
|
||||
[^:]+: 25f35634 whilelt {p4\.d-p5\.d}, x17, x19
|
||||
287
gas/testsuite/gas/aarch64/sve2-sme2-2.s
Normal file
287
gas/testsuite/gas/aarch64/sve2-sme2-2.s
Normal file
|
|
@ -0,0 +1,287 @@
|
|||
whilege { p0.b - p1.b }, x0, x0
|
||||
WHILEGE { P0.B - P1.B }, X0, X0
|
||||
whilege { p14.b - p15.b }, x0, x0
|
||||
whilege { p0.b - p1.b }, x30, x0
|
||||
whilege { p0.b - p1.b }, xzr, x0
|
||||
whilege { p0.b - p1.b }, x0, x30
|
||||
whilege { p0.b - p1.b }, x0, xzr
|
||||
whilege { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilege { p0.h - p1.h }, x0, x0
|
||||
WHILEGE { P0.h - P1.h }, X0, X0
|
||||
whilege { p14.h - p15.h }, x0, x0
|
||||
whilege { p0.h - p1.h }, x30, x0
|
||||
whilege { p0.h - p1.h }, xzr, x0
|
||||
whilege { p0.h - p1.h }, x0, x30
|
||||
whilege { p0.h - p1.h }, x0, xzr
|
||||
whilege { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilege { p0.s - p1.s }, x0, x0
|
||||
WHILEGE { P0.s - P1.s }, X0, X0
|
||||
whilege { p14.s - p15.s }, x0, x0
|
||||
whilege { p0.s - p1.s }, x30, x0
|
||||
whilege { p0.s - p1.s }, xzr, x0
|
||||
whilege { p0.s - p1.s }, x0, x30
|
||||
whilege { p0.s - p1.s }, x0, xzr
|
||||
whilege { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilege { p0.d - p1.d }, x0, x0
|
||||
WHILEGE { P0.d - P1.d }, X0, X0
|
||||
whilege { p14.d - p15.d }, x0, x0
|
||||
whilege { p0.d - p1.d }, x30, x0
|
||||
whilege { p0.d - p1.d }, xzr, x0
|
||||
whilege { p0.d - p1.d }, x0, x30
|
||||
whilege { p0.d - p1.d }, x0, xzr
|
||||
whilege { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilegt { p0.b - p1.b }, x0, x0
|
||||
WHILEGT { P0.B - P1.B }, X0, X0
|
||||
whilegt { p14.b - p15.b }, x0, x0
|
||||
whilegt { p0.b - p1.b }, x30, x0
|
||||
whilegt { p0.b - p1.b }, xzr, x0
|
||||
whilegt { p0.b - p1.b }, x0, x30
|
||||
whilegt { p0.b - p1.b }, x0, xzr
|
||||
whilegt { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilegt { p0.h - p1.h }, x0, x0
|
||||
WHILEGT { P0.h - P1.h }, X0, X0
|
||||
whilegt { p14.h - p15.h }, x0, x0
|
||||
whilegt { p0.h - p1.h }, x30, x0
|
||||
whilegt { p0.h - p1.h }, xzr, x0
|
||||
whilegt { p0.h - p1.h }, x0, x30
|
||||
whilegt { p0.h - p1.h }, x0, xzr
|
||||
whilegt { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilegt { p0.s - p1.s }, x0, x0
|
||||
WHILEGT { P0.s - P1.s }, X0, X0
|
||||
whilegt { p14.s - p15.s }, x0, x0
|
||||
whilegt { p0.s - p1.s }, x30, x0
|
||||
whilegt { p0.s - p1.s }, xzr, x0
|
||||
whilegt { p0.s - p1.s }, x0, x30
|
||||
whilegt { p0.s - p1.s }, x0, xzr
|
||||
whilegt { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilegt { p0.d - p1.d }, x0, x0
|
||||
WHILEGT { P0.d - P1.d }, X0, X0
|
||||
whilegt { p14.d - p15.d }, x0, x0
|
||||
whilegt { p0.d - p1.d }, x30, x0
|
||||
whilegt { p0.d - p1.d }, xzr, x0
|
||||
whilegt { p0.d - p1.d }, x0, x30
|
||||
whilegt { p0.d - p1.d }, x0, xzr
|
||||
whilegt { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilehi { p0.b - p1.b }, x0, x0
|
||||
WHILEHI { P0.B - P1.B }, X0, X0
|
||||
whilehi { p14.b - p15.b }, x0, x0
|
||||
whilehi { p0.b - p1.b }, x30, x0
|
||||
whilehi { p0.b - p1.b }, xzr, x0
|
||||
whilehi { p0.b - p1.b }, x0, x30
|
||||
whilehi { p0.b - p1.b }, x0, xzr
|
||||
whilehi { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilehi { p0.h - p1.h }, x0, x0
|
||||
WHILEHI { P0.h - P1.h }, X0, X0
|
||||
whilehi { p14.h - p15.h }, x0, x0
|
||||
whilehi { p0.h - p1.h }, x30, x0
|
||||
whilehi { p0.h - p1.h }, xzr, x0
|
||||
whilehi { p0.h - p1.h }, x0, x30
|
||||
whilehi { p0.h - p1.h }, x0, xzr
|
||||
whilehi { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilehi { p0.s - p1.s }, x0, x0
|
||||
WHILEHI { P0.s - P1.s }, X0, X0
|
||||
whilehi { p14.s - p15.s }, x0, x0
|
||||
whilehi { p0.s - p1.s }, x30, x0
|
||||
whilehi { p0.s - p1.s }, xzr, x0
|
||||
whilehi { p0.s - p1.s }, x0, x30
|
||||
whilehi { p0.s - p1.s }, x0, xzr
|
||||
whilehi { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilehi { p0.d - p1.d }, x0, x0
|
||||
WHILEHI { P0.d - P1.d }, X0, X0
|
||||
whilehi { p14.d - p15.d }, x0, x0
|
||||
whilehi { p0.d - p1.d }, x30, x0
|
||||
whilehi { p0.d - p1.d }, xzr, x0
|
||||
whilehi { p0.d - p1.d }, x0, x30
|
||||
whilehi { p0.d - p1.d }, x0, xzr
|
||||
whilehi { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilehs { p0.b - p1.b }, x0, x0
|
||||
WHILEHS { P0.B - P1.B }, X0, X0
|
||||
whilehs { p14.b - p15.b }, x0, x0
|
||||
whilehs { p0.b - p1.b }, x30, x0
|
||||
whilehs { p0.b - p1.b }, xzr, x0
|
||||
whilehs { p0.b - p1.b }, x0, x30
|
||||
whilehs { p0.b - p1.b }, x0, xzr
|
||||
whilehs { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilehs { p0.h - p1.h }, x0, x0
|
||||
WHILEHS { P0.h - P1.h }, X0, X0
|
||||
whilehs { p14.h - p15.h }, x0, x0
|
||||
whilehs { p0.h - p1.h }, x30, x0
|
||||
whilehs { p0.h - p1.h }, xzr, x0
|
||||
whilehs { p0.h - p1.h }, x0, x30
|
||||
whilehs { p0.h - p1.h }, x0, xzr
|
||||
whilehs { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilehs { p0.s - p1.s }, x0, x0
|
||||
WHILEHS { P0.s - P1.s }, X0, X0
|
||||
whilehs { p14.s - p15.s }, x0, x0
|
||||
whilehs { p0.s - p1.s }, x30, x0
|
||||
whilehs { p0.s - p1.s }, xzr, x0
|
||||
whilehs { p0.s - p1.s }, x0, x30
|
||||
whilehs { p0.s - p1.s }, x0, xzr
|
||||
whilehs { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilehs { p0.d - p1.d }, x0, x0
|
||||
WHILEHS { P0.d - P1.d }, X0, X0
|
||||
whilehs { p14.d - p15.d }, x0, x0
|
||||
whilehs { p0.d - p1.d }, x30, x0
|
||||
whilehs { p0.d - p1.d }, xzr, x0
|
||||
whilehs { p0.d - p1.d }, x0, x30
|
||||
whilehs { p0.d - p1.d }, x0, xzr
|
||||
whilehs { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilele { p0.b - p1.b }, x0, x0
|
||||
WHILELE { P0.B - P1.B }, X0, X0
|
||||
whilele { p14.b - p15.b }, x0, x0
|
||||
whilele { p0.b - p1.b }, x30, x0
|
||||
whilele { p0.b - p1.b }, xzr, x0
|
||||
whilele { p0.b - p1.b }, x0, x30
|
||||
whilele { p0.b - p1.b }, x0, xzr
|
||||
whilele { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilele { p0.h - p1.h }, x0, x0
|
||||
WHILELE { P0.h - P1.h }, X0, X0
|
||||
whilele { p14.h - p15.h }, x0, x0
|
||||
whilele { p0.h - p1.h }, x30, x0
|
||||
whilele { p0.h - p1.h }, xzr, x0
|
||||
whilele { p0.h - p1.h }, x0, x30
|
||||
whilele { p0.h - p1.h }, x0, xzr
|
||||
whilele { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilele { p0.s - p1.s }, x0, x0
|
||||
WHILELE { P0.s - P1.s }, X0, X0
|
||||
whilele { p14.s - p15.s }, x0, x0
|
||||
whilele { p0.s - p1.s }, x30, x0
|
||||
whilele { p0.s - p1.s }, xzr, x0
|
||||
whilele { p0.s - p1.s }, x0, x30
|
||||
whilele { p0.s - p1.s }, x0, xzr
|
||||
whilele { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilele { p0.d - p1.d }, x0, x0
|
||||
WHILELE { P0.d - P1.d }, X0, X0
|
||||
whilele { p14.d - p15.d }, x0, x0
|
||||
whilele { p0.d - p1.d }, x30, x0
|
||||
whilele { p0.d - p1.d }, xzr, x0
|
||||
whilele { p0.d - p1.d }, x0, x30
|
||||
whilele { p0.d - p1.d }, x0, xzr
|
||||
whilele { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilelo { p0.b - p1.b }, x0, x0
|
||||
WHILELO { P0.B - P1.B }, X0, X0
|
||||
whilelo { p14.b - p15.b }, x0, x0
|
||||
whilelo { p0.b - p1.b }, x30, x0
|
||||
whilelo { p0.b - p1.b }, xzr, x0
|
||||
whilelo { p0.b - p1.b }, x0, x30
|
||||
whilelo { p0.b - p1.b }, x0, xzr
|
||||
whilelo { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilelo { p0.h - p1.h }, x0, x0
|
||||
WHILELO { P0.h - P1.h }, X0, X0
|
||||
whilelo { p14.h - p15.h }, x0, x0
|
||||
whilelo { p0.h - p1.h }, x30, x0
|
||||
whilelo { p0.h - p1.h }, xzr, x0
|
||||
whilelo { p0.h - p1.h }, x0, x30
|
||||
whilelo { p0.h - p1.h }, x0, xzr
|
||||
whilelo { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilelo { p0.s - p1.s }, x0, x0
|
||||
WHILELO { P0.s - P1.s }, X0, X0
|
||||
whilelo { p14.s - p15.s }, x0, x0
|
||||
whilelo { p0.s - p1.s }, x30, x0
|
||||
whilelo { p0.s - p1.s }, xzr, x0
|
||||
whilelo { p0.s - p1.s }, x0, x30
|
||||
whilelo { p0.s - p1.s }, x0, xzr
|
||||
whilelo { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilelo { p0.d - p1.d }, x0, x0
|
||||
WHILELO { P0.d - P1.d }, X0, X0
|
||||
whilelo { p14.d - p15.d }, x0, x0
|
||||
whilelo { p0.d - p1.d }, x30, x0
|
||||
whilelo { p0.d - p1.d }, xzr, x0
|
||||
whilelo { p0.d - p1.d }, x0, x30
|
||||
whilelo { p0.d - p1.d }, x0, xzr
|
||||
whilelo { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilels { p0.b - p1.b }, x0, x0
|
||||
WHILELS { P0.B - P1.B }, X0, X0
|
||||
whilels { p14.b - p15.b }, x0, x0
|
||||
whilels { p0.b - p1.b }, x30, x0
|
||||
whilels { p0.b - p1.b }, xzr, x0
|
||||
whilels { p0.b - p1.b }, x0, x30
|
||||
whilels { p0.b - p1.b }, x0, xzr
|
||||
whilels { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilels { p0.h - p1.h }, x0, x0
|
||||
WHILELS { P0.h - P1.h }, X0, X0
|
||||
whilels { p14.h - p15.h }, x0, x0
|
||||
whilels { p0.h - p1.h }, x30, x0
|
||||
whilels { p0.h - p1.h }, xzr, x0
|
||||
whilels { p0.h - p1.h }, x0, x30
|
||||
whilels { p0.h - p1.h }, x0, xzr
|
||||
whilels { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilels { p0.s - p1.s }, x0, x0
|
||||
WHILELS { P0.s - P1.s }, X0, X0
|
||||
whilels { p14.s - p15.s }, x0, x0
|
||||
whilels { p0.s - p1.s }, x30, x0
|
||||
whilels { p0.s - p1.s }, xzr, x0
|
||||
whilels { p0.s - p1.s }, x0, x30
|
||||
whilels { p0.s - p1.s }, x0, xzr
|
||||
whilels { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilels { p0.d - p1.d }, x0, x0
|
||||
WHILELS { P0.d - P1.d }, X0, X0
|
||||
whilels { p14.d - p15.d }, x0, x0
|
||||
whilels { p0.d - p1.d }, x30, x0
|
||||
whilels { p0.d - p1.d }, xzr, x0
|
||||
whilels { p0.d - p1.d }, x0, x30
|
||||
whilels { p0.d - p1.d }, x0, xzr
|
||||
whilels { p4.d - p5.d }, x17, x19
|
||||
|
||||
whilelt { p0.b - p1.b }, x0, x0
|
||||
WHILELT { P0.B - P1.B }, X0, X0
|
||||
whilelt { p14.b - p15.b }, x0, x0
|
||||
whilelt { p0.b - p1.b }, x30, x0
|
||||
whilelt { p0.b - p1.b }, xzr, x0
|
||||
whilelt { p0.b - p1.b }, x0, x30
|
||||
whilelt { p0.b - p1.b }, x0, xzr
|
||||
whilelt { p4.b - p5.b }, x17, x19
|
||||
|
||||
whilelt { p0.h - p1.h }, x0, x0
|
||||
WHILELT { P0.h - P1.h }, X0, X0
|
||||
whilelt { p14.h - p15.h }, x0, x0
|
||||
whilelt { p0.h - p1.h }, x30, x0
|
||||
whilelt { p0.h - p1.h }, xzr, x0
|
||||
whilelt { p0.h - p1.h }, x0, x30
|
||||
whilelt { p0.h - p1.h }, x0, xzr
|
||||
whilelt { p4.h - p5.h }, x17, x19
|
||||
|
||||
whilelt { p0.s - p1.s }, x0, x0
|
||||
WHILELT { P0.s - P1.s }, X0, X0
|
||||
whilelt { p14.s - p15.s }, x0, x0
|
||||
whilelt { p0.s - p1.s }, x30, x0
|
||||
whilelt { p0.s - p1.s }, xzr, x0
|
||||
whilelt { p0.s - p1.s }, x0, x30
|
||||
whilelt { p0.s - p1.s }, x0, xzr
|
||||
whilelt { p4.s - p5.s }, x17, x19
|
||||
|
||||
whilelt { p0.d - p1.d }, x0, x0
|
||||
WHILELT { P0.d - P1.d }, X0, X0
|
||||
whilelt { p14.d - p15.d }, x0, x0
|
||||
whilelt { p0.d - p1.d }, x30, x0
|
||||
whilelt { p0.d - p1.d }, xzr, x0
|
||||
whilelt { p0.d - p1.d }, x0, x30
|
||||
whilelt { p0.d - p1.d }, x0, xzr
|
||||
whilelt { p4.d - p5.d }, x17, x19
|
||||
|
|
@ -487,6 +487,8 @@ enum aarch64_opnd
|
|||
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
|
||||
AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
|
||||
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
|
||||
AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
|
||||
AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
|
||||
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
|
||||
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
|
||||
AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
|
||||
|
|
@ -497,8 +499,14 @@ enum aarch64_opnd
|
|||
AARCH64_OPND_SME_ZA_HV_idx_srcxN, /* SME N source ZA tile vectors. */
|
||||
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
|
||||
AARCH64_OPND_SME_ZA_HV_idx_destxN, /* SME N dest ZA tile vectors. */
|
||||
AARCH64_OPND_SME_Pdx2, /* Predicate register list in [3:1]. */
|
||||
AARCH64_OPND_SME_PdxN, /* Predicate register list in [3:0]. */
|
||||
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
|
||||
AARCH64_OPND_SME_PNd3, /* Predicate-as-counter register, bits [3:0]. */
|
||||
AARCH64_OPND_SME_PNg3, /* Predicate-as-counter register, bits [12:10]. */
|
||||
AARCH64_OPND_SME_PNn, /* Predicate-as-counter register, bits [8:5]. */
|
||||
AARCH64_OPND_SME_PNn3_INDEX1, /* Indexed pred-as-counter reg, bits [8:5]. */
|
||||
AARCH64_OPND_SME_PNn3_INDEX2, /* Indexed pred-as-counter reg, bits [9:5]. */
|
||||
AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
|
||||
AARCH64_OPND_SME_ZA_HV_idx_ldstr, /* SME destination ZA tile vector. */
|
||||
AARCH64_OPND_SME_ZA_array_off3_0, /* SME ZA[<Wv>{, #<imm3>}]. */
|
||||
|
|
@ -507,6 +515,8 @@ enum aarch64_opnd
|
|||
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
|
||||
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
|
||||
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
|
||||
AARCH64_OPND_SME_VLxN_10, /* VLx2 or VLx4, in bit 10. */
|
||||
AARCH64_OPND_SME_VLxN_13, /* VLx2 or VLx4, in bit 13. */
|
||||
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
|
||||
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
|
||||
AARCH64_OPND_MOPS_ADDR_Rd, /* [Rd]!, in bits [0, 4]. */
|
||||
|
|
@ -1559,6 +1569,7 @@ aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
|
|||
|
||||
extern const char *const aarch64_sve_pattern_array[32];
|
||||
extern const char *const aarch64_sve_prfop_array[16];
|
||||
extern const char *const aarch64_sme_vlxn_array[2];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
|
|
@ -667,10 +667,12 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 203:
|
||||
case 209:
|
||||
case 212:
|
||||
case 220:
|
||||
case 221:
|
||||
case 226:
|
||||
case 227:
|
||||
case 222:
|
||||
case 223:
|
||||
case 230:
|
||||
case 231:
|
||||
case 232:
|
||||
case 233:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 15:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
|
|
@ -682,7 +684,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 237:
|
||||
case 247:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
|
|
@ -727,10 +729,12 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
case 192:
|
||||
case 193:
|
||||
case 194:
|
||||
case 228:
|
||||
case 236:
|
||||
case 241:
|
||||
case 242:
|
||||
case 244:
|
||||
case 245:
|
||||
case 246:
|
||||
case 251:
|
||||
case 252:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
|
|
@ -889,35 +893,42 @@ aarch64_insert_operand (const aarch64_operand *self,
|
|||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 211:
|
||||
case 213:
|
||||
case 229:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
case 214:
|
||||
case 215:
|
||||
case 216:
|
||||
case 217:
|
||||
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
|
||||
case 218:
|
||||
case 219:
|
||||
case 228:
|
||||
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
|
||||
case 220:
|
||||
case 221:
|
||||
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
|
||||
case 222:
|
||||
case 224:
|
||||
case 229:
|
||||
case 226:
|
||||
case 237:
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 223:
|
||||
case 225:
|
||||
case 227:
|
||||
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
|
||||
case 230:
|
||||
case 231:
|
||||
case 232:
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 233:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 234:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 235:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
return aarch64_ins_simple_index (self, info, code, inst, errors);
|
||||
case 238:
|
||||
case 239:
|
||||
case 240:
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 241:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 242:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 243:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
case 248:
|
||||
case 249:
|
||||
case 250:
|
||||
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -57,6 +57,25 @@ insert_fields (aarch64_insn *code, aarch64_insn value, aarch64_insn mask, ...)
|
|||
va_end (va);
|
||||
}
|
||||
|
||||
/* Insert a raw field value VALUE into all fields in SELF->fields after START.
|
||||
The least significant bit goes in the final field. */
|
||||
|
||||
static void
|
||||
insert_all_fields_after (const aarch64_operand *self, unsigned int start,
|
||||
aarch64_insn *code, aarch64_insn value)
|
||||
{
|
||||
unsigned int i;
|
||||
enum aarch64_field_kind kind;
|
||||
|
||||
for (i = ARRAY_SIZE (self->fields); i-- > start; )
|
||||
if (self->fields[i] != FLD_NIL)
|
||||
{
|
||||
kind = self->fields[i];
|
||||
insert_field (kind, code, value, 0);
|
||||
value >>= fields[kind].width;
|
||||
}
|
||||
}
|
||||
|
||||
/* Insert a raw field value VALUE into all fields in SELF->fields.
|
||||
The least significant bit goes in the final field. */
|
||||
|
||||
|
|
@ -64,16 +83,7 @@ static void
|
|||
insert_all_fields (const aarch64_operand *self, aarch64_insn *code,
|
||||
aarch64_insn value)
|
||||
{
|
||||
unsigned int i;
|
||||
enum aarch64_field_kind kind;
|
||||
|
||||
for (i = ARRAY_SIZE (self->fields); i-- > 0; )
|
||||
if (self->fields[i] != FLD_NIL)
|
||||
{
|
||||
kind = self->fields[i];
|
||||
insert_field (kind, code, value, 0);
|
||||
value >>= fields[kind].width;
|
||||
}
|
||||
return insert_all_fields_after (self, 0, code, value);
|
||||
}
|
||||
|
||||
/* Operand inserters. */
|
||||
|
|
@ -1595,6 +1605,21 @@ aarch64_ins_x0_to_x30 (const aarch64_operand *self,
|
|||
return true;
|
||||
}
|
||||
|
||||
/* Insert an indexed register, with the first field being the register
|
||||
number and the remaining fields being the index. */
|
||||
bool
|
||||
aarch64_ins_simple_index (const aarch64_operand *self,
|
||||
const aarch64_opnd_info *info,
|
||||
aarch64_insn *code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int bias = get_operand_specific_data (self);
|
||||
insert_field (self->fields[0], code, info->reglane.regno - bias, 0);
|
||||
insert_all_fields_after (self, 1, code, info->reglane.index);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Miscellaneous encoding functions. */
|
||||
|
||||
/* Encode size[0], i.e. bit 22, for
|
||||
|
|
|
|||
|
|
@ -110,6 +110,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sme_pred_reg_with_index);
|
|||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate1);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_imm_rotate2);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_x0_to_x30);
|
||||
AARCH64_DECL_OPD_INSERTER (ins_simple_index);
|
||||
|
||||
#undef AARCH64_DECL_OPD_INSERTER
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -168,18 +168,20 @@ extract_fields (aarch64_insn code, aarch64_insn mask, ...)
|
|||
return value;
|
||||
}
|
||||
|
||||
/* Extract the value of all fields in SELF->fields from instruction CODE.
|
||||
The least significant bit comes from the final field. */
|
||||
/* Extract the value of all fields in SELF->fields after START from
|
||||
instruction CODE. The least significant bit comes from the final field. */
|
||||
|
||||
static aarch64_insn
|
||||
extract_all_fields (const aarch64_operand *self, aarch64_insn code)
|
||||
extract_all_fields_after (const aarch64_operand *self, unsigned int start,
|
||||
aarch64_insn code)
|
||||
{
|
||||
aarch64_insn value;
|
||||
unsigned int i;
|
||||
enum aarch64_field_kind kind;
|
||||
|
||||
value = 0;
|
||||
for (i = 0; i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
|
||||
for (i = start;
|
||||
i < ARRAY_SIZE (self->fields) && self->fields[i] != FLD_NIL; ++i)
|
||||
{
|
||||
kind = self->fields[i];
|
||||
value <<= fields[kind].width;
|
||||
|
|
@ -188,6 +190,15 @@ extract_all_fields (const aarch64_operand *self, aarch64_insn code)
|
|||
return value;
|
||||
}
|
||||
|
||||
/* Extract the value of all fields in SELF->fields from instruction CODE.
|
||||
The least significant bit comes from the final field. */
|
||||
|
||||
static aarch64_insn
|
||||
extract_all_fields (const aarch64_operand *self, aarch64_insn code)
|
||||
{
|
||||
return extract_all_fields_after (self, 0, code);
|
||||
}
|
||||
|
||||
/* Sign-extend bit I of VALUE. */
|
||||
static inline uint64_t
|
||||
sign_extend (aarch64_insn value, unsigned i)
|
||||
|
|
@ -2126,6 +2137,20 @@ aarch64_ext_x0_to_x30 (const aarch64_operand *self, aarch64_opnd_info *info,
|
|||
info->reg.regno = extract_field (self->fields[0], code, 0);
|
||||
return info->reg.regno <= 30;
|
||||
}
|
||||
|
||||
/* Decode an indexed register, with the first field being the register
|
||||
number and the remaining fields being the index. */
|
||||
bool
|
||||
aarch64_ext_simple_index (const aarch64_operand *self, aarch64_opnd_info *info,
|
||||
const aarch64_insn code,
|
||||
const aarch64_inst *inst ATTRIBUTE_UNUSED,
|
||||
aarch64_operand_error *errors ATTRIBUTE_UNUSED)
|
||||
{
|
||||
int bias = get_operand_specific_data (self);
|
||||
info->reglane.regno = extract_field (self->fields[0], code, 0) + bias;
|
||||
info->reglane.index = extract_all_fields_after (self, 1, code);
|
||||
return true;
|
||||
}
|
||||
|
||||
/* Bitfields that are commonly used to encode certain operands' information
|
||||
may be partially used as part of the base opcode in some instructions.
|
||||
|
|
|
|||
|
|
@ -134,6 +134,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sme_pred_reg_with_index);
|
|||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate1);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_imm_rotate2);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_x0_to_x30);
|
||||
AARCH64_DECL_OPD_EXTRACTOR (ext_simple_index);
|
||||
|
||||
#undef AARCH64_DECL_OPD_EXTRACTOR
|
||||
|
||||
|
|
|
|||
|
|
@ -240,6 +240,8 @@ const struct aarch64_operand aarch64_operands[] =
|
|||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
|
||||
|
|
@ -250,8 +252,14 @@ const struct aarch64_operand aarch64_operands[] =
|
|||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_srcxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_5}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_destxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_V,FLD_SME_Rv,FLD_imm3_0}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Pdx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pdx2}, "a list of SVE predicate registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_PdxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pd}, "a list of SVE predicate registers"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SME_PNd3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNd3}, "an SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SME_PNg3", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pg3}, "an SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_PRED_REG, "SME_PNn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Pn}, "an SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm1_8}, "an indexed SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_PNn3, FLD_imm2_8}, "an indexed SVE predicate-as-counter register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "a list of 64-bit ZA element tiles"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_HV_idx_ldstr", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_22,FLD_index2,FLD_SME_V,FLD_SME_Rv,FLD_imm4_0}, "an SME horizontal or vertical vector access register"},
|
||||
{AARCH64_OPND_CLASS_ZA_ACCESS, "SME_ZA_array_off3_0", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rv,FLD_imm3_0}, "ZA array"},
|
||||
|
|
@ -260,6 +268,8 @@ const struct aarch64_operand aarch64_operands[] =
|
|||
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
|
||||
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_10}, "VLx2 or VLx4"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_VLxN_13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_VL_13}, "VLx2 or VLx4"},
|
||||
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_5}, "a 16-bit unsigned immediate for TME tcancel"},
|
||||
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
|
||||
{AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"},
|
||||
|
|
|
|||
|
|
@ -99,6 +99,13 @@ const char *const aarch64_sve_prfop_array[16] = {
|
|||
0
|
||||
};
|
||||
|
||||
/* Vector length multiples for a predicate-as-counter operand. Used in things
|
||||
like AARCH64_OPND_SME_VLxN_10. */
|
||||
const char *const aarch64_sme_vlxn_array[2] = {
|
||||
"vlx2",
|
||||
"vlx4"
|
||||
};
|
||||
|
||||
/* Helper functions to determine which operand to be used to encode/decode
|
||||
the size:Q fields for AdvSIMD instructions. */
|
||||
|
||||
|
|
@ -220,15 +227,22 @@ const aarch64_field fields[] =
|
|||
{ 10, 5 }, /* Rt2: in load/store pair instructions. */
|
||||
{ 12, 1 }, /* S: in load/store reg offset instructions. */
|
||||
{ 12, 2 }, /* SM3_imm2: Indexed element SM3 2 bits index immediate. */
|
||||
{ 1, 3 }, /* SME_Pdx2: predicate register, multiple of 2, [3:1]. */
|
||||
{ 13, 3 }, /* SME_Pm: second source scalable predicate register P0-P7. */
|
||||
{ 0, 3 }, /* SME_PNd3: PN0-PN7, bits [2:0]. */
|
||||
{ 5, 3 }, /* SME_PNn3: PN0-PN7, bits [7:5]. */
|
||||
{ 16, 1 }, /* SME_Q: Q class bit, bit 16. */
|
||||
{ 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
|
||||
{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
|
||||
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
|
||||
{ 10, 1 }, /* SME_VL_10: VLx2 or VLx4, bit [10]. */
|
||||
{ 13, 1 }, /* SME_VL_13: VLx2 or VLx4, bit [13]. */
|
||||
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
|
||||
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
|
||||
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
|
||||
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
|
||||
{ 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */
|
||||
{ 18, 3 }, /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */
|
||||
{ 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
|
||||
{ 7, 3 }, /* SME_Zn4: Z0-Z31, multiple of 4, bits [9:7]. */
|
||||
{ 4, 1 }, /* SME_ZtT: upper bit of Zt, bit [4]. */
|
||||
|
|
@ -303,6 +317,8 @@ const aarch64_field fields[] =
|
|||
{ 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
|
||||
{ 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
|
||||
{ 21, 2 }, /* hw: in move wide constant instructions. */
|
||||
{ 8, 1 }, /* imm1_8: general immediate in bits [8]. */
|
||||
{ 8, 2 }, /* imm2_8: general immediate in bits [9:8]. */
|
||||
{ 0, 3 }, /* imm3_0: general immediate in bits [2:0]. */
|
||||
{ 5, 3 }, /* imm3_5: general immediate in bits [7:5]. */
|
||||
{ 10, 3 }, /* imm3_10: in add/sub extended reg instructions. */
|
||||
|
|
@ -1720,6 +1736,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_PNn3_INDEX1:
|
||||
case AARCH64_OPND_SME_PNn3_INDEX2:
|
||||
size = get_operand_field_width (get_operand_from_code (type), 1);
|
||||
if (!check_reglane (opnd, mismatch_detail, idx, "pn", 8, 15,
|
||||
0, (1 << size) - 1))
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_PnT_Wm_imm:
|
||||
size = aarch64_get_qualifier_esize (opnd->qualifier);
|
||||
max_value = 16 / size - 1;
|
||||
|
|
@ -1736,8 +1760,11 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
case AARCH64_OPND_CLASS_SVE_REGLIST:
|
||||
switch (type)
|
||||
{
|
||||
case AARCH64_OPND_SME_Pdx2:
|
||||
case AARCH64_OPND_SME_Zdnx2:
|
||||
case AARCH64_OPND_SME_Zdnx4:
|
||||
case AARCH64_OPND_SME_Zmx2:
|
||||
case AARCH64_OPND_SME_Zmx4:
|
||||
case AARCH64_OPND_SME_Znx2:
|
||||
case AARCH64_OPND_SME_Znx4:
|
||||
num = get_operand_specific_data (&aarch64_operands[type]);
|
||||
|
|
@ -1767,6 +1794,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_PdxN:
|
||||
case AARCH64_OPND_SVE_ZnxN:
|
||||
case AARCH64_OPND_SVE_ZtxN:
|
||||
num = get_opcode_dependent_value (opcode);
|
||||
|
|
@ -1825,6 +1853,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
|||
case AARCH64_OPND_CLASS_PRED_REG:
|
||||
switch (type)
|
||||
{
|
||||
case AARCH64_OPND_SME_PNd3:
|
||||
case AARCH64_OPND_SME_PNg3:
|
||||
if (opnd->reg.regno < 8)
|
||||
{
|
||||
|
|
@ -3366,10 +3395,11 @@ static void
|
|||
print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
|
||||
const char *prefix, struct aarch64_styler *styler)
|
||||
{
|
||||
const int mask = (prefix[0] == 'p' ? 15 : 31);
|
||||
const int num_regs = opnd->reglist.num_regs;
|
||||
const int stride = opnd->reglist.stride;
|
||||
const int first_reg = opnd->reglist.first_regno;
|
||||
const int last_reg = (first_reg + (num_regs - 1) * stride) & 0x1f;
|
||||
const int last_reg = (first_reg + (num_regs - 1) * stride) & mask;
|
||||
const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
|
||||
char tb[16]; /* Temporary buffer. */
|
||||
|
||||
|
|
@ -3394,9 +3424,9 @@ print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
|
|||
else
|
||||
{
|
||||
const int reg0 = first_reg;
|
||||
const int reg1 = (first_reg + stride) & 0x1f;
|
||||
const int reg2 = (first_reg + stride * 2) & 0x1f;
|
||||
const int reg3 = (first_reg + stride * 3) & 0x1f;
|
||||
const int reg1 = (first_reg + stride) & mask;
|
||||
const int reg2 = (first_reg + stride * 2) & mask;
|
||||
const int reg3 = (first_reg + stride * 3) & mask;
|
||||
|
||||
switch (num_regs)
|
||||
{
|
||||
|
|
@ -3774,7 +3804,9 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
case AARCH64_OPND_SVE_PNg4_10:
|
||||
case AARCH64_OPND_SVE_PNn:
|
||||
case AARCH64_OPND_SVE_PNt:
|
||||
case AARCH64_OPND_SME_PNd3:
|
||||
case AARCH64_OPND_SME_PNg3:
|
||||
case AARCH64_OPND_SME_PNn:
|
||||
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
|
||||
snprintf (buf, size, "%s",
|
||||
style_reg (styler, "pn%d", opnd->reg.regno));
|
||||
|
|
@ -3789,6 +3821,18 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
aarch64_get_qualifier_name (opnd->qualifier)));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_Pdx2:
|
||||
case AARCH64_OPND_SME_PdxN:
|
||||
print_register_list (buf, size, opnd, "p", styler);
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_PNn3_INDEX1:
|
||||
case AARCH64_OPND_SME_PNn3_INDEX2:
|
||||
snprintf (buf, size, "%s[%s]",
|
||||
style_reg (styler, "pn%d", opnd->reglane.regno),
|
||||
style_imm (styler, "%" PRIi64, opnd->reglane.index));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SVE_Za_5:
|
||||
case AARCH64_OPND_SVE_Za_16:
|
||||
case AARCH64_OPND_SVE_Zd:
|
||||
|
|
@ -3808,6 +3852,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
case AARCH64_OPND_SVE_ZtxN:
|
||||
case AARCH64_OPND_SME_Zdnx2:
|
||||
case AARCH64_OPND_SME_Zdnx4:
|
||||
case AARCH64_OPND_SME_Zmx2:
|
||||
case AARCH64_OPND_SME_Zmx4:
|
||||
case AARCH64_OPND_SME_Znx2:
|
||||
case AARCH64_OPND_SME_Znx4:
|
||||
case AARCH64_OPND_SME_Ztx2_STRIDED:
|
||||
|
|
@ -3902,6 +3948,14 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
|||
style_imm (styler, "%" PRIi64, opnd->indexed_za.index.imm));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_VLxN_10:
|
||||
case AARCH64_OPND_SME_VLxN_13:
|
||||
enum_value = opnd->imm.value;
|
||||
assert (enum_value < ARRAY_SIZE (aarch64_sme_vlxn_array));
|
||||
snprintf (buf, size, "%s",
|
||||
style_sub_mnem (styler, aarch64_sme_vlxn_array[enum_value]));
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_CRn:
|
||||
case AARCH64_OPND_CRm:
|
||||
snprintf (buf, size, "%s",
|
||||
|
|
|
|||
|
|
@ -48,15 +48,22 @@ enum aarch64_field_kind
|
|||
FLD_Rt2,
|
||||
FLD_S,
|
||||
FLD_SM3_imm2,
|
||||
FLD_SME_Pdx2,
|
||||
FLD_SME_Pm,
|
||||
FLD_SME_PNd3,
|
||||
FLD_SME_PNn3,
|
||||
FLD_SME_Q,
|
||||
FLD_SME_Rm,
|
||||
FLD_SME_Rv,
|
||||
FLD_SME_V,
|
||||
FLD_SME_VL_10,
|
||||
FLD_SME_VL_13,
|
||||
FLD_SME_ZAda_2b,
|
||||
FLD_SME_ZAda_3b,
|
||||
FLD_SME_Zdn2,
|
||||
FLD_SME_Zdn4,
|
||||
FLD_SME_Zm2,
|
||||
FLD_SME_Zm4,
|
||||
FLD_SME_Zn2,
|
||||
FLD_SME_Zn4,
|
||||
FLD_SME_ZtT,
|
||||
|
|
@ -131,6 +138,8 @@ enum aarch64_field_kind
|
|||
FLD_cond2,
|
||||
FLD_defgh,
|
||||
FLD_hw,
|
||||
FLD_imm1_8,
|
||||
FLD_imm2_8,
|
||||
FLD_imm3_0,
|
||||
FLD_imm3_5,
|
||||
FLD_imm3_10,
|
||||
|
|
|
|||
|
|
@ -2138,6 +2138,13 @@
|
|||
QLF3(S_S,X,X), \
|
||||
QLF3(S_D,X,X), \
|
||||
}
|
||||
#define OP_SVE_VXXU_BHSD \
|
||||
{ \
|
||||
QLF4(S_B,X,X,NIL), \
|
||||
QLF4(S_H,X,X,NIL), \
|
||||
QLF4(S_S,X,X,NIL), \
|
||||
QLF4(S_D,X,X,NIL), \
|
||||
}
|
||||
#define OP_SVE_VZVD_BHS \
|
||||
{ \
|
||||
QLF4(S_B,P_Z,S_B,S_D), \
|
||||
|
|
@ -2185,6 +2192,13 @@
|
|||
QLF3(S_S,P_Z,S_S), \
|
||||
QLF3(S_D,P_Z,S_D), \
|
||||
}
|
||||
#define OP_SVE_V_BHSD \
|
||||
{ \
|
||||
QLF1(S_B), \
|
||||
QLF1(S_H), \
|
||||
QLF1(S_S), \
|
||||
QLF1(S_D), \
|
||||
}
|
||||
#define OP_SVE_V_HSD \
|
||||
{ \
|
||||
QLF1(S_H), \
|
||||
|
|
@ -5285,7 +5299,18 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_Pd, SVE_Pg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
|
||||
SME_INSN ("psel", 0x25204000, 0xff20c210, sme_psel, 0, OP3 (SVE_PNd, SVE_PNg4_10, SME_PnT_Wm_imm), OP_SVE_NN_BHSD, 0, 0),
|
||||
|
||||
/* SME2 extensions to SVE2. */
|
||||
SME2_INSN ("whilege", 0x25205010, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilegt", 0x25205011, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilehi", 0x25205811, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilehs", 0x25205810, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilele", 0x25205411, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilelo", 0x25205c10, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilels", 0x25205c11, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
|
||||
/* SME2 extensions to SME. */
|
||||
SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
|
|
@ -5366,6 +5391,11 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
|
||||
SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
|
||||
SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
|
||||
SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
|
||||
SME2_INSN ("pext", 0x25207410, 0xff3ffe10, sme_size_22, 0, OP2 (SME_PdxN, SME_PNn3_INDEX1), OP_SVE_VU_BHSD, F_OD (2), 0),
|
||||
SME2_INSN ("ptrue", 0x25207810, 0xff3ffff8, sme_size_22, 0, OP1 (SME_PNd3), OP_SVE_V_BHSD, 0, 0),
|
||||
SME2_INSN ("sel", 0xc1208000, 0xff21e021, sme_size_22, 0, OP4 (SME_Zdnx2, SME_PNg3, SME_Znx2, SME_Zmx2), OP_SVE_VUVV_BHSD, 0, 0),
|
||||
SME2_INSN ("sel", 0xc1218000, 0xff23e063, sme_size_22, 0, OP4 (SME_Zdnx4, SME_PNg3, SME_Znx4, SME_Zmx4), OP_SVE_VUVV_BHSD, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa0600000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa0608000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BUU, 0, 0),
|
||||
SME2_INSN ("st1b", 0xa1600000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BUU, 0, 0),
|
||||
|
|
@ -5430,6 +5460,14 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
SME2_INSN ("stnt1w", 0xa020c001, 0xffe0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilehs", 0x25204810, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilele", 0x25204418, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilelo", 0x25204c10, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilels", 0x25204c18, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilelt", 0x25204410, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
|
||||
/* SIMD Dot Product (optional in v8.2-A). */
|
||||
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
|
||||
|
|
@ -6074,6 +6112,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
F(FLD_SME_Zdn2), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zdn4), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zm2), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zm4), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx2", 2 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zn2), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
|
||||
|
|
@ -6100,10 +6142,24 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
Y(ZA_ACCESS, sme_za_hv_tiles_range, "SME_ZA_HV_idx_destxN", 0, \
|
||||
F(FLD_SME_V,FLD_SME_Rv,FLD_imm3_0), \
|
||||
"an SME horizontal or vertical vector access register") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Pdx2", 2 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Pdx2), "a list of SVE predicate registers") \
|
||||
Y(SVE_REGLIST, sve_reglist, "SME_PdxN", 0, F(FLD_SVE_Pd), \
|
||||
"a list of SVE predicate registers") \
|
||||
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
|
||||
"an SVE predicate register") \
|
||||
Y(PRED_REG, regno, "SME_PNd3", 8 << OPD_F_OD_LSB, F(FLD_SME_PNd3), \
|
||||
"an SVE predicate-as-counter register") \
|
||||
Y(PRED_REG, regno, "SME_PNg3", 8 << OPD_F_OD_LSB, F(FLD_SVE_Pg3), \
|
||||
"an SVE predicate-as-counter register") \
|
||||
Y(PRED_REG, regno, "SME_PNn", 0, F(FLD_SVE_Pn), \
|
||||
"an SVE predicate-as-counter register") \
|
||||
Y(SVE_REG, simple_index, "SME_PNn3_INDEX1", 8 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_PNn3, FLD_imm1_8), \
|
||||
"an indexed SVE predicate-as-counter register") \
|
||||
Y(SVE_REG, simple_index, "SME_PNn3_INDEX2", 8 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_PNn3, FLD_imm2_8), \
|
||||
"an indexed SVE predicate-as-counter register") \
|
||||
Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
|
||||
F(FLD_SME_zero_mask), "a list of 64-bit ZA element tiles") \
|
||||
Y(ZA_ACCESS, sme_za_hv_tiles, "SME_ZA_HV_idx_ldstr", 0, \
|
||||
|
|
@ -6122,6 +6178,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
|||
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
|
||||
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
|
||||
"Source scalable predicate register with index ") \
|
||||
Y(IMMEDIATE, imm, "SME_VLxN_10", 0, F(FLD_SME_VL_10), \
|
||||
"VLx2 or VLx4") \
|
||||
Y(IMMEDIATE, imm, "SME_VLxN_13", 0, F(FLD_SME_VL_13), \
|
||||
"VLx2 or VLx4") \
|
||||
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16_5), \
|
||||
"a 16-bit unsigned immediate for TME tcancel") \
|
||||
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue