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Assorted fixes to pinsrw, pextrw, pmovmskb, movmskp, maskmovq.

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This commit is contained in:
Alan Modra 2001-05-04 11:10:55 +00:00
parent cac1532771
commit 992aaec9a9
8 changed files with 57 additions and 23 deletions
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7
gas/testsuite/ChangeLog
View file

@ -1,3 +1,10 @@
2001-05-04 Alan Modra <amodra@one.net.au>
* gas/i386/katmai.d: Correct pmovmskb and pextrw opcodes.
* gas/i386/ssemmx2.d: Likewise. Correct register for pextrw,
pinsrw, and pmovmskb.
* gas/i386/sse2.d: Correct register for movmskpd.
2001-05-02 Johan Rydberg <jrydberg@opencores.org> 2001-05-02 Johan Rydberg <jrydberg@opencores.org>
* gas/openrisc/addi.s: New file. * gas/openrisc/addi.s: New file.

4
gas/testsuite/gas/i386/katmai.d
View file

@ -135,7 +135,7 @@ Disassembly of section .text:
1e4: 0f e0 0a [ ]*pavgb \(%edx\),%mm1 1e4: 0f e0 0a [ ]*pavgb \(%edx\),%mm1
1e7: 0f e3 d3 [ ]*pavgw %mm3,%mm2 1e7: 0f e3 d3 [ ]*pavgw %mm3,%mm2
1ea: 0f e3 1c 24 [ ]*pavgw \(%esp,1\),%mm3 1ea: 0f e3 1c 24 [ ]*pavgw \(%esp,1\),%mm3
1ee: 0f c5 c8 00 [ ]*pextrw \$0x0,%mm1,%eax 1ee: 0f c5 c1 00 [ ]*pextrw \$0x0,%mm1,%eax
1f2: 0f c4 09 01 [ ]*pinsrw \$0x1,\(%ecx\),%mm1 1f2: 0f c4 09 01 [ ]*pinsrw \$0x1,\(%ecx\),%mm1
1f6: 0f c4 d2 02 [ ]*pinsrw \$0x2,%edx,%mm2 1f6: 0f c4 d2 02 [ ]*pinsrw \$0x2,%edx,%mm2
1fa: 0f ee c1 [ ]*pmaxsw %mm1,%mm0 1fa: 0f ee c1 [ ]*pmaxsw %mm1,%mm0
@ -146,7 +146,7 @@ Disassembly of section .text:
20a: 0f ea 2e [ ]*pminsw \(%esi\),%mm5 20a: 0f ea 2e [ ]*pminsw \(%esi\),%mm5
20d: 0f da f7 [ ]*pminub %mm7,%mm6 20d: 0f da f7 [ ]*pminub %mm7,%mm6
210: 0f da 38 [ ]*pminub \(%eax\),%mm7 210: 0f da 38 [ ]*pminub \(%eax\),%mm7
213: 0f d7 e8 [ ]*pmovmskb %mm5,%eax 213: 0f d7 c5 [ ]*pmovmskb %mm5,%eax
216: 0f e4 e5 [ ]*pmulhuw %mm5,%mm4 216: 0f e4 e5 [ ]*pmulhuw %mm5,%mm4
219: 0f e4 2e [ ]*pmulhuw \(%esi\),%mm5 219: 0f e4 2e [ ]*pmulhuw \(%esi\),%mm5
21c: 0f f6 f7 [ ]*psadbw %mm7,%mm6 21c: 0f f6 f7 [ ]*psadbw %mm7,%mm6

2
gas/testsuite/gas/i386/sse2.d
View file

@ -95,7 +95,7 @@ Disassembly of section .text:
181: 66 0f 16 2e[ ]+movhpd \(%esi\),%xmm5 181: 66 0f 16 2e[ ]+movhpd \(%esi\),%xmm5
185: 66 0f 13 07[ ]+movlpd %xmm0,\(%edi\) 185: 66 0f 13 07[ ]+movlpd %xmm0,\(%edi\)
189: 66 0f 12 00[ ]+movlpd \(%eax\),%xmm0 189: 66 0f 12 00[ ]+movlpd \(%eax\),%xmm0
18d: 66 0f 50 ca[ ]+movmskpd %xmm2,%cx 18d: 66 0f 50 ca[ ]+movmskpd %xmm2,%ecx
191: 66 0f 10 d3[ ]+movupd %xmm3,%xmm2 191: 66 0f 10 d3[ ]+movupd %xmm3,%xmm2
195: 66 0f 11 22[ ]+movupd %xmm4,\(%edx\) 195: 66 0f 11 22[ ]+movupd %xmm4,\(%edx\)
199: 66 0f 10 65 00[ ]+movupd 0x0\(%ebp\),%xmm4 199: 66 0f 10 65 00[ ]+movupd 0x0\(%ebp\),%xmm4

6
gas/testsuite/gas/i386/ssemmx2.d
View file

@ -11,9 +11,9 @@ Disassembly of section .text:
[ ]+4: 66 0f e0 0a[ ]+pavgb[ ]+\(%edx\),%xmm1 [ ]+4: 66 0f e0 0a[ ]+pavgb[ ]+\(%edx\),%xmm1
[ ]+8: 66 0f e3 d3[ ]+pavgw[ ]+%xmm3,%xmm2 [ ]+8: 66 0f e3 d3[ ]+pavgw[ ]+%xmm3,%xmm2
[ ]+c: 66 0f e3 1c 24[ ]+pavgw[ ]+\(%esp,1\),%xmm3 [ ]+c: 66 0f e3 1c 24[ ]+pavgw[ ]+\(%esp,1\),%xmm3
[ ]+11: 66 0f c5 c8 00[ ]+pextrw \$0x0,%xmm1,%ax [ ]+11: 66 0f c5 c1 00[ ]+pextrw \$0x0,%xmm1,%eax
[ ]+16: 66 0f c4 09 01[ ]+pinsrw \$0x1,\(%ecx\),%xmm1 [ ]+16: 66 0f c4 09 01[ ]+pinsrw \$0x1,\(%ecx\),%xmm1
[ ]+1b: 66 0f c4 d2 02[ ]+pinsrw \$0x2,%dx,%xmm2 [ ]+1b: 66 0f c4 d2 02[ ]+pinsrw \$0x2,%edx,%xmm2
[ ]+20: 66 0f ee c1[ ]+pmaxsw %xmm1,%xmm0 [ ]+20: 66 0f ee c1[ ]+pmaxsw %xmm1,%xmm0
[ ]+24: 66 0f ee 0a[ ]+pmaxsw \(%edx\),%xmm1 [ ]+24: 66 0f ee 0a[ ]+pmaxsw \(%edx\),%xmm1
[ ]+28: 66 0f de d2[ ]+pmaxub %xmm2,%xmm2 [ ]+28: 66 0f de d2[ ]+pmaxub %xmm2,%xmm2
@ -22,7 +22,7 @@ Disassembly of section .text:
[ ]+35: 66 0f ea 2e[ ]+pminsw \(%esi\),%xmm5 [ ]+35: 66 0f ea 2e[ ]+pminsw \(%esi\),%xmm5
[ ]+39: 66 0f da f7[ ]+pminub %xmm7,%xmm6 [ ]+39: 66 0f da f7[ ]+pminub %xmm7,%xmm6
[ ]+3d: 66 0f da 38[ ]+pminub \(%eax\),%xmm7 [ ]+3d: 66 0f da 38[ ]+pminub \(%eax\),%xmm7
[ ]+41: 66 0f d7 e8[ ]+pmovmskb %xmm5,%ax [ ]+41: 66 0f d7 c5[ ]+pmovmskb %xmm5,%eax
[ ]+45: 66 0f e4 e5[ ]+pmulhuw %xmm5,%xmm4 [ ]+45: 66 0f e4 e5[ ]+pmulhuw %xmm5,%xmm4
[ ]+49: 66 0f e4 2e[ ]+pmulhuw \(%esi\),%xmm5 [ ]+49: 66 0f e4 2e[ ]+pmulhuw \(%esi\),%xmm5
[ ]+4d: 66 0f f6 f7[ ]+psadbw %xmm7,%xmm6 [ ]+4d: 66 0f f6 f7[ ]+psadbw %xmm7,%xmm6

5
include/opcode/ChangeLog
View file

@ -1,3 +1,8 @@
2001-05-04 Alan Modra <amodra@one.net.au>
* i386.h (i386_optab): Move InvMem to first operand of pmovmskb
and pextrw to swap reg/rm assignments.
2001-04-05 Hans-Peter Nilsson <hp@axis.com> 2001-04-05 Hans-Peter Nilsson <hp@axis.com>
* cris.h (enum cris_insn_version_usage): Correct comment for * cris.h (enum cris_insn_version_usage): Correct comment for

8
include/opcode/i386.h
View file

@ -1152,8 +1152,8 @@ static const template i386_optab[] = {
{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX, Reg32|InvMem } }, {"pextrw", 3, 0x0fc5, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|InvMem, Reg32 } },
{"pextrw", 3, 0x660fc5, X, CpuSSE2,FP|Modrm, { Imm8, RegXMM, Reg32|InvMem } }, {"pextrw", 3, 0x660fc5, X, CpuSSE2,FP|Modrm, { Imm8, RegXMM|InvMem, Reg32 } },
{"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } }, {"pinsrw", 3, 0x0fc4, X, CpuSSE, FP|Modrm, { Imm8, Reg32|ShortMem, RegMMX } },
{"pinsrw", 3, 0x660fc4, X, CpuSSE2, FP|Modrm, { Imm8, Reg32|ShortMem, RegXMM } }, {"pinsrw", 3, 0x660fc4, X, CpuSSE2, FP|Modrm, { Imm8, Reg32|ShortMem, RegXMM } },
{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
@ -1164,8 +1164,8 @@ static const template i386_optab[] = {
{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX, Reg32|InvMem, 0 } }, {"pmovmskb", 2, 0x0fd7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, Reg32, 0 } },
{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,FP|Modrm, { RegXMM, Reg32|InvMem, 0 } }, {"pmovmskb", 2, 0x660fd7, X, CpuSSE2,FP|Modrm, { RegXMM|InvMem, Reg32, 0 } },
{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, {"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } },
{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } },
{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, {"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } },

11
opcodes/ChangeLog
View file

@ -1,3 +1,14 @@
2001-05-04 Alan Modra <amodra@one.net.au>
* i386-dis.c (Ev, Ed): Remove duplicate define.
(Gd): Define.
(XS): Define.
(OP_XS): New function.
(dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and
movmskp operands.
(dis386_twobyte_intel): Likewise.
(prefix_user_table): Use MS for maskmovq operand.
2001-04-27 Johan Rydberg <jrydberg@opencores.org> 2001-04-27 Johan Rydberg <jrydberg@opencores.org>
* Makefile.am: Add OpenRISC target. * Makefile.am: Add OpenRISC target.

37
opcodes/i386-dis.c
View file

@ -149,15 +149,14 @@ fetch_data (info, addr)
#define Ev OP_E, v_mode #define Ev OP_E, v_mode
#define Ed OP_E, d_mode #define Ed OP_E, d_mode
#define indirEb OP_indirE, b_mode #define indirEb OP_indirE, b_mode
#define Gb OP_G, b_mode
#define Ev OP_E, v_mode
#define Ed OP_E, d_mode
#define indirEv OP_indirE, v_mode #define indirEv OP_indirE, v_mode
#define Ew OP_E, w_mode #define Ew OP_E, w_mode
#define Ma OP_E, v_mode #define Ma OP_E, v_mode
#define M OP_E, 0 /* lea */ #define M OP_E, 0 /* lea */
#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ #define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */
#define Gb OP_G, b_mode
#define Gv OP_G, v_mode #define Gv OP_G, v_mode
#define Gd OP_G, d_mode
#define Gw OP_G, w_mode #define Gw OP_G, w_mode
#define Rd OP_Rd, d_mode #define Rd OP_Rd, d_mode
#define Rm OP_Rd, m_mode #define Rm OP_Rd, m_mode
@ -246,6 +245,7 @@ fetch_data (info, addr)
#define EM OP_EM, v_mode #define EM OP_EM, v_mode
#define EX OP_EX, v_mode #define EX OP_EX, v_mode
#define MS OP_MS, v_mode #define MS OP_MS, v_mode
#define XS OP_XS, v_mode
#define None OP_E, 0 #define None OP_E, 0
#define OPSUF OP_3DNowSuffix, 0 #define OPSUF OP_3DNowSuffix, 0
#define OPSIMD OP_SIMD_Suffix, 0 #define OPSIMD OP_SIMD_Suffix, 0
@ -287,6 +287,7 @@ static void OP_XMM PARAMS ((int, int));
static void OP_EM PARAMS ((int, int)); static void OP_EM PARAMS ((int, int));
static void OP_EX PARAMS ((int, int)); static void OP_EX PARAMS ((int, int));
static void OP_MS PARAMS ((int, int)); static void OP_MS PARAMS ((int, int));
static void OP_XS PARAMS ((int, int));
static void OP_3DNowSuffix PARAMS ((int, int)); static void OP_3DNowSuffix PARAMS ((int, int));
static void OP_SIMD_Suffix PARAMS ((int, int)); static void OP_SIMD_Suffix PARAMS ((int, int));
static void SIMD_Fixup PARAMS ((int, int)); static void SIMD_Fixup PARAMS ((int, int));
@ -1708,7 +1709,7 @@ static const struct dis386 dis386_twobyte_att[] = {
{ "cmovle", Gv, Ev, XX }, { "cmovle", Gv, Ev, XX },
{ "cmovg", Gv, Ev, XX }, { "cmovg", Gv, Ev, XX },
/* 50 */ /* 50 */
{ "movmskpX", Gv, EX, XX }, { "movmskpX", Gd, XS, XX },
{ PREGRP13 }, { PREGRP13 },
{ PREGRP12 }, { PREGRP12 },
{ PREGRP11 }, { PREGRP11 },
@ -1838,8 +1839,8 @@ static const struct dis386 dis386_twobyte_att[] = {
{ "xaddS", Ev, Gv, XX }, { "xaddS", Ev, Gv, XX },
{ PREGRP1 }, { PREGRP1 },
{ "movntiS", Ev, Gv, XX }, { "movntiS", Ev, Gv, XX },
{ "pinsrw", MX, Ev, Ib }, { "pinsrw", MX, Ed, Ib },
{ "pextrw", Ev, MX, Ib }, { "pextrw", Gd, MS, Ib },
{ "shufpX", XM, EX, Ib }, { "shufpX", XM, EX, Ib },
{ GRP9 }, { GRP9 },
/* c8 */ /* c8 */
@ -1859,7 +1860,7 @@ static const struct dis386 dis386_twobyte_att[] = {
{ "paddq", MX, EM, XX }, { "paddq", MX, EM, XX },
{ "pmullw", MX, EM, XX }, { "pmullw", MX, EM, XX },
{ PREGRP21 }, { PREGRP21 },
{ "pmovmskb", Ev, MX, XX }, { "pmovmskb", Gd, MS, XX },
/* d8 */ /* d8 */
{ "psubusb", MX, EM, XX }, { "psubusb", MX, EM, XX },
{ "psubusw", MX, EM, XX }, { "psubusw", MX, EM, XX },
@ -2000,7 +2001,7 @@ static const struct dis386 dis386_twobyte_intel[] = {
{ "cmovle", Gv, Ev, XX }, { "cmovle", Gv, Ev, XX },
{ "cmovg", Gv, Ev, XX }, { "cmovg", Gv, Ev, XX },
/* 50 */ /* 50 */
{ "movmskpX", Gv, EX, XX }, { "movmskpX", Gd, XS, XX },
{ PREGRP13 }, { PREGRP13 },
{ PREGRP12 }, { PREGRP12 },
{ PREGRP11 }, { PREGRP11 },
@ -2130,8 +2131,8 @@ static const struct dis386 dis386_twobyte_intel[] = {
{ "xadd", Ev, Gv, XX }, { "xadd", Ev, Gv, XX },
{ PREGRP1 }, { PREGRP1 },
{ "movnti", Ev, Gv, XX }, { "movnti", Ev, Gv, XX },
{ "pinsrw", MX, Ev, Ib }, { "pinsrw", MX, Ed, Ib },
{ "pextrw", Ev, MX, Ib }, { "pextrw", Gd, MS, Ib },
{ "shufpX", XM, EX, Ib }, { "shufpX", XM, EX, Ib },
{ GRP9 }, { GRP9 },
/* c8 */ /* c8 */
@ -2151,7 +2152,7 @@ static const struct dis386 dis386_twobyte_intel[] = {
{ "paddq", MX, EM, XX }, { "paddq", MX, EM, XX },
{ "pmullw", MX, EM, XX }, { "pmullw", MX, EM, XX },
{ PREGRP21 }, { PREGRP21 },
{ "pmovmskb", Ev, MX, XX }, { "pmovmskb", Gd, MS, XX },
/* d8 */ /* d8 */
{ "psubusb", MX, EM, XX }, { "psubusb", MX, EM, XX },
{ "psubusw", MX, EM, XX }, { "psubusw", MX, EM, XX },
@ -2693,7 +2694,7 @@ static const struct dis386 prefix_user_table[][4] = {
}, },
/* PREGRP18 */ /* PREGRP18 */
{ {
{ "maskmovq", MX, EM, XX }, { "maskmovq", MX, MS, XX },
{ "(bad)", XM, EX, XX }, { "(bad)", XM, EX, XX },
{ "maskmovdqu", XM, EX, XX }, { "maskmovdqu", XM, EX, XX },
{ "(bad)", XM, EX, XX }, { "(bad)", XM, EX, XX },
@ -3170,7 +3171,6 @@ print_insn_i386 (pc, info)
used_prefixes |= (prefixes & PREFIX_REPNZ); used_prefixes |= (prefixes & PREFIX_REPNZ);
if (prefixes & PREFIX_REPNZ) if (prefixes & PREFIX_REPNZ)
index = 3; index = 3;
} }
} }
dp = &prefix_user_table[dp->bytemode1][index]; dp = &prefix_user_table[dp->bytemode1][index];
@ -4967,6 +4967,17 @@ OP_MS (bytemode, sizeflag)
BadOp(); BadOp();
} }
static void
OP_XS (bytemode, sizeflag)
int bytemode;
int sizeflag;
{
if (mod == 3)
OP_EX (bytemode, sizeflag);
else
BadOp();
}
static const char *Suffix3DNow[] = { static const char *Suffix3DNow[] = {
/* 00 */ NULL, NULL, NULL, NULL, /* 00 */ NULL, NULL, NULL, NULL,
/* 04 */ NULL, NULL, NULL, NULL, /* 04 */ NULL, NULL, NULL, NULL,