import gdb-1999-07-07 pre reformat
This commit is contained in:
Jason Molenda
parent
f04894943e
commit
9846de1bb5
66 changed files with 2327 additions and 2418 deletions
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@ -1,3 +1,7 @@
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1999-07-06 Doug Evans <devans@casey.cygnus.com>
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* cpu.h,decode.h,model.c,sem-switch.c,sem.c: Rebuild.
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1999-05-08 Felix Lee <flee@cygnus.com>
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* configure: Regenerated to track ../common/aclocal.m4 changes.
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285
sim/fr30/cpu.h
285
sim/fr30/cpu.h
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@ -362,18 +362,6 @@ union sem_fields {
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unsigned char in_Rj;
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unsigned char out_Ri;
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} fmt_ld;
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struct { /* e.g. lduh @$Rj,$Ri */
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SI * i_Rj;
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SI * i_Ri;
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unsigned char in_Rj;
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unsigned char out_Ri;
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} fmt_lduh;
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struct { /* e.g. ldub @$Rj,$Ri */
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SI * i_Rj;
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SI * i_Ri;
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unsigned char in_Rj;
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unsigned char out_Ri;
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} fmt_ldub;
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struct { /* e.g. ld @($R13,$Rj),$Ri */
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SI * i_Rj;
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SI * i_Ri;
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@ -381,20 +369,6 @@ union sem_fields {
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unsigned char in_h_gr_13;
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unsigned char out_Ri;
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} fmt_ldr13;
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struct { /* e.g. lduh @($R13,$Rj),$Ri */
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SI * i_Rj;
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SI * i_Ri;
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unsigned char in_Rj;
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unsigned char in_h_gr_13;
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unsigned char out_Ri;
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} fmt_ldr13uh;
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struct { /* e.g. ldub @($R13,$Rj),$Ri */
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SI * i_Rj;
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SI * i_Ri;
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unsigned char in_Rj;
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unsigned char in_h_gr_13;
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unsigned char out_Ri;
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} fmt_ldr13ub;
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struct { /* e.g. ld @($R14,$disp10),$Ri */
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SI f_disp10;
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SI * i_Ri;
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@ -442,18 +416,6 @@ union sem_fields {
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unsigned char in_Ri;
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unsigned char in_Rj;
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} fmt_st;
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struct { /* e.g. sth $Ri,@$Rj */
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SI * i_Ri;
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SI * i_Rj;
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unsigned char in_Ri;
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unsigned char in_Rj;
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} fmt_sth;
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struct { /* e.g. stb $Ri,@$Rj */
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SI * i_Ri;
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SI * i_Rj;
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unsigned char in_Ri;
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unsigned char in_Rj;
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} fmt_stb;
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struct { /* e.g. st $Ri,@($R13,$Rj) */
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SI * i_Ri;
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SI * i_Rj;
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@ -461,20 +423,6 @@ union sem_fields {
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unsigned char in_Rj;
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unsigned char in_h_gr_13;
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} fmt_str13;
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struct { /* e.g. sth $Ri,@($R13,$Rj) */
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SI * i_Ri;
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SI * i_Rj;
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unsigned char in_Ri;
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unsigned char in_Rj;
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unsigned char in_h_gr_13;
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} fmt_str13h;
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struct { /* e.g. stb $Ri,@($R13,$Rj) */
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SI * i_Ri;
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SI * i_Rj;
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unsigned char in_Ri;
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unsigned char in_Rj;
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unsigned char in_h_gr_13;
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} fmt_str13b;
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struct { /* e.g. st $Ri,@($R14,$disp10) */
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SI f_disp10;
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SI * i_Ri;
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@ -614,15 +562,6 @@ union sem_fields {
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struct { /* e.g. copop $u4c,$ccc,$CRj,$CRi */
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int empty;
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} fmt_copop;
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struct { /* e.g. copld $u4c,$ccc,$Rjc,$CRi */
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int empty;
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} fmt_copld;
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struct { /* e.g. copst $u4c,$ccc,$CRj,$Ric */
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int empty;
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} fmt_copst;
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struct { /* e.g. nop */
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int empty;
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} fmt_nop;
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struct { /* e.g. andccr $u8 */
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UINT f_u8;
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} fmt_andccr;
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@ -846,10 +785,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_ADD_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_Rj = EXTRACT_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_Rj = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_ADDI_VARS \
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/* Instruction fields. */ \
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@ -860,10 +799,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_ADDI_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_u4 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_u4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_ADD2_VARS \
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/* Instruction fields. */ \
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@ -874,10 +813,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_ADD2_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_m4 = ((EXTRACT_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_m4 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) | (((-1) << (4)))); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_DIV0S_VARS \
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/* Instruction fields. */ \
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@ -888,10 +827,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_DIV0S_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_DIV3_VARS \
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/* Instruction fields. */ \
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@ -902,10 +841,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_DIV3_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_op4 = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_op4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDI8_VARS \
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/* Instruction fields. */ \
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@ -915,16 +854,16 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_LDI8_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_i8 = EXTRACT_UINT (insn, 16, 4, 8); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_i8 = EXTRACT_MSB0_UINT (insn, 16, 4, 8); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDI20_VARS \
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/* Instruction fields. */ \
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UINT f_op1; \
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UINT f_i20; \
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UINT f_i20_4; \
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UINT f_i20_16; \
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UINT f_i20; \
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UINT f_op2; \
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UINT f_Ri; \
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/* Contents of trailing part of insn. */ \
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@ -933,14 +872,14 @@ struct scache {
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#define EXTRACT_IFMT_LDI20_CODE \
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length = 4; \
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word_1 = GETIMEMUHI (current_cpu, pc + 2); \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_i20_4 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_i20_16 = (0|(EXTRACT_UINT (word_1, 16, 0, 16) << 0)); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_i20_4 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_i20_16 = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 0)); \
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{\
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f_i20 = ((((f_i20_4) << (16))) | (f_i20_16));\
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}\
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDI32_VARS \
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/* Instruction fields. */ \
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@ -957,11 +896,11 @@ struct scache {
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length = 6; \
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word_1 = GETIMEMUHI (current_cpu, pc + 2); \
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word_2 = GETIMEMUHI (current_cpu, pc + 4); \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_i32 = (0|(EXTRACT_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_UINT (word_1, 16, 0, 16) << 16)); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_i32 = (0|(EXTRACT_MSB0_UINT (word_2, 16, 0, 16) << 0)|(EXTRACT_MSB0_UINT (word_1, 16, 0, 16) << 16)); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDR14_VARS \
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/* Instruction fields. */ \
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@ -971,9 +910,9 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_LDR14_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_disp10 = ((EXTRACT_INT (insn, 16, 4, 8)) << (2)); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_disp10 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (2)); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDR14UH_VARS \
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/* Instruction fields. */ \
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@ -983,9 +922,9 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_LDR14UH_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_disp9 = ((EXTRACT_INT (insn, 16, 4, 8)) << (1)); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_disp9 = ((EXTRACT_MSB0_INT (insn, 16, 4, 8)) << (1)); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDR14UB_VARS \
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/* Instruction fields. */ \
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@ -995,9 +934,9 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_LDR14UB_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_disp8 = EXTRACT_INT (insn, 16, 4, 8); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_disp8 = EXTRACT_MSB0_INT (insn, 16, 4, 8); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDR15_VARS \
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/* Instruction fields. */ \
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@ -1008,10 +947,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_LDR15_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_udisp6 = ((EXTRACT_UINT (insn, 16, 8, 4)) << (2)); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_udisp6 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 4)) << (2)); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_LDR15DR_VARS \
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/* Instruction fields. */ \
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@ -1022,10 +961,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_LDR15DR_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_Rs2 = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_Rs2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_MOVDR_VARS \
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/* Instruction fields. */ \
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@ -1036,10 +975,10 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_MOVDR_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_Rs1 = EXTRACT_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_UINT (insn, 16, 12, 4); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
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f_Rs1 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
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f_Ri = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
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#define EXTRACT_IFMT_CALL_VARS \
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/* Instruction fields. */ \
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@ -1049,9 +988,9 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_CALL_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op5 = EXTRACT_UINT (insn, 16, 4, 1); \
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f_rel12 = ((((EXTRACT_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \
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f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
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f_op5 = EXTRACT_MSB0_UINT (insn, 16, 4, 1); \
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f_rel12 = ((((EXTRACT_MSB0_INT (insn, 16, 5, 11)) << (1))) + (((pc) + (2)))); \
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#define EXTRACT_IFMT_INT_VARS \
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/* Instruction fields. */ \
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@ -1061,9 +1000,9 @@ struct scache {
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unsigned int length;
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#define EXTRACT_IFMT_INT_CODE \
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length = 2; \
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f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
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f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
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f_u8 = EXTRACT_UINT (insn, 16, 8, 8); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_u8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
||||
|
||||
#define EXTRACT_IFMT_BRAD_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1073,9 +1012,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_BRAD_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_cc = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_rel9 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_cc = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_rel9 = ((((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (1))) + (((pc) + (2)))); \
|
||||
|
||||
#define EXTRACT_IFMT_DMOVR13_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1085,9 +1024,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_DMOVR13_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_dir10 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (2)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_dir10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
|
||||
|
||||
#define EXTRACT_IFMT_DMOVR13H_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1097,9 +1036,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_DMOVR13H_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_dir9 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (1)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_dir9 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (1)); \
|
||||
|
||||
#define EXTRACT_IFMT_DMOVR13B_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1109,9 +1048,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_DMOVR13B_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_dir8 = EXTRACT_UINT (insn, 16, 8, 8); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_dir8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
||||
|
||||
#define EXTRACT_IFMT_COPOP_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1128,13 +1067,13 @@ struct scache {
|
|||
#define EXTRACT_IFMT_COPOP_CODE \
|
||||
length = 4; \
|
||||
word_1 = GETIMEMUHI (current_cpu, pc + 2); \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
|
||||
f_CRj = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \
|
||||
f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \
|
||||
f_CRi = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
||||
f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
|
||||
f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
||||
f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
|
||||
|
||||
#define EXTRACT_IFMT_COPLD_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1151,13 +1090,13 @@ struct scache {
|
|||
#define EXTRACT_IFMT_COPLD_CODE \
|
||||
length = 4; \
|
||||
word_1 = GETIMEMUHI (current_cpu, pc + 2); \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
|
||||
f_Rjc = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \
|
||||
f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \
|
||||
f_CRi = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
||||
f_Rjc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
|
||||
f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
||||
f_CRi = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
|
||||
|
||||
#define EXTRACT_IFMT_COPST_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1174,13 +1113,13 @@ struct scache {
|
|||
#define EXTRACT_IFMT_COPST_CODE \
|
||||
length = 4; \
|
||||
word_1 = GETIMEMUHI (current_cpu, pc + 2); \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_ccc = (0|(EXTRACT_UINT (word_1, 16, 0, 8) << 0)); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_op3 = EXTRACT_UINT (insn, 16, 8, 4); \
|
||||
f_CRj = (0|(EXTRACT_UINT (word_1, 16, 8, 4) << 0)); \
|
||||
f_u4c = EXTRACT_UINT (insn, 16, 12, 4); \
|
||||
f_Ric = (0|(EXTRACT_UINT (word_1, 16, 12, 16) << 0)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_ccc = (0|(EXTRACT_MSB0_UINT (word_1, 16, 0, 8) << 0)); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_op3 = EXTRACT_MSB0_UINT (insn, 16, 8, 4); \
|
||||
f_CRj = (0|(EXTRACT_MSB0_UINT (word_1, 16, 8, 4) << 0)); \
|
||||
f_u4c = EXTRACT_MSB0_UINT (insn, 16, 12, 4); \
|
||||
f_Ric = (0|(EXTRACT_MSB0_UINT (word_1, 16, 12, 16) << 0)); \
|
||||
|
||||
#define EXTRACT_IFMT_ADDSP_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1190,9 +1129,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ADDSP_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_s10 = ((EXTRACT_INT (insn, 16, 8, 8)) << (2)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_s10 = ((EXTRACT_MSB0_INT (insn, 16, 8, 8)) << (2)); \
|
||||
|
||||
#define EXTRACT_IFMT_LDM0_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1202,9 +1141,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDM0_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_low_ld = EXTRACT_UINT (insn, 16, 8, 8); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_low_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
||||
|
||||
#define EXTRACT_IFMT_LDM1_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1214,9 +1153,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_LDM1_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_hi_ld = EXTRACT_UINT (insn, 16, 8, 8); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_hi_ld = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
||||
|
||||
#define EXTRACT_IFMT_STM0_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1226,9 +1165,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_STM0_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_low_st = EXTRACT_UINT (insn, 16, 8, 8); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_low_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
||||
|
||||
#define EXTRACT_IFMT_STM1_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1238,9 +1177,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_STM1_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_hi_st = EXTRACT_UINT (insn, 16, 8, 8); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_reglist_hi_st = EXTRACT_MSB0_UINT (insn, 16, 8, 8); \
|
||||
|
||||
#define EXTRACT_IFMT_ENTER_VARS \
|
||||
/* Instruction fields. */ \
|
||||
|
|
@ -1250,9 +1189,9 @@ struct scache {
|
|||
unsigned int length;
|
||||
#define EXTRACT_IFMT_ENTER_CODE \
|
||||
length = 2; \
|
||||
f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_UINT (insn, 16, 4, 4); \
|
||||
f_u10 = ((EXTRACT_UINT (insn, 16, 8, 8)) << (2)); \
|
||||
f_op1 = EXTRACT_MSB0_UINT (insn, 16, 0, 4); \
|
||||
f_op2 = EXTRACT_MSB0_UINT (insn, 16, 4, 4); \
|
||||
f_u10 = ((EXTRACT_MSB0_UINT (insn, 16, 8, 8)) << (2)); \
|
||||
|
||||
/* Collection of various things for the trace handler to use. */
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -1594,7 +1594,7 @@ model_fr30_1_ld (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_lduh (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_lduh.f
|
||||
#define FLD(f) abuf->fields.fmt_ld.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1616,7 +1616,7 @@ model_fr30_1_lduh (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_ldub (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_ldub.f
|
||||
#define FLD(f) abuf->fields.fmt_ld.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1660,7 +1660,7 @@ model_fr30_1_ldr13 (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_ldr13uh (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_ldr13uh.f
|
||||
#define FLD(f) abuf->fields.fmt_ldr13.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1682,7 +1682,7 @@ model_fr30_1_ldr13uh (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_ldr13ub (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_ldr13ub.f
|
||||
#define FLD(f) abuf->fields.fmt_ldr13.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1862,7 +1862,7 @@ model_fr30_1_st (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_sth (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_sth.f
|
||||
#define FLD(f) abuf->fields.fmt_st.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1884,7 +1884,7 @@ model_fr30_1_sth (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_stb (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_stb.f
|
||||
#define FLD(f) abuf->fields.fmt_st.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1928,7 +1928,7 @@ model_fr30_1_str13 (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_str13h (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_str13h.f
|
||||
#define FLD(f) abuf->fields.fmt_str13.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -1950,7 +1950,7 @@ model_fr30_1_str13h (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_str13b (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_str13b.f
|
||||
#define FLD(f) abuf->fields.fmt_str13.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -3371,7 +3371,7 @@ model_fr30_1_copop (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_copld (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_copld.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -3390,7 +3390,7 @@ model_fr30_1_copld (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_copst (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_copst.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -3409,7 +3409,7 @@ model_fr30_1_copst (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_copsv (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_copst.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
@ -3428,7 +3428,7 @@ model_fr30_1_copsv (SIM_CPU *current_cpu, void *sem_arg)
|
|||
static int
|
||||
model_fr30_1_nop (SIM_CPU *current_cpu, void *sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_nop.f
|
||||
#define FLD(f) abuf->fields.fmt_bnod.f
|
||||
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
|
||||
const IDESC * UNUSED idesc = abuf->idesc;
|
||||
int cycles = 0;
|
||||
|
|
|
|||
|
|
@ -2388,7 +2388,7 @@ if (NESI (tmp_shift, 0)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_lduh.f
|
||||
#define FLD(f) abuf->fields.fmt_ld.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2407,7 +2407,7 @@ if (NESI (tmp_shift, 0)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_ldub.f
|
||||
#define FLD(f) abuf->fields.fmt_ld.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2445,7 +2445,7 @@ if (NESI (tmp_shift, 0)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_ldr13uh.f
|
||||
#define FLD(f) abuf->fields.fmt_ldr13.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2464,7 +2464,7 @@ if (NESI (tmp_shift, 0)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_ldr13ub.f
|
||||
#define FLD(f) abuf->fields.fmt_ldr13.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2662,7 +2662,7 @@ if (NESI (FLD (f_Ri), 15)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_sth.f
|
||||
#define FLD(f) abuf->fields.fmt_st.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2681,7 +2681,7 @@ if (NESI (FLD (f_Ri), 15)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_stb.f
|
||||
#define FLD(f) abuf->fields.fmt_st.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2719,7 +2719,7 @@ if (NESI (FLD (f_Ri), 15)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_str13h.f
|
||||
#define FLD(f) abuf->fields.fmt_str13.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -2738,7 +2738,7 @@ if (NESI (FLD (f_Ri), 15)) {
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_str13b.f
|
||||
#define FLD(f) abuf->fields.fmt_str13.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
@ -4517,7 +4517,7 @@ do { } while (0); /*nop*/
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_copld.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
|
@ -4532,7 +4532,7 @@ do { } while (0); /*nop*/
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_copst.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
|
@ -4547,7 +4547,7 @@ do { } while (0); /*nop*/
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_copst.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
|
||||
|
|
@ -4562,7 +4562,7 @@ do { } while (0); /*nop*/
|
|||
{
|
||||
SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc);
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
#define FLD(f) abuf->fields.fmt_nop.f
|
||||
#define FLD(f) abuf->fields.fmt_bnod.f
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
vpc = SEM_NEXT_VPC (sem_arg, pc, 2);
|
||||
|
|
|
|||
|
|
@ -2287,7 +2287,7 @@ SEM_FN_NAME (fr30bf,ld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_lduh.f
|
||||
#define FLD(f) abuf->fields.fmt_ld.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2308,7 +2308,7 @@ SEM_FN_NAME (fr30bf,lduh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,ldub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_ldub.f
|
||||
#define FLD(f) abuf->fields.fmt_ld.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2350,7 +2350,7 @@ SEM_FN_NAME (fr30bf,ldr13) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,ldr13uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_ldr13uh.f
|
||||
#define FLD(f) abuf->fields.fmt_ldr13.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2371,7 +2371,7 @@ SEM_FN_NAME (fr30bf,ldr13uh) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,ldr13ub) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_ldr13ub.f
|
||||
#define FLD(f) abuf->fields.fmt_ldr13.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2587,7 +2587,7 @@ SEM_FN_NAME (fr30bf,st) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_sth.f
|
||||
#define FLD(f) abuf->fields.fmt_st.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2608,7 +2608,7 @@ SEM_FN_NAME (fr30bf,sth) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,stb) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_stb.f
|
||||
#define FLD(f) abuf->fields.fmt_st.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2650,7 +2650,7 @@ SEM_FN_NAME (fr30bf,str13) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,str13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_str13h.f
|
||||
#define FLD(f) abuf->fields.fmt_str13.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -2671,7 +2671,7 @@ SEM_FN_NAME (fr30bf,str13h) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,str13b) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_str13b.f
|
||||
#define FLD(f) abuf->fields.fmt_str13.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -4596,7 +4596,7 @@ do { } while (0); /*nop*/
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,copld) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_copld.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -4613,7 +4613,7 @@ do { } while (0); /*nop*/
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,copst) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_copst.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -4630,7 +4630,7 @@ do { } while (0); /*nop*/
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,copsv) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_copst.f
|
||||
#define FLD(f) abuf->fields.fmt_copop.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
@ -4647,7 +4647,7 @@ do { } while (0); /*nop*/
|
|||
SEM_PC
|
||||
SEM_FN_NAME (fr30bf,nop) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
|
||||
{
|
||||
#define FLD(f) abuf->fields.fmt_nop.f
|
||||
#define FLD(f) abuf->fields.fmt_bnod.f
|
||||
ARGBUF *abuf = SEM_ARGBUF (sem_arg);
|
||||
int UNUSED written = 0;
|
||||
IADDR UNUSED pc = abuf->addr;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue