gdbarch software_single_step returns VEC (CORE_ADDR) *
This patch changes gdbarch method software_single_step to return a vector of addresses on which GDB should insert breakpoints, and don't insert breakpoints. Instead, the caller of gdbarch_software_single_step inserts breakpoints if the returned vector is not NULL. gdb: 2016-11-08 Yao Qi <yao.qi@linaro.org> * aarch64-tdep.c (aarch64_software_single_step): Return VEC (CORE_ADDR) *. Return NULL instead of 0. Don't call insert_single_step_breakpoint. * alpha-tdep.c (alpha_deal_with_atomic_sequence): Likewise. (alpha_software_single_step): Likewise. * alpha-tdep.h (alpha_software_single_step): Update declaration. * arm-linux-tdep.c (arm_linux_software_single_step): Return VEC (CORE_ADDR) *. Return NULL instead of 0. * arm-tdep.c (arm_software_single_step): Return NULL instead of 0. * arm-tdep.h (arm_software_single_step): Update declaration. * breakpoint.c (insert_single_step_breakpoints): New function. * breakpoint.h (insert_single_step_breakpoints): Declare. * cris-tdep.c (cris_software_single_step): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. * gdbarch.sh (software_single_step): Change it to return VEC (CORE_ADDR) *. * gdbarch.c, gdbarch.h: Regenerated. * infrun.c (maybe_software_singlestep): Adjust. * mips-tdep.c (mips_deal_with_atomic_sequence): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. (micromips_deal_with_atomic_sequence): Likewise. (deal_with_atomic_sequence): Likewise. (mips_software_single_step): Likewise. * mips-tdep.h (mips_software_single_step): Update declaration. * moxie-tdep.c (moxie_software_single_step): Likewise. * nios2-tdep.c (nios2_software_single_step): Likewise. * ppc-tdep.h (ppc_deal_with_atomic_sequence): Update declaration. * record-full.c (record_full_resume): Adjust. (record_full_wait_1): Likewise. * rs6000-aix-tdep.c (rs6000_software_single_step): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. * rs6000-tdep.c (ppc_deal_with_atomic_sequence): Return VEC (CORE_ADDR) *. Don't call insert_single_step_breakpoint. * s390-linux-tdep.c (s390_software_single_step): Likewise. * sparc-tdep.c (sparc_software_single_step): Likewise. * spu-tdep.c (spu_software_single_step): Likewise. * tic6x-tdep.c (tic6x_software_single_step): Likewise.
This commit is contained in:
Yao Qi
parent
0bc5d801ec
commit
93f9a11fbd
26 changed files with 225 additions and 173 deletions
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@ -3877,9 +3877,8 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
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#define SC_OPCODE 0x38
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#define SCD_OPCODE 0x3c
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static int
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mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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struct address_space *aspace, CORE_ADDR pc)
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static VEC (CORE_ADDR) *
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mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
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{
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CORE_ADDR breaks[2] = {-1, -1};
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CORE_ADDR loc = pc;
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@ -3889,11 +3888,12 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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int index;
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int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
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const int atomic_sequence_length = 16; /* Instruction sequence length. */
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VEC (CORE_ADDR) *next_pcs = NULL;
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insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL);
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/* Assume all atomic sequences start with a ll/lld instruction. */
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if (itype_op (insn) != LL_OPCODE && itype_op (insn) != LLD_OPCODE)
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return 0;
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return NULL;
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/* Assume that no atomic sequence is longer than "atomic_sequence_length"
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instructions. */
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@ -3957,7 +3957,7 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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/* Assume that the atomic sequence ends with a sc/scd instruction. */
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if (itype_op (insn) != SC_OPCODE && itype_op (insn) != SCD_OPCODE)
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return 0;
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return NULL;
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loc += MIPS_INSN32_SIZE;
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@ -3971,14 +3971,13 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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/* Effectively inserts the breakpoints. */
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for (index = 0; index <= last_breakpoint; index++)
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insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
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VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
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return 1;
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return next_pcs;
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}
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static int
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static VEC (CORE_ADDR) *
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micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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struct address_space *aspace,
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CORE_ADDR pc)
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{
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const int atomic_sequence_length = 16; /* Instruction sequence length. */
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@ -3991,16 +3990,17 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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ULONGEST insn;
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int insn_count;
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int index;
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VEC (CORE_ADDR) *next_pcs = NULL;
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/* Assume all atomic sequences start with a ll/lld instruction. */
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insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
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if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */
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return 0;
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return NULL;
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loc += MIPS_INSN16_SIZE;
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insn <<= 16;
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insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL);
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if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
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return 0;
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return NULL;
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loc += MIPS_INSN16_SIZE;
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/* Assume all atomic sequences end with an sc/scd instruction. Assume
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@ -4097,24 +4097,24 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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&& b5s5_op (insn) != 0x18)
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/* JRADDIUSP: bits 010001 11000 */
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break;
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return 0; /* Fall back to the standard single-step code. */
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return NULL; /* Fall back to the standard single-step code. */
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case 0x33: /* B16: bits 110011 */
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return 0; /* Fall back to the standard single-step code. */
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return NULL; /* Fall back to the standard single-step code. */
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}
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break;
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}
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if (is_branch)
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{
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if (last_breakpoint >= 1)
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return 0; /* More than one branch found, fallback to the
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return NULL; /* More than one branch found, fallback to the
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standard single-step code. */
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breaks[1] = branch_bp;
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last_breakpoint++;
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}
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}
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if (!sc_found)
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return 0;
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return NULL;
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/* Insert a breakpoint right after the end of the atomic sequence. */
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breaks[0] = loc;
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@ -4126,21 +4126,20 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch,
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/* Effectively inserts the breakpoints. */
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for (index = 0; index <= last_breakpoint; index++)
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insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
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VEC_safe_push (CORE_ADDR, next_pcs, breaks[index]);
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return 1;
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return next_pcs;
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}
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static int
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deal_with_atomic_sequence (struct gdbarch *gdbarch,
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struct address_space *aspace, CORE_ADDR pc)
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static VEC (CORE_ADDR) *
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deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc)
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{
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if (mips_pc_is_mips (pc))
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return mips_deal_with_atomic_sequence (gdbarch, aspace, pc);
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return mips_deal_with_atomic_sequence (gdbarch, pc);
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else if (mips_pc_is_micromips (gdbarch, pc))
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return micromips_deal_with_atomic_sequence (gdbarch, aspace, pc);
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return micromips_deal_with_atomic_sequence (gdbarch, pc);
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else
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return 0;
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return NULL;
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}
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/* mips_software_single_step() is called just before we want to resume
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@ -4148,21 +4147,22 @@ deal_with_atomic_sequence (struct gdbarch *gdbarch,
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or kernel single-step support (MIPS on GNU/Linux for example). We find
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the target of the coming instruction and breakpoint it. */
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int
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VEC (CORE_ADDR) *
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mips_software_single_step (struct frame_info *frame)
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{
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struct gdbarch *gdbarch = get_frame_arch (frame);
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struct address_space *aspace = get_frame_address_space (frame);
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CORE_ADDR pc, next_pc;
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VEC (CORE_ADDR) *next_pcs;
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pc = get_frame_pc (frame);
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if (deal_with_atomic_sequence (gdbarch, aspace, pc))
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return 1;
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next_pcs = deal_with_atomic_sequence (gdbarch, pc);
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if (next_pcs != NULL)
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return next_pcs;
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next_pc = mips_next_pc (frame, pc);
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insert_single_step_breakpoint (gdbarch, aspace, next_pc);
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return 1;
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VEC_safe_push (CORE_ADDR, next_pcs, next_pc);
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return next_pcs;
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}
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/* Test whether the PC points to the return instruction at the
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