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[AArch64] PR target/20666, fix wrong encoding of new introduced BFC pseudo

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opcode/
	PR target/20666
	* aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.

gas/
	* testsuite/gas/aarch64/alias-2.d: Update expected results.
This commit is contained in:
Jiong Wang 2016-10-11 11:24:44 +01:00
parent f02cb05882
commit 93562a343c
4 changed files with 28 additions and 18 deletions
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5
gas/ChangeLog
View file

@ -1,3 +1,8 @@
2016-10-11 Jiong Wang <jiong.wang@arm.com>
PR target/20666
* testsuite/gas/aarch64/alias-2.d: Update expected results.
2016-10-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
* testsuite/gas/cfi/cfi-common-1.d: Adjust regexps for mips64.

34
gas/testsuite/gas/aarch64/alias-2.d
View file

@ -3,9 +3,9 @@
.*: file format .*
Disassembly of section \.text:
Disassembly of section .*:
0000000000000000 <.*>:
.* <.*>:
[0-9a-f]+: b34107e0 bfxil x0, xzr, #1, #1
[0-9a-f]+: b3410420 bfxil x0, x1, #1, #1
[0-9a-f]+: b341043f bfxil xzr, x1, #1, #1
@ -78,23 +78,23 @@ Disassembly of section \.text:
[0-9a-f]+: b3613820 bfi x0, x1, #31, #15
[0-9a-f]+: b361383f bfi xzr, x1, #31, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: b34003e0 bfxil x0, xzr, #0, #1
[0-9a-f]+: b37f03e0 bfc x0, #1, #1
[0-9a-f]+: b37f03ff bfc xzr, #1, #1
[0-9a-f]+: b37f1fe0 bfc x0, #1, #8
[0-9a-f]+: b37f1fff bfc xzr, #1, #8
[0-9a-f]+: b37f3be0 bfc x0, #1, #15
[0-9a-f]+: b37f3bff bfc xzr, #1, #15
[0-9a-f]+: b37003e0 bfc x0, #16, #1
[0-9a-f]+: b37003ff bfc xzr, #16, #1
[0-9a-f]+: b3701fe0 bfc x0, #16, #8
[0-9a-f]+: b3701fff bfc xzr, #16, #8
[0-9a-f]+: b3703be0 bfc x0, #16, #15
[0-9a-f]+: b3703bff bfc xzr, #16, #15
[0-9a-f]+: b36103e0 bfc x0, #31, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3401fe0 bfxil x0, xzr, #0, #8
[0-9a-f]+: b3611fe0 bfc x0, #31, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: b34003e0 bfxil x0, xzr, #0, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3401fe0 bfxil x0, xzr, #0, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: b34003e0 bfxil x0, xzr, #0, #1
[0-9a-f]+: b36103ff bfc xzr, #31, #1
[0-9a-f]+: b3401fe0 bfxil x0, xzr, #0, #8
[0-9a-f]+: b3611fff bfc xzr, #31, #8
[0-9a-f]+: b3403be0 bfxil x0, xzr, #0, #15
[0-9a-f]+: b3613be0 bfc x0, #31, #15
[0-9a-f]+: b3613bff bfc xzr, #31, #15
[0-9a-f]+: dac00fe0 rev x0, xzr
[0-9a-f]+: dac00c20 rev x0, x1

5
opcodes/ChangeLog
View file

@ -1,3 +1,8 @@
2016-10-11 Jiong Wang <jiong.wang@arm.com>
PR target/20666
* aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
2016-10-07 Jiong Wang <jiong.wang@arm.com>
PR target/20667

2
opcodes/aarch64-asm.c
View file

@ -1539,7 +1539,7 @@ convert_bfc_to_bfm (aarch64_inst *inst)
/* Insert XZR. */
copy_operand_info (inst, 3, 2);
copy_operand_info (inst, 2, 1);
copy_operand_info (inst, 2, 0);
copy_operand_info (inst, 0, 0);
inst->operands[1].reg.regno = 0x1f;
/* Convert the immedate operand. */