Add support for m32rx.
* config/tc-m32r.c (enable_m32rx): New static global. (enable_special,warn_explicit_parallel_conflicts,optimize): Ditto. (allow_m32rx): New function. (M32R_SHORTOPTS): Add `O'. (md_longopts): Add --m32rx plus several warning options. (md_parse_option): Handle new options. (md_show_usage): Print them. (md_begin): Enable m32rx. (OPERAND_IS_COND_BIT): New macro. (first_writes_to_seconds_operands): New function. (writes_to_pc,can_make_parallel,make_parallel): New functions. (target_make_parallel,assemble_two_insns): New functions. (md_assemble): Recognize "insn1 -> insn2" and "insn1 || insn2". If optimizing and m32rx, try to make consecutive insns parallel.
This commit is contained in:
Doug Evans
parent
1fa60b5dde
commit
925c058e93
2 changed files with 618 additions and 1 deletions
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@ -1,3 +1,22 @@
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Mon Oct 4 17:24:23 1999 Nick Clifton <nickc@cygnus.com>
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Doug Evans <devans@cygnus.com>
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Add support for m32rx.
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* config/tc-m32r.c (enable_m32rx): New static global.
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(enable_special,warn_explicit_parallel_conflicts,optimize): Ditto.
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(allow_m32rx): New function.
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(M32R_SHORTOPTS): Add `O'.
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(md_longopts): Add --m32rx plus several warning options.
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(md_parse_option): Handle new options.
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(md_show_usage): Print them.
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(md_begin): Enable m32rx.
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(OPERAND_IS_COND_BIT): New macro.
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(first_writes_to_seconds_operands): New function.
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(writes_to_pc,can_make_parallel,make_parallel): New functions.
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(target_make_parallel,assemble_two_insns): New functions.
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(md_assemble): Recognize "insn1 -> insn2" and "insn1 || insn2".
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If optimizing and m32rx, try to make consecutive insns parallel.
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Tue Sep 28 14:06:44 1999 Geoffrey Keating <geoffk@cygnus.com>
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* config/tc-mips.c (nopic_need_relax): Allow for the
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@ -91,6 +91,20 @@ static const char * m32r_cpu_desc;
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shouldn't assume or require it to). */
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static int warn_unmatched_high = 0;
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/* Non-zero if -m32rx has been specified, in which case support for the
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extended M32RX instruction set should be enabled. */
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static int enable_m32rx = 0;
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/* Non-zero if -m32rx -hidden has been specified, in which case support for
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the special M32RX instruction set should be enabled. */
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static int enable_special = 0;
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/* Non-zero if the programmer should be warned when an explicit parallel
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instruction might have constraint violations. */
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static int warn_explicit_parallel_conflicts = 1;
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/* Non-zero if insns can be made parallel. */
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static int optimize;
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/* stuff for .scomm symbols. */
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static segT sbss_section;
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@ -127,12 +141,32 @@ struct m32r_hi_fixup
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static struct m32r_hi_fixup * m32r_hi_fixup_list;
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static void
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allow_m32rx (on)
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int on;
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{
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enable_m32rx = on;
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if (stdoutput != NULL)
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bfd_set_arch_mach (stdoutput, TARGET_ARCH,
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enable_m32rx ? bfd_mach_m32rx : bfd_mach_m32r);
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}
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#define M32R_SHORTOPTS ""
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#define M32R_SHORTOPTS "O"
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const char * md_shortopts = M32R_SHORTOPTS;
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struct option md_longopts[] =
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{
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#define OPTION_M32RX (OPTION_MD_BASE)
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{"m32rx", no_argument, NULL, OPTION_M32RX},
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#define OPTION_WARN_PARALLEL (OPTION_MD_BASE + 1)
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{"warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_WARN_PARALLEL},
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{"Wp", no_argument, NULL, OPTION_WARN_PARALLEL},
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#define OPTION_NO_WARN_PARALLEL (OPTION_MD_BASE + 2)
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{"no-warn-explicit-parallel-conflicts", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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{"Wnp", no_argument, NULL, OPTION_NO_WARN_PARALLEL},
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#define OPTION_SPECIAL (OPTION_MD_BASE + 3)
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{"hidden", no_argument, NULL, OPTION_SPECIAL},
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/* Sigh. I guess all warnings must now have both variants. */
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#define OPTION_WARN_UNMATCHED (OPTION_MD_BASE + 4)
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@ -159,6 +193,32 @@ md_parse_option (c, arg)
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{
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switch (c)
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{
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case 'O':
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optimize = 1;
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break;
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case OPTION_M32RX:
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allow_m32rx (1);
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break;
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case OPTION_WARN_PARALLEL:
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warn_explicit_parallel_conflicts = 1;
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break;
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case OPTION_NO_WARN_PARALLEL:
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warn_explicit_parallel_conflicts = 0;
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break;
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case OPTION_SPECIAL:
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if (enable_m32rx)
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enable_special = 1;
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else
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{
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/* Pretend that we do not recognise this option. */
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as_bad (_("Unrecognised option: -hidden"));
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return 0;
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}
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break;
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case OPTION_WARN_UNMATCHED:
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warn_unmatched_high = 1;
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@ -190,6 +250,23 @@ md_show_usage (stream)
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{
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fprintf (stream, _(" M32R specific command line options:\n"));
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fprintf (stream, _("\
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-m32rx support the extended m32rx instruction set\n"));
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fprintf (stream, _("\
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-O try to combine instructions in parallel\n"));
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fprintf (stream, _("\
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-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
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fprintf (stream, _("\
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violate contraints\n"));
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fprintf (stream, _("\
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-no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
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fprintf (stream, _("\
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instructions violate contraints\n"));
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fprintf (stream, _("\
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-Wp synonym for -warn-explicit-parallel-conflicts\n"));
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fprintf (stream, _("\
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-Wnp synonym for -no-warn-explicit-parallel-conflicts\n"));
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fprintf (stream, _("\
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-warn-unmatched-high warn when an (s)high reloc has no matching low reloc\n"));
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@ -224,6 +301,9 @@ const pseudo_typeS md_pseudo_table[] =
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{ "fillinsn", fill_insn, 0 },
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{ "scomm", m32r_scomm, 0 },
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{ "debugsym", debug_sym, 0 },
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/* Not documented as so far there is no need for them.... */
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{ "m32r", allow_m32rx, 0 },
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{ "m32rx", allow_m32rx, 1 },
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{ NULL, NULL, 0 }
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};
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@ -464,9 +544,427 @@ md_begin ()
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scom_symbol.name = ".scommon";
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scom_symbol.section = & scom_section;
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allow_m32rx (enable_m32rx);
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}
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#define OPERAND_IS_COND_BIT(operand, indices, index) \
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((operand)->hw_type == HW_H_COND \
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|| ((operand)->hw_type == HW_H_PSW) \
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|| ((operand)->hw_type == HW_H_CR \
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&& (indices [index] == 0 || indices [index] == 1)))
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/* Returns true if an output of instruction 'a' is referenced by an operand
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of instruction 'b'. If 'check_outputs' is true then b's outputs are
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checked, otherwise its inputs are examined. */
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static int
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first_writes_to_seconds_operands (a, b, check_outputs)
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m32r_insn * a;
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m32r_insn * b;
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const int check_outputs;
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{
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const CGEN_OPINST * a_operands = CGEN_INSN_OPERANDS (a->insn);
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const CGEN_OPINST * b_ops = CGEN_INSN_OPERANDS (b->insn);
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int a_index;
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/* If at least one of the instructions takes no operands, then there is
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nothing to check. There really are instructions without operands,
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eg 'nop'. */
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if (a_operands == NULL || b_ops == NULL)
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return 0;
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/* Scan the operand list of 'a' looking for an output operand. */
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for (a_index = 0;
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a_operands->type != CGEN_OPINST_END;
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a_index ++, a_operands ++)
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{
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if (a_operands->type == CGEN_OPINST_OUTPUT)
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{
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int b_index;
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const CGEN_OPINST * b_operands = b_ops;
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/* Special Case:
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The Condition bit 'C' is a shadow of the CBR register (control
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register 1) and also a shadow of bit 31 of the program status
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word (control register 0). For now this is handled here, rather
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than by cgen.... */
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if (OPERAND_IS_COND_BIT (a_operands, a->indices, a_index))
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{
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/* Scan operand list of 'b' looking for another reference to the
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condition bit, which goes in the right direction. */
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for (b_index = 0;
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b_operands->type != CGEN_OPINST_END;
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b_index ++, b_operands ++)
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{
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if ((b_operands->type
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== (check_outputs
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? CGEN_OPINST_OUTPUT
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: CGEN_OPINST_INPUT))
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&& OPERAND_IS_COND_BIT (b_operands, b->indices, b_index))
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return 1;
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}
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}
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else
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{
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/* Scan operand list of 'b' looking for an operand that
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references the same hardware element, and which goes in the
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right direction. */
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for (b_index = 0;
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b_operands->type != CGEN_OPINST_END;
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b_index ++, b_operands ++)
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{
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if ((b_operands->type
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== (check_outputs
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? CGEN_OPINST_OUTPUT
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: CGEN_OPINST_INPUT))
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&& (b_operands->hw_type == a_operands->hw_type)
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&& (a->indices [a_index] == b->indices [b_index]))
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return 1;
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}
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}
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}
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}
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return 0;
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}
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/* Returns true if the insn can (potentially) alter the program counter. */
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static int
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writes_to_pc (a)
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m32r_insn * a;
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{
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#if 0 /* Once PC operands are working.... */
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const CGEN_OPINST * a_operands == CGEN_INSN_OPERANDS (gas_cgen_cpu_desc,
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a->insn);
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if (a_operands == NULL)
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return 0;
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while (a_operands->type != CGEN_OPINST_END)
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{
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if (a_operands->operand != NULL
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&& CGEN_OPERAND_INDEX (gas_cgen_cpu_desc, a_operands->operand) == M32R_OPERAND_PC)
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return 1;
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a_operands ++;
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}
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#else
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if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI)
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|| CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI))
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return 1;
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#endif
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return 0;
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}
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/* Returns NULL if the two 16 bit insns can be executed in parallel,
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otherwise it returns a pointer to an error message explaining why not. */
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static const char *
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can_make_parallel (a, b)
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m32r_insn * a;
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m32r_insn * b;
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{
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PIPE_ATTR a_pipe;
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PIPE_ATTR b_pipe;
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/* Make sure the instructions are the right length. */
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if ( CGEN_FIELDS_BITSIZE (& a->fields) != 16
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|| CGEN_FIELDS_BITSIZE (& b->fields) != 16)
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abort();
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if (first_writes_to_seconds_operands (a, b, true))
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return _("Instructions write to the same destination register.");
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a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE);
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b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE);
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/* Make sure that the instructions use the correct execution pipelines. */
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if ( a_pipe == PIPE_NONE
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|| b_pipe == PIPE_NONE)
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return _("Instructions do not use parallel execution pipelines.");
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/* Leave this test for last, since it is the only test that can
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go away if the instructions are swapped, and we want to make
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sure that any other errors are detected before this happens. */
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if ( a_pipe == PIPE_S
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|| b_pipe == PIPE_O)
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return _("Instructions share the same execution pipeline");
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return NULL;
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}
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/* Force the top bit of the second 16-bit insn to be set. */
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static void
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make_parallel (buffer)
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CGEN_INSN_BYTES_PTR buffer;
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{
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#if CGEN_INT_INSN_P
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*buffer |= 0x8000;
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#else
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buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
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|= 0x80;
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#endif
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}
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/* Same as make_parallel except buffer contains the bytes in target order. */
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static void
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target_make_parallel (buffer)
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char *buffer;
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{
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buffer [CGEN_CPU_ENDIAN (gas_cgen_cpu_desc) == CGEN_ENDIAN_BIG ? 0 : 1]
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|= 0x80;
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}
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/* Assemble two instructions with an explicit parallel operation (||) or
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sequential operation (->). */
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static void
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assemble_two_insns (str, str2, parallel_p)
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char * str;
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char * str2;
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int parallel_p;
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{
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char * str3;
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m32r_insn first;
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m32r_insn second;
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char * errmsg;
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char save_str2 = *str2;
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* str2 = 0; /* Seperate the two instructions. */
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/* Make sure the two insns begin on a 32 bit boundary.
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This is also done for the serial case (foo -> bar), relaxing doesn't
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affect insns written like this.
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Note that we must always do this as we can't assume anything about
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whether we're currently on a 32 bit boundary or not. Relaxing may
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change this. */
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fill_insn (0);
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first.debug_sym_link = debug_sym_link;
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debug_sym_link = (sym_linkS *)0;
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/* Parse the first instruction. */
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if (! (first.insn = m32r_cgen_assemble_insn
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(gas_cgen_cpu_desc, str, & first.fields, first.buffer, & errmsg)))
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{
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as_bad (errmsg);
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return;
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}
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/* Check it. */
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if (CGEN_FIELDS_BITSIZE (&first.fields) != 16)
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{
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/* xgettext:c-format */
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as_bad (_("not a 16 bit instruction '%s'"), str);
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return;
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}
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else if (! enable_special
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&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_SPECIAL))
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{
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/* xgettext:c-format */
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as_bad (_("unknown instruction '%s'"), str);
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return;
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}
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else if (! enable_m32rx
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/* FIXME: Need standard macro to perform this test. */
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&& CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' is for the M32RX only"), str);
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return;
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}
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/* Check to see if this is an allowable parallel insn. */
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if (parallel_p && CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_PIPE) == PIPE_NONE)
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{
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/* xgettext:c-format */
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as_bad (_("instruction '%s' cannot be executed in parallel."), str);
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return;
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}
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*str2 = save_str2; /* Restore the original assembly text, just in case it is needed. */
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str3 = str; /* Save the original string pointer. */
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str = str2 + 2; /* Advanced past the parsed string. */
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str2 = str3; /* Remember the entire string in case it is needed for error messages. */
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/* Convert the opcode to lower case. */
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{
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char *s2 = str;
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while (isspace (*s2 ++))
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continue;
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--s2;
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while (isalnum (*s2))
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{
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if (isupper ((unsigned char) *s2))
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*s2 = tolower (*s2);
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s2 ++;
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}
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}
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/* Preserve any fixups that have been generated and reset the list to empty. */
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gas_cgen_save_fixups ();
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/* Get the indices of the operands of the instruction. */
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/* FIXME: CGEN_FIELDS is already recorded, but relying on that fact
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doesn't seem right. Perhaps allow passing fields like we do insn. */
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/* FIXME: ALIAS insns do not have operands, so we use this function
|
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to find the equivalent insn and overwrite the value stored in our
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structure. We still need the original insn, however, since this
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may have certain attributes that are not present in the unaliased
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version (eg relaxability). When aliases behave differently this
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may have to change. */
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first.orig_insn = first.insn;
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{
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CGEN_FIELDS tmp_fields;
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first.insn = cgen_lookup_get_insn_operands
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(gas_cgen_cpu_desc, NULL, INSN_VALUE (first.buffer), NULL, 16,
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first.indices, &tmp_fields);
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}
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if (first.insn == NULL)
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as_fatal (_("internal error: lookup/get operands failed"));
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second.debug_sym_link = NULL;
|
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|
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/* Parse the second instruction. */
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if (! (second.insn = m32r_cgen_assemble_insn
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(gas_cgen_cpu_desc, str, & second.fields, second.buffer, & errmsg)))
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{
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as_bad (errmsg);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check it. */
|
||||
if (CGEN_FIELDS_BITSIZE (&second.fields) != 16)
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("not a 16 bit instruction '%s'"), str);
|
||||
return;
|
||||
}
|
||||
else if (! enable_special
|
||||
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_SPECIAL))
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("unknown instruction '%s'"), str);
|
||||
return;
|
||||
}
|
||||
else if (! enable_m32rx
|
||||
&& CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("instruction '%s' is for the M32RX only"), str);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Check to see if this is an allowable parallel insn. */
|
||||
if (parallel_p && CGEN_INSN_ATTR_VALUE (second.insn, CGEN_INSN_PIPE) == PIPE_NONE)
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("instruction '%s' cannot be executed in parallel."), str);
|
||||
return;
|
||||
}
|
||||
|
||||
if (parallel_p && ! enable_m32rx)
|
||||
{
|
||||
if (CGEN_INSN_NUM (first.insn) != M32R_INSN_NOP
|
||||
&& CGEN_INSN_NUM (second.insn) != M32R_INSN_NOP)
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("'%s': only the NOP instruction can be issued in parallel on the m32r"), str2);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/* Get the indices of the operands of the instruction. */
|
||||
second.orig_insn = second.insn;
|
||||
{
|
||||
CGEN_FIELDS tmp_fields;
|
||||
second.insn = cgen_lookup_get_insn_operands
|
||||
(gas_cgen_cpu_desc, NULL, INSN_VALUE (second.buffer), NULL, 16,
|
||||
second.indices, &tmp_fields);
|
||||
}
|
||||
|
||||
if (second.insn == NULL)
|
||||
as_fatal (_("internal error: lookup/get operands failed"));
|
||||
|
||||
/* We assume that if the first instruction writes to a register that is
|
||||
read by the second instruction it is because the programmer intended
|
||||
this to happen, (after all they have explicitly requested that these
|
||||
two instructions be executed in parallel). Although if the global
|
||||
variable warn_explicit_parallel_conflicts is true then we do generate
|
||||
a warning message. Similarly we assume that parallel branch and jump
|
||||
instructions are deliberate and should not produce errors. */
|
||||
|
||||
if (parallel_p && warn_explicit_parallel_conflicts)
|
||||
{
|
||||
if (first_writes_to_seconds_operands (& first, & second, false))
|
||||
/* xgettext:c-format */
|
||||
as_warn (_("%s: output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?"), str2);
|
||||
|
||||
if (first_writes_to_seconds_operands (& second, & first, false))
|
||||
/* xgettext:c-format */
|
||||
as_warn (_("%s: output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?"), str2);
|
||||
}
|
||||
|
||||
if (!parallel_p
|
||||
|| (errmsg = (char *) can_make_parallel (& first, & second)) == NULL)
|
||||
{
|
||||
/* Get the fixups for the first instruction. */
|
||||
gas_cgen_swap_fixups ();
|
||||
|
||||
/* Write it out. */
|
||||
expand_debug_syms (first.debug_sym_link, 1);
|
||||
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
||||
CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
|
||||
|
||||
/* Force the top bit of the second insn to be set. */
|
||||
if (parallel_p)
|
||||
make_parallel (second.buffer);
|
||||
|
||||
/* Get its fixups. */
|
||||
gas_cgen_restore_fixups ();
|
||||
|
||||
/* Write it out. */
|
||||
expand_debug_syms (second.debug_sym_link, 1);
|
||||
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
||||
CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
|
||||
}
|
||||
/* Try swapping the instructions to see if they work that way. */
|
||||
else if (can_make_parallel (& second, & first) == NULL)
|
||||
{
|
||||
/* Write out the second instruction first. */
|
||||
expand_debug_syms (second.debug_sym_link, 1);
|
||||
gas_cgen_finish_insn (second.orig_insn, second.buffer,
|
||||
CGEN_FIELDS_BITSIZE (& second.fields), 0, NULL);
|
||||
|
||||
/* Force the top bit of the first instruction to be set. */
|
||||
make_parallel (first.buffer);
|
||||
|
||||
/* Get the fixups for the first instruction. */
|
||||
gas_cgen_restore_fixups ();
|
||||
|
||||
/* Write out the first instruction. */
|
||||
expand_debug_syms (first.debug_sym_link, 1);
|
||||
gas_cgen_finish_insn (first.orig_insn, first.buffer,
|
||||
CGEN_FIELDS_BITSIZE (& first.fields), 0, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
as_bad ("'%s': %s", str2, errmsg);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set these so m32r_fill_insn can use them. */
|
||||
prev_seg = now_seg;
|
||||
prev_subseg = now_subseg;
|
||||
}
|
||||
|
||||
void
|
||||
md_assemble (str)
|
||||
|
|
@ -479,6 +977,19 @@ md_assemble (str)
|
|||
/* Initialize GAS's cgen interface for a new instruction. */
|
||||
gas_cgen_init_parse ();
|
||||
|
||||
/* Look for a parallel instruction seperator. */
|
||||
if ((str2 = strstr (str, "||")) != NULL)
|
||||
{
|
||||
assemble_two_insns (str, str2, 1);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Also look for a sequential instruction seperator. */
|
||||
if ((str2 = strstr (str, "->")) != NULL)
|
||||
{
|
||||
assemble_two_insns (str, str2, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
insn.debug_sym_link = debug_sym_link;
|
||||
debug_sym_link = (sym_linkS *)0;
|
||||
|
|
@ -492,6 +1003,20 @@ md_assemble (str)
|
|||
return;
|
||||
}
|
||||
|
||||
if (! enable_special
|
||||
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_SPECIAL))
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("unknown instruction '%s'"), str);
|
||||
return;
|
||||
}
|
||||
else if (! enable_m32rx
|
||||
&& CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MACH) == (1 << MACH_M32RX))
|
||||
{
|
||||
/* xgettext:c-format */
|
||||
as_bad (_("instruction '%s' is for the M32RX only"), str);
|
||||
return;
|
||||
}
|
||||
|
||||
if (CGEN_INSN_BITSIZE (insn.insn) == 32)
|
||||
{
|
||||
|
|
@ -513,16 +1038,62 @@ md_assemble (str)
|
|||
else
|
||||
{
|
||||
int on_32bit_boundary_p;
|
||||
int swap = false;
|
||||
|
||||
if (CGEN_INSN_BITSIZE (insn.insn) != 16)
|
||||
abort();
|
||||
|
||||
insn.orig_insn = insn.insn;
|
||||
|
||||
/* If the previous insn was relaxable, then it may be expanded
|
||||
to fill the current 16 bit slot. Emit a NOP here to occupy
|
||||
this slot, so that we can start at optimizing at a 32 bit
|
||||
boundary. */
|
||||
if (prev_insn.insn && seen_relaxable_p && optimize)
|
||||
fill_insn (0);
|
||||
|
||||
if (enable_m32rx)
|
||||
{
|
||||
/* Get the indices of the operands of the instruction.
|
||||
FIXME: See assemble_parallel for notes on orig_insn. */
|
||||
{
|
||||
CGEN_FIELDS tmp_fields;
|
||||
insn.insn = cgen_lookup_get_insn_operands
|
||||
(gas_cgen_cpu_desc, NULL, INSN_VALUE (insn.buffer), NULL,
|
||||
16, insn.indices, &tmp_fields);
|
||||
}
|
||||
|
||||
if (insn.insn == NULL)
|
||||
as_fatal (_("internal error: lookup/get operands failed"));
|
||||
}
|
||||
|
||||
/* Compute whether we're on a 32 bit boundary or not.
|
||||
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
||||
on_32bit_boundary_p = prev_insn.insn == NULL;
|
||||
|
||||
/* Look to see if this instruction can be combined with the
|
||||
previous instruction to make one, parallel, 32 bit instruction.
|
||||
If the previous instruction (potentially) changed the flow of
|
||||
program control, then it cannot be combined with the current
|
||||
instruction. If the current instruction is relaxable, then it
|
||||
might be replaced with a longer version, so we cannot combine it.
|
||||
Also if the output of the previous instruction is used as an
|
||||
input to the current instruction then it cannot be combined.
|
||||
Otherwise call can_make_parallel() with both orderings of the
|
||||
instructions to see if they can be combined. */
|
||||
if ( ! on_32bit_boundary_p
|
||||
&& enable_m32rx
|
||||
&& optimize
|
||||
&& CGEN_INSN_ATTR_VALUE (insn.orig_insn, CGEN_INSN_RELAXABLE) == 0
|
||||
&& ! writes_to_pc (& prev_insn)
|
||||
&& ! first_writes_to_seconds_operands (& prev_insn, &insn, false)
|
||||
)
|
||||
{
|
||||
if (can_make_parallel (& prev_insn, & insn) == NULL)
|
||||
make_parallel (insn.buffer);
|
||||
else if (can_make_parallel (& insn, & prev_insn) == NULL)
|
||||
swap = true;
|
||||
}
|
||||
|
||||
expand_debug_syms (insn.debug_sym_link, 1);
|
||||
|
||||
|
|
@ -543,6 +1114,33 @@ md_assemble (str)
|
|||
insn.fixups[i] = fi.fixups[i];
|
||||
}
|
||||
|
||||
if (swap)
|
||||
{
|
||||
int i,tmp;
|
||||
|
||||
#define SWAP_BYTES(a,b) tmp = a; a = b; b = tmp
|
||||
|
||||
/* Swap the two insns */
|
||||
SWAP_BYTES (prev_insn.addr [0], insn.addr [0]);
|
||||
SWAP_BYTES (prev_insn.addr [1], insn.addr [1]);
|
||||
|
||||
target_make_parallel (insn.addr);
|
||||
|
||||
/* Swap any relaxable frags recorded for the two insns. */
|
||||
/* FIXME: Clarify. relaxation precludes parallel insns */
|
||||
if (prev_insn.frag->fr_opcode == prev_insn.addr)
|
||||
prev_insn.frag->fr_opcode = insn.addr;
|
||||
else if (insn.frag->fr_opcode == insn.addr)
|
||||
insn.frag->fr_opcode = prev_insn.addr;
|
||||
|
||||
/* Update the addresses in any fixups.
|
||||
Note that we don't have to handle the case where each insn is in
|
||||
a different frag as we ensure they're in the same frag above. */
|
||||
for (i = 0; i < prev_insn.num_fixups; ++i)
|
||||
prev_insn.fixups[i]->fx_where += 2;
|
||||
for (i = 0; i < insn.num_fixups; ++i)
|
||||
insn.fixups[i]->fx_where -= 2;
|
||||
}
|
||||
|
||||
/* Keep track of whether we've seen a pair of 16 bit insns.
|
||||
prev_insn.insn is NULL when we're on a 32 bit boundary. */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue