sim: riscv: move libsim.a creation to top-level
The objects are still compiled in the subdir, but the creation of the archive itself is in the top-level. This is a required step before we can move compilation itself up, and makes it easier to review. The downside is that each object compile is a recursive make instead of a single one. On my 4 core system, it adds ~100msec to the build per port, so it's not great, but it shouldn't be a big deal. This will go away of course once the top-level compiles objects.
This commit is contained in:
Mike Frysinger
parent
3373e27fe1
commit
91344291e0
3 changed files with 83 additions and 31 deletions
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@ -312,19 +312,20 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
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@SIM_ENABLE_ARCH_ppc_TRUE@am__append_116 = ppc/run ppc/psim
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@SIM_ENABLE_ARCH_pru_TRUE@am__append_117 = pru/libsim.a
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@SIM_ENABLE_ARCH_pru_TRUE@am__append_118 = pru/run
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@SIM_ENABLE_ARCH_riscv_TRUE@am__append_119 = riscv/run
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@SIM_ENABLE_ARCH_rl78_TRUE@am__append_120 = rl78/run
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@SIM_ENABLE_ARCH_rx_TRUE@am__append_121 = rx/run
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_122 = sh/run
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_123 = \
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@SIM_ENABLE_ARCH_riscv_TRUE@am__append_119 = riscv/libsim.a
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@SIM_ENABLE_ARCH_riscv_TRUE@am__append_120 = riscv/run
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@SIM_ENABLE_ARCH_rl78_TRUE@am__append_121 = rl78/run
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@SIM_ENABLE_ARCH_rx_TRUE@am__append_122 = rx/run
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_123 = sh/run
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_124 = \
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@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
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@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_124 = $(sh_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_125 = sh/gencode
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_126 = $(sh_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_127 = v850/run
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_128 = \
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_125 = $(sh_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_126 = sh/gencode
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@SIM_ENABLE_ARCH_sh_TRUE@am__append_127 = $(sh_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_128 = v850/run
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_129 = \
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
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@ -333,8 +334,8 @@ TESTS = testsuite/common/bits32m0$(EXEEXT) \
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_129 = $(v850_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_130 = $(v850_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_v850_TRUE@am__append_131 = $(v850_BUILD_OUTPUTS)
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subdir = .
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ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
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am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
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@ -811,6 +812,18 @@ pru_libsim_a_AR = $(AR) $(ARFLAGS)
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@SIM_ENABLE_ARCH_pru_TRUE@ pru/sim-resume.o
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am_pru_libsim_a_OBJECTS =
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pru_libsim_a_OBJECTS = $(am_pru_libsim_a_OBJECTS)
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riscv_libsim_a_AR = $(AR) $(ARFLAGS)
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_DEPENDENCIES = \
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_OBJECTS) \
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst \
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@SIM_ENABLE_ARCH_riscv_TRUE@ %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst \
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@SIM_ENABLE_ARCH_riscv_TRUE@ %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o riscv/machs.o \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.o riscv/sim-main.o \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o
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am_riscv_libsim_a_OBJECTS =
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riscv_libsim_a_OBJECTS = $(am_riscv_libsim_a_OBJECTS)
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@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) \
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@SIM_ENABLE_IGEN_TRUE@ igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \
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@SIM_ENABLE_IGEN_TRUE@ igen/ld-decode$(EXEEXT) \
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@ -1147,11 +1160,12 @@ SOURCES = $(aarch64_libsim_a_SOURCES) $(arm_libsim_a_SOURCES) \
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$(mips_libsim_a_SOURCES) $(mn10300_libsim_a_SOURCES) \
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$(moxie_libsim_a_SOURCES) $(msp430_libsim_a_SOURCES) \
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$(or1k_libsim_a_SOURCES) $(pru_libsim_a_SOURCES) \
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$(aarch64_run_SOURCES) $(arm_run_SOURCES) $(avr_run_SOURCES) \
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$(bfin_run_SOURCES) $(bpf_run_SOURCES) $(cr16_gencode_SOURCES) \
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$(cr16_run_SOURCES) $(cris_run_SOURCES) \
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$(cris_rvdummy_SOURCES) $(d10v_gencode_SOURCES) \
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$(d10v_run_SOURCES) $(erc32_run_SOURCES) erc32/sis.c \
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$(riscv_libsim_a_SOURCES) $(aarch64_run_SOURCES) \
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$(arm_run_SOURCES) $(avr_run_SOURCES) $(bfin_run_SOURCES) \
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$(bpf_run_SOURCES) $(cr16_gencode_SOURCES) $(cr16_run_SOURCES) \
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$(cris_run_SOURCES) $(cris_rvdummy_SOURCES) \
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$(d10v_gencode_SOURCES) $(d10v_run_SOURCES) \
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$(erc32_run_SOURCES) erc32/sis.c \
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$(example_synacor_run_SOURCES) $(frv_run_SOURCES) \
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$(ft32_run_SOURCES) $(h8300_run_SOURCES) \
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$(igen_filter_SOURCES) $(igen_gen_SOURCES) \
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@ -1715,12 +1729,12 @@ noinst_LIBRARIES = common/libcommon.a $(am__append_5) $(am__append_8) \
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$(am__append_72) $(am__append_78) $(am__append_84) \
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$(am__append_86) $(am__append_91) $(am__append_101) \
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$(am__append_107) $(am__append_109) $(am__append_111) \
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$(am__append_117)
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$(am__append_117) $(am__append_119)
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BUILT_SOURCES = $(am__append_19) $(am__append_24) $(am__append_32) \
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$(am__append_37) $(am__append_49) $(am__append_58) \
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$(am__append_64) $(am__append_75) $(am__append_94) \
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$(am__append_104) $(am__append_113) $(am__append_123) \
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$(am__append_128)
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$(am__append_104) $(am__append_113) $(am__append_124) \
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$(am__append_129)
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CLEANFILES = common/version.c common/version.c-stamp \
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testsuite/common/bits-gen testsuite/common/bits32m0.c \
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testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
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@ -1735,7 +1749,7 @@ MOSTLYCLEANFILES = core $(common_HW_CONFIG_H_TARGETS) $(patsubst \
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$(am__append_51) $(am__append_60) $(am__append_66) \
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$(am__append_71) $(am__append_77) $(am__append_83) \
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$(am__append_99) $(am__append_106) $(am__append_115) \
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$(am__append_126) $(am__append_130)
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$(am__append_127) $(am__append_131)
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AM_CFLAGS = $(WERROR_CFLAGS) $(WARN_CFLAGS)
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AM_CPPFLAGS = $(INCGNU) -I$(srcroot)/include -I../bfd -I.. \
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$(SIM_HW_CFLAGS) $(SIM_INLINE) -I$(srcdir)/common \
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@ -1750,8 +1764,8 @@ SIM_ALL_RECURSIVE_DEPS = common/libcommon.a \
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$(am__append_33) $(am__append_38) $(am__append_50) \
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$(am__append_59) $(am__append_65) $(am__append_69) \
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$(am__append_76) $(am__append_81) $(am__append_98) \
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$(am__append_105) $(am__append_114) $(am__append_124) \
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$(am__append_129)
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$(am__append_105) $(am__append_114) $(am__append_125) \
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$(am__append_130)
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SIM_INSTALL_DATA_LOCAL_DEPS =
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SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_43)
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SIM_UNINSTALL_LOCAL_DEPS = $(am__append_44)
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@ -2715,6 +2729,17 @@ testsuite_common_CPPFLAGS = \
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@SIM_ENABLE_ARCH_pru_TRUE@ pru/libsim.a \
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@SIM_ENABLE_ARCH_pru_TRUE@ $(SIM_COMMON_LIBS)
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_SOURCES =
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv_libsim_a_LIBADD = \
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(common_libcommon_a_OBJECTS) \
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/%,$(SIM_NEW_COMMON_OBJS)) \
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(patsubst %,riscv/dv-%.o,$(SIM_HW_DEVICES)) \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/interp.o \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/machs.o \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/modules.o \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-main.o \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/sim-resume.o
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_SOURCES =
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv_run_LDADD = \
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@SIM_ENABLE_ARCH_riscv_TRUE@ riscv/nrun.o \
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@ -3244,6 +3269,14 @@ pru/libsim.a: $(pru_libsim_a_OBJECTS) $(pru_libsim_a_DEPENDENCIES) $(EXTRA_pru_l
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$(AM_V_at)-rm -f pru/libsim.a
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$(AM_V_AR)$(pru_libsim_a_AR) pru/libsim.a $(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD)
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$(AM_V_at)$(RANLIB) pru/libsim.a
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riscv/$(am__dirstamp):
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@$(MKDIR_P) riscv
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@: > riscv/$(am__dirstamp)
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riscv/libsim.a: $(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_DEPENDENCIES) $(EXTRA_riscv_libsim_a_DEPENDENCIES) riscv/$(am__dirstamp)
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$(AM_V_at)-rm -f riscv/libsim.a
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$(AM_V_AR)$(riscv_libsim_a_AR) riscv/libsim.a $(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD)
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$(AM_V_at)$(RANLIB) riscv/libsim.a
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clean-checkPROGRAMS:
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@list='$(check_PROGRAMS)'; test -n "$$list" || exit 0; \
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@ -3465,9 +3498,6 @@ ppc/run$(EXEEXT): $(ppc_run_OBJECTS) $(ppc_run_DEPENDENCIES) $(EXTRA_ppc_run_DEP
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pru/run$(EXEEXT): $(pru_run_OBJECTS) $(pru_run_DEPENDENCIES) $(EXTRA_pru_run_DEPENDENCIES) pru/$(am__dirstamp)
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@rm -f pru/run$(EXEEXT)
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$(AM_V_CCLD)$(LINK) $(pru_run_OBJECTS) $(pru_run_LDADD) $(LIBS)
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riscv/$(am__dirstamp):
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@$(MKDIR_P) riscv
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@: > riscv/$(am__dirstamp)
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riscv/run$(EXEEXT): $(riscv_run_OBJECTS) $(riscv_run_DEPENDENCIES) $(EXTRA_riscv_run_DEPENDENCIES) riscv/$(am__dirstamp)
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@rm -f riscv/run$(EXEEXT)
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@ -5253,6 +5283,13 @@ testsuite/common/bits64m63.c: testsuite/common/bits-gen$(EXEEXT) testsuite/commo
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@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c
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@SIM_ENABLE_ARCH_pru_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
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@SIM_ENABLE_ARCH_riscv_TRUE@$(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD): riscv/hw-config.h
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: riscv/%.c
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
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@SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: common/%.c
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@SIM_ENABLE_ARCH_riscv_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
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@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: rl78/%.c | rl78/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
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@SIM_ENABLE_ARCH_rl78_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
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@ -17,12 +17,7 @@
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## COMMON_PRE_CONFIG_FRAG
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SIM_OBJS = \
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$(SIM_NEW_COMMON_OBJS) \
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sim-resume.o \
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interp.o \
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machs.o \
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sim-main.o
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SIM_LIBSIM =
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SIM_EXTRA_CFLAGS = -DWITH_TARGET_WORD_BITSIZE=@SIM_RISCV_BITSIZE@
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@ -16,6 +16,26 @@
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## You should have received a copy of the GNU General Public License
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## along with this program. If not, see <http://www.gnu.org/licenses/>.
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%C%_libsim_a_SOURCES =
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%C%_libsim_a_LIBADD = \
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$(common_libcommon_a_OBJECTS) \
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$(patsubst %,%D%/%,$(SIM_NEW_COMMON_OBJS)) \
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$(patsubst %,%D%/dv-%.o,$(SIM_HW_DEVICES)) \
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%D%/interp.o \
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%D%/machs.o \
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%D%/modules.o \
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%D%/sim-main.o \
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%D%/sim-resume.o
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$(%C%_libsim_a_OBJECTS) $(%C%_libsim_a_LIBADD): %D%/hw-config.h
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noinst_LIBRARIES += %D%/libsim.a
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%D%/%.o: %D%/%.c
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$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
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%D%/%.o: common/%.c
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$(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
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%C%_run_SOURCES =
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%C%_run_LDADD = \
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%D%/nrun.o \
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