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sim: mips: invert sim_state storage

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This commit is contained in:
Mike Frysinger 2016-01-21 22:40:43 -05:00
parent 937af0fde5
commit 8ea7241cf3
5 changed files with 27 additions and 27 deletions
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12
sim/mips/ChangeLog
View file

@ -1,3 +1,15 @@
2021-05-17 Mike Frysinger <vapier@gentoo.org>
* interp.c (sim_open): Switch to sim_state_alloc_extra.
* micromips.igen: Change SD to mips_sim_state.
* micromipsrun.c (sim_engine_run): Likewise.
* sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define.
(watch_options_install): Delete.
(struct swatch): Delete.
(struct sim_state): Delete.
(struct mips_sim_state): New struct.
(MIPS_SIM_STATE): Define.
2021-05-16 Mike Frysinger <vapier@gentoo.org>
* interp.c: Replace config.h include with defs.h.

3
sim/mips/interp.c
View file

@ -343,7 +343,8 @@ sim_open (SIM_OPEN_KIND kind, host_callback *cb,
struct bfd *abfd, char * const *argv)
{
int i;
SIM_DESC sd = sim_state_alloc (kind, cb);
SIM_DESC sd = sim_state_alloc_extra (kind, cb,
sizeof (struct mips_sim_state));
sim_cpu *cpu;
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);

6
sim/mips/micromips.igen
View file

@ -58,7 +58,8 @@
*micromips32:
*micromips64:
{
SD->isa_mode = target & 0x1;
struct mips_sim_state *state = MIPS_SIM_STATE (SD);
state->isa_mode = target & 0x1;
return (target & (-(1 << 1)));
}
@ -1076,10 +1077,11 @@
*micromips32:
*micromips64:
{
struct mips_sim_state *state = MIPS_SIM_STATE (SD);
address_word region = (NIA & MASK (63, 26));
NIA = do_micromips_jal (SD_, (region | (IMM_SHIFT_2BIT)) | ISA_MODE_MIPS32,
NIA, MICROMIPS_DELAYSLOT_SIZE_32);
SD->isa_mode = ISA_MODE_MIPS32;
state->isa_mode = ISA_MODE_MIPS32;
}
000000,00000,5.RS,0000111100,111100:POOL32A:32::JR

9
sim/mips/micromipsrun.c
View file

@ -80,10 +80,11 @@ void
sim_engine_run (SIM_DESC sd, int next_cpu_nr, int nr_cpus,
int signal)
{
struct mips_sim_state *state = MIPS_SIM_STATE (sd);
micromips_m32_instruction_word instruction_0;
sim_cpu *cpu = STATE_CPU (sd, next_cpu_nr);
micromips32_instruction_address cia = CPU_PC_GET (cpu);
sd->isa_mode = ISA_MODE_MIPS32;
state->isa_mode = ISA_MODE_MIPS32;
while (1)
{
@ -95,17 +96,17 @@ sim_engine_run (SIM_DESC sd, int next_cpu_nr, int nr_cpus,
from the elf header.
2. Setting the correct isa mode after a MIPS32 jump or branch
instruction. */
if ((sd->isa_mode == ISA_MODE_MIPS32)
if ((state->isa_mode == ISA_MODE_MIPS32)
&& ((cia & 0x1) == ISA_MODE_MICROMIPS))
{
sd->isa_mode = ISA_MODE_MICROMIPS;
state->isa_mode = ISA_MODE_MICROMIPS;
cia = cia & ~0x1;
}
#if defined (ENGINE_ISSUE_PREFIX_HOOK)
ENGINE_ISSUE_PREFIX_HOOK ();
#endif
switch (sd->isa_mode)
switch (state->isa_mode)
{
case ISA_MODE_MICROMIPS:
nia =

24
sim/mips/sim-main.h
View file

@ -20,6 +20,8 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */
#ifndef SIM_MAIN_H
#define SIM_MAIN_H
#define SIM_HAVE_COMMON_SIM_STATE
/* MIPS uses an unusual format for floating point quiet NaNs. */
#define SIM_QUIET_NAN_NEGATED
@ -475,30 +477,12 @@ struct _sim_cpu {
extern void mips_sim_close (SIM_DESC sd, int quitting);
#define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)
/* MIPS specific simulator watch config */
void watch_options_install (SIM_DESC sd);
struct swatch {
sim_event *pc;
sim_event *clock;
sim_event *cycles;
};
/* FIXME: At present much of the simulator is still static */
struct sim_state {
struct swatch watch;
sim_cpu *cpu[MAX_NR_PROCESSORS];
struct mips_sim_state {
/* microMIPS ISA mode. */
int isa_mode;
sim_state_base base;
};
#define MIPS_SIM_STATE(sd) ((struct mips_sim_state *) STATE_ARCH_DATA (sd))
/* Status information: */