* mips.h (M_ULD, M_ULD_A, M_USD, M_USD_A): Define.
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2 changed files with 15 additions and 2 deletions
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@ -218,14 +218,18 @@ struct mips_opcode
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#define INSN_WRITE_HI 0x01000000
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/* Modifies the LO register. */
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#define INSN_WRITE_LO 0x02000000
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/* Instruction stores value into memory. */
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#define INSN_STORE_MEMORY 0x04000000
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/* Takes a trap (easier to keep out of delay slot). */
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#define INSN_TRAP 0x04000000
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/* Instruction stores value into memory. */
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#define INSN_STORE_MEMORY 0x08000000
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/* MIPS ISA field--CPU level at which insn is supported. */
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#define INSN_ISA 0x70000000
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/* MIPS ISA 2 instruction (R6000 or R4000). */
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#define INSN_ISA2 0x10000000
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/* MIPS ISA 3 instruction (R4000). */
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#define INSN_ISA3 0x20000000
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/* MIPS R4650 instruction. */
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#define INSN_4650 0x30000000
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/* Instruction is actually a macro. It should be ignored by the
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disassembler, and requires special treatment by the assembler. */
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@ -425,6 +429,8 @@ enum {
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M_TNE_I,
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M_TRUNCWD,
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M_TRUNCWS,
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M_ULD,
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M_ULD_A,
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M_ULH,
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M_ULH_A,
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M_ULHU,
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@ -435,6 +441,8 @@ enum {
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M_USH_A,
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M_USW,
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M_USW_A,
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M_USD,
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M_USD_A,
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M_XOR_I
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};
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