aarch64: Add WFET instruction for Armv8.7-a
This patch adds new to Armv8.7 WFET instruction which take one operand:
WFET <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFET (Wait For Event with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 565 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: New test.
* testsuite/gas/aarch64/system-5.s: New test.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
and operand description.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
This commit is contained in:
Przemyslaw Wirkus
parent
fd195909ce
commit
82503ca7ed
7 changed files with 1429 additions and 1349 deletions
3
gas/NEWS
3
gas/NEWS
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@ -21,7 +21,8 @@
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* Add support for Armv8-R and Armv8.7-A AArch64.
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* Add support for DSB memory nXS barrier instruction for Armv8.7 AArch64.
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* Add support for DSB memory nXS barrier and WFET instruction for Armv8.7
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AArch64.
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* Add support for Intel TDX instructions.
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39
gas/testsuite/gas/aarch64/system-5.d
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39
gas/testsuite/gas/aarch64/system-5.d
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@ -0,0 +1,39 @@
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#name: WFET (Wait For Event with Timeout) instruction
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#objdump: -dr
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.*: file format .*
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Disassembly of section \.text:
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0+ <.*>:
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.*: d5031000 wfet x0
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.*: d5031001 wfet x1
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.*: d5031002 wfet x2
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.*: d5031003 wfet x3
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.*: d5031004 wfet x4
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.*: d5031005 wfet x5
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.*: d5031006 wfet x6
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.*: d5031007 wfet x7
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.*: d5031008 wfet x8
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.*: d5031009 wfet x9
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.*: d503100a wfet x10
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.*: d503100b wfet x11
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.*: d503100c wfet x12
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.*: d503100d wfet x13
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.*: d503100e wfet x14
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.*: d503100f wfet x15
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.*: d5031010 wfet x16
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.*: d5031011 wfet x17
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.*: d5031012 wfet x18
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.*: d5031013 wfet x19
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.*: d5031014 wfet x20
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.*: d5031015 wfet x21
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.*: d5031016 wfet x22
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.*: d5031017 wfet x23
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.*: d5031018 wfet x24
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.*: d5031019 wfet x25
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.*: d503101a wfet x26
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.*: d503101b wfet x27
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.*: d503101c wfet x28
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.*: d503101d wfet x29
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.*: d503101e wfet x30
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34
gas/testsuite/gas/aarch64/system-5.s
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34
gas/testsuite/gas/aarch64/system-5.s
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@ -0,0 +1,34 @@
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/* Wait For Event with Timeout is a Armv8.7 instruction. */
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.arch armv8.7-a
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wfet x0
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wfet x1
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wfet x2
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wfet x3
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wfet x4
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wfet x5
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wfet x6
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wfet x7
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wfet x8
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wfet x9
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wfet x10
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wfet x11
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wfet x12
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wfet x13
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wfet x14
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wfet x15
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wfet x16
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wfet x17
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wfet x18
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wfet x19
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wfet x20
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wfet x21
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wfet x22
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wfet x23
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wfet x24
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wfet x25
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wfet x26
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wfet x27
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wfet x28
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wfet x29
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wfet x30
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@ -426,14 +426,14 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1184: /* movz */
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value = 1184; /* --> movz. */
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break;
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case 1240: /* autibsp */
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case 1239: /* autibz */
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case 1238: /* autiasp */
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case 1237: /* autiaz */
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case 1236: /* pacibsp */
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case 1235: /* pacibz */
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case 1234: /* paciasp */
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case 1233: /* paciaz */
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case 1241: /* autibsp */
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case 1240: /* autibz */
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case 1239: /* autiasp */
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case 1238: /* autiaz */
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case 1237: /* pacibsp */
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case 1236: /* pacibz */
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case 1235: /* paciasp */
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case 1234: /* paciaz */
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case 1211: /* tsb */
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case 1210: /* psb */
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case 1209: /* esb */
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@ -462,9 +462,9 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1214: /* dsb */
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value = 1214; /* --> dsb. */
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break;
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case 1228: /* cpp */
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case 1227: /* dvp */
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case 1226: /* cfp */
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case 1229: /* cpp */
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case 1228: /* dvp */
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case 1227: /* cfp */
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case 1225: /* tlbi */
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case 1224: /* ic */
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case 1223: /* dc */
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@ -472,125 +472,128 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
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case 1221: /* sys */
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value = 1221; /* --> sys. */
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break;
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case 2038: /* bic */
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case 1288: /* and */
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value = 1288; /* --> and. */
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case 1226: /* wfet */
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value = 1226; /* --> wfet. */
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break;
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case 1271: /* mov */
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case 1290: /* and */
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value = 1290; /* --> and. */
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case 2039: /* bic */
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case 1289: /* and */
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value = 1289; /* --> and. */
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break;
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case 1275: /* movs */
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case 1291: /* ands */
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value = 1291; /* --> ands. */
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case 1272: /* mov */
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case 1291: /* and */
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value = 1291; /* --> and. */
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break;
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case 2039: /* cmple */
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case 1326: /* cmpge */
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value = 1326; /* --> cmpge. */
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case 1276: /* movs */
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case 1292: /* ands */
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value = 1292; /* --> ands. */
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break;
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case 2042: /* cmplt */
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case 1329: /* cmpgt */
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value = 1329; /* --> cmpgt. */
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case 2040: /* cmple */
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case 1327: /* cmpge */
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value = 1327; /* --> cmpge. */
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break;
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case 2040: /* cmplo */
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case 1331: /* cmphi */
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value = 1331; /* --> cmphi. */
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case 2043: /* cmplt */
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case 1330: /* cmpgt */
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value = 1330; /* --> cmpgt. */
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break;
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case 2041: /* cmpls */
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case 1334: /* cmphs */
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value = 1334; /* --> cmphs. */
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case 2041: /* cmplo */
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case 1332: /* cmphi */
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value = 1332; /* --> cmphi. */
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break;
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case 1268: /* mov */
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case 1356: /* cpy */
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value = 1356; /* --> cpy. */
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case 2042: /* cmpls */
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case 1335: /* cmphs */
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value = 1335; /* --> cmphs. */
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break;
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case 1270: /* mov */
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case 1269: /* mov */
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case 1357: /* cpy */
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value = 1357; /* --> cpy. */
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break;
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case 2049: /* fmov */
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case 1273: /* mov */
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case 1271: /* mov */
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case 1358: /* cpy */
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value = 1358; /* --> cpy. */
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break;
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case 1263: /* mov */
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case 1370: /* dup */
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value = 1370; /* --> dup. */
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case 2050: /* fmov */
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case 1274: /* mov */
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case 1359: /* cpy */
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value = 1359; /* --> cpy. */
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break;
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case 1265: /* mov */
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case 1262: /* mov */
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case 1264: /* mov */
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case 1371: /* dup */
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value = 1371; /* --> dup. */
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break;
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case 2048: /* fmov */
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case 1267: /* mov */
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case 1266: /* mov */
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case 1263: /* mov */
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case 1372: /* dup */
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value = 1372; /* --> dup. */
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break;
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case 1266: /* mov */
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case 1373: /* dupm */
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value = 1373; /* --> dupm. */
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case 2049: /* fmov */
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case 1268: /* mov */
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case 1373: /* dup */
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value = 1373; /* --> dup. */
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break;
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case 2043: /* eon */
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case 1375: /* eor */
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value = 1375; /* --> eor. */
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case 1267: /* mov */
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case 1374: /* dupm */
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value = 1374; /* --> dupm. */
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break;
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case 1276: /* not */
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case 1377: /* eor */
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value = 1377; /* --> eor. */
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case 2044: /* eon */
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case 1376: /* eor */
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value = 1376; /* --> eor. */
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break;
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case 1277: /* nots */
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case 1378: /* eors */
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value = 1378; /* --> eors. */
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case 1277: /* not */
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case 1378: /* eor */
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value = 1378; /* --> eor. */
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break;
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case 2044: /* facle */
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case 1383: /* facge */
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value = 1383; /* --> facge. */
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case 1278: /* nots */
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case 1379: /* eors */
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value = 1379; /* --> eors. */
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break;
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case 2045: /* faclt */
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case 1384: /* facgt */
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value = 1384; /* --> facgt. */
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case 2045: /* facle */
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case 1384: /* facge */
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value = 1384; /* --> facge. */
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break;
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case 2046: /* fcmle */
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case 1397: /* fcmge */
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value = 1397; /* --> fcmge. */
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case 2046: /* faclt */
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case 1385: /* facgt */
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value = 1385; /* --> facgt. */
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break;
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case 2047: /* fcmlt */
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case 1399: /* fcmgt */
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value = 1399; /* --> fcmgt. */
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case 2047: /* fcmle */
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case 1398: /* fcmge */
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value = 1398; /* --> fcmge. */
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break;
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case 2048: /* fcmlt */
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case 1400: /* fcmgt */
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value = 1400; /* --> fcmgt. */
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break;
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case 1261: /* fmov */
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case 1406: /* fcpy */
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value = 1406; /* --> fcpy. */
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break;
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case 1260: /* fmov */
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case 1405: /* fcpy */
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value = 1405; /* --> fcpy. */
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case 1429: /* fdup */
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value = 1429; /* --> fdup. */
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break;
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case 1259: /* fmov */
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case 1428: /* fdup */
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value = 1428; /* --> fdup. */
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break;
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case 1261: /* mov */
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case 1759: /* orr */
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value = 1759; /* --> orr. */
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break;
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case 2050: /* orn */
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case 1262: /* mov */
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case 1760: /* orr */
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value = 1760; /* --> orr. */
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break;
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case 1264: /* mov */
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case 1762: /* orr */
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value = 1762; /* --> orr. */
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case 2051: /* orn */
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case 1761: /* orr */
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value = 1761; /* --> orr. */
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break;
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case 1274: /* movs */
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case 1763: /* orrs */
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value = 1763; /* --> orrs. */
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case 1265: /* mov */
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case 1763: /* orr */
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value = 1763; /* --> orr. */
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break;
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case 1269: /* mov */
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case 1825: /* sel */
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value = 1825; /* --> sel. */
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case 1275: /* movs */
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case 1764: /* orrs */
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value = 1764; /* --> orrs. */
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break;
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case 1272: /* mov */
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case 1270: /* mov */
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case 1826: /* sel */
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value = 1826; /* --> sel. */
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break;
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case 1273: /* mov */
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case 1827: /* sel */
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value = 1827; /* --> sel. */
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break;
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default: return NULL;
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}
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File diff suppressed because it is too large
Load diff
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@ -311,17 +311,17 @@ static const unsigned op_enum_table [] =
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391,
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413,
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415,
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1264,
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1269,
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1262,
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1261,
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1265,
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1272,
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1274,
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1270,
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1263,
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1262,
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1266,
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1273,
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1275,
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1271,
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1277,
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1276,
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1272,
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1278,
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1277,
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131,
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};
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@ -3867,6 +3867,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
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CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
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CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
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CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
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V8_7_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
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PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
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PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
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PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
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Loading…
Add table
Reference in a new issue