FT32B is a new FT32 family member. It has a code compression scheme, which requires the use of linker relaxations. The change is quite large, so submission is in several parts.
Part 2 adds a relaxation pass, which actually implements the code compression scheme. bfd * archures.c: Add bfd_mach_ft32b. * cpu-ft32.c: Add arch_info_struct. * elf32-ft32.c: Add R_FT32_RELAX, SC0, SC1, DIFF32. (ft32_elf_relocate_section): Add clauses for R_FT32_SC0, SC1, DIFF32. (ft32_reloc_shortable, elf32_ft32_is_diff_reloc, elf32_ft32_adjust_diff_reloc_value, elf32_ft32_adjust_reloc_if_spans_insn, elf32_ft32_relax_delete_bytes, elf32_ft32_relax_is_branch_target, ft32_elf_relax_section): New function. * reloc.c: Add BFD_RELOC_FT32_RELAX, SC0, SC1, DIFF32. * bfd-in2.h: Regenerate. * libbfd.h: Regenerate. gas * config/tc-ft32.c (md_assemble): add relaxation reloc BFD_RELOC_FT32_RELAX. (md_longopts): Add "norelax" and "no-relax". (md_apply_fix): Add reloc BFD_RELOC_FT32_DIFF32. (relaxable_section, ft32_validate_fix_sub, ft32_force_relocation, ft32_allow_local_subtract): New function. * config/tc-ft32.h: remove unused MD_PCREL_FROM_SECTION. * testsuite/gas/ft32/insnsc.s: New test exercising all FT32B shortcodes. include * elf/ft32.h: Add R_FT32_RELAX, SC0, SC1, DIFF32.
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@ -12453,6 +12453,8 @@ is_16bit_abs_reloc (unsigned int reloc_type)
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case EM_CYGNUS_D10V:
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case EM_D10V:
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return reloc_type == 3; /* R_D10V_16. */
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case EM_FT32:
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return reloc_type == 2; /* R_FT32_16. */
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case EM_H8S:
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case EM_H8_300:
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case EM_H8_300H:
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