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Revert "MIPS/Allegrex: Enable dbreak instruction"

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This reverts commit c41020942b.
This commit is contained in:
Maciej W. Rozycki 2024-06-10 16:00:08 +01:00
parent a8463c6844
commit 811f77dc38
3 changed files with 2 additions and 4 deletions
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3
gas/testsuite/gas/mips/allegrex.d
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@ -46,6 +46,5 @@ Disassembly of section .text:
0x00000094 7002003d mfdr \$2,\$0 0x00000094 7002003d mfdr \$2,\$0
0x00000098 7002083d mfdr \$2,\$1 0x00000098 7002083d mfdr \$2,\$1
0x0000009c 7083083d mtdr \$3,\$1 0x0000009c 7083083d mtdr \$3,\$1
0x000000a0 7000003f dbreak 0x000000a0 7000003e dret
0x000000a4 7000003e dret
\.\.\. \.\.\.

1
gas/testsuite/gas/mips/allegrex.s
View file

@ -40,7 +40,6 @@
mfdr $v0, $0 mfdr $v0, $0
mfdr $v0, $1 mfdr $v0, $1
mtdr $v1, $1 mtdr $v1, $1
dbreak
dret dret
# Force some (non-delay-slot) zero bytes, to make 'objdump' print ... # Force some (non-delay-slot) zero bytes, to make 'objdump' print ...

2
opcodes/mips-opc.c
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@ -1030,7 +1030,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 }, {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
{"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 }, {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3, 0, 0 },
{"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 }, {"daddwc", "d,s,t", 0x70000038, 0xfc0007ff, WR_1|RD_2|RD_3|WR_C0|RD_C0, 0, XLR, 0, 0 },
{"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5|AL, 0, 0 }, {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5, 0, 0 },
{"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, {"dclo", "d,s", 0x00000053, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },
{"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 }, {"dclo", "U,s", 0x70000025, 0xfc0007ff, WR_1|RD_2, 0, I64|N55, 0, I69 },
{"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 }, {"dclz", "d,s", 0x00000052, 0xfc1f07ff, WR_1|RD_2, 0, I69, 0, 0 },