2008-03-04 Paul Brook <paul@codesourcery.com>
gas/ * config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New. (arm_ext_v7m): Rename... (arm_ext_m): ... to this. Include v6-M. (do_t_add_sub): Allow narrow low-reg non flag setting adds. (do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m. (md_assemble): Allow wide msr instructions. (insns): Add classifications for v6-m instructions. (arm_cpu_option_table): Add cortex-m1. (arm_arch_option_table): Add armv6-m. (cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants. gas/testsuite/ * gas/arm/archv6m.d: New test. * gas/arm/archv6m.s: New test. * gas/arm/t16-bad.s: Test low register non flag setting add. * gas/arm/t16-bad.l: Update expected output. include/opcode/ * arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define. (ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags. (ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
This commit is contained in:
Paul Brook
parent
fb66452df4
commit
7e8064706d
9 changed files with 116 additions and 27 deletions
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@ -1,3 +1,16 @@
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2008-03-04 Paul Brook <paul@codesourcery.com>
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* config/tc-arm.c (arm_ext_barrier, arm_ext_msr): New.
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(arm_ext_v7m): Rename...
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(arm_ext_m): ... to this. Include v6-M.
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(do_t_add_sub): Allow narrow low-reg non flag setting adds.
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(do_t_mrs, do_t_msr, aeabi_set_public_attributes): Use arm_ext_m.
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(md_assemble): Allow wide msr instructions.
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(insns): Add classifications for v6-m instructions.
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(arm_cpu_option_table): Add cortex-m1.
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(arm_arch_option_table): Add armv6-m.
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(cpu_arch): Add ARM_ARCH_V6M. Fix numbering of other v6 variants.
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2008-03-03 Sterling Augustine <sterling@tensilica.com>
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Bob Wilson <bob.wilson@acm.org>
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@ -192,11 +192,14 @@ static const arm_feature_set arm_ext_v6k = ARM_FEATURE (ARM_EXT_V6K, 0);
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static const arm_feature_set arm_ext_v6z = ARM_FEATURE (ARM_EXT_V6Z, 0);
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static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE (ARM_EXT_V6T2, 0);
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static const arm_feature_set arm_ext_v6_notm = ARM_FEATURE (ARM_EXT_V6_NOTM, 0);
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static const arm_feature_set arm_ext_barrier = ARM_FEATURE (ARM_EXT_BARRIER, 0);
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static const arm_feature_set arm_ext_msr = ARM_FEATURE (ARM_EXT_THUMB_MSR, 0);
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static const arm_feature_set arm_ext_div = ARM_FEATURE (ARM_EXT_DIV, 0);
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static const arm_feature_set arm_ext_v7 = ARM_FEATURE (ARM_EXT_V7, 0);
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static const arm_feature_set arm_ext_v7a = ARM_FEATURE (ARM_EXT_V7A, 0);
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static const arm_feature_set arm_ext_v7r = ARM_FEATURE (ARM_EXT_V7R, 0);
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static const arm_feature_set arm_ext_v7m = ARM_FEATURE (ARM_EXT_V7M, 0);
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static const arm_feature_set arm_ext_m =
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ARM_FEATURE (ARM_EXT_V6M | ARM_EXT_V7M, 0);
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static const arm_feature_set arm_arch_any = ARM_ANY;
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static const arm_feature_set arm_arch_full = ARM_FEATURE (-1, -1);
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@ -8497,25 +8500,25 @@ do_t_add_sub (void)
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return;
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}
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if (inst.instruction == T_MNEM_add)
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if (inst.instruction == T_MNEM_add && (Rd == Rs || Rd == Rn))
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{
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if (Rd == Rs)
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/* Thumb-1 cores (except v6-M) require at least one high
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register in a narrow non flag setting add. */
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if (Rd > 7 || Rn > 7
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|| ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_v6t2)
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|| ARM_CPU_HAS_FEATURE (selected_cpu, arm_ext_msr))
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{
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if (Rd == Rn)
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{
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Rn = Rs;
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Rs = Rd;
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}
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inst.instruction = T_OPCODE_ADD_HI;
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inst.instruction |= (Rd & 8) << 4;
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inst.instruction |= (Rd & 7);
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inst.instruction |= Rn << 3;
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return;
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}
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/* ... because addition is commutative! */
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else if (Rd == Rn)
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{
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inst.instruction = T_OPCODE_ADD_HI;
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inst.instruction |= (Rd & 8) << 4;
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inst.instruction |= (Rd & 7);
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inst.instruction |= Rs << 3;
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return;
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}
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}
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}
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/* If we get here, it can't be done in 16 bits. */
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@ -9806,7 +9809,7 @@ do_t_mrs (void)
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flags = inst.operands[1].imm & (PSR_c|PSR_x|PSR_s|PSR_f|SPSR_BIT);
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if (flags == 0)
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
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_("selected processor does not support "
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"requested special purpose register"));
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}
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@ -9844,7 +9847,7 @@ do_t_msr (void)
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}
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else
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{
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7m),
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constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_m),
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_("selected processor does not support "
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"requested special purpose register"));
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flags |= PSR_f;
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@ -14225,7 +14228,8 @@ md_assemble (char *str)
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{
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/* Implicit require narrow instructions on Thumb-1. This avoids
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relaxation accidentally introducing Thumb-2 instructions. */
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if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23)
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if (opcode->tencode != do_t_blx && opcode->tencode != do_t_branch23
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&& !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
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inst.size_req = 2;
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}
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@ -14279,10 +14283,11 @@ md_assemble (char *str)
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*opcode->tvariant);
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/* Many Thumb-2 instructions also have Thumb-1 variants, so explicitly
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set those bits when Thumb-2 32-bit instructions are seen. ie.
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anything other than bl/blx.
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anything other than bl/blx and v6-M instructions.
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This is overly pessimistic for relaxable instructions. */
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if ((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
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|| inst.relax)
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if (((inst.size == 4 && (inst.instruction & 0xf800e800) != 0xf000e800)
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|| inst.relax)
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&& !ARM_CPU_HAS_FEATURE(*opcode->tvariant, arm_ext_msr))
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ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used,
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arm_ext_v6t2);
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}
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@ -15028,11 +15033,15 @@ static const struct asm_opcode insns[] =
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#undef ARM_VARIANT
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#define ARM_VARIANT &arm_ext_v3 /* ARM 6 Status register instructions. */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &arm_ext_msr
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TCE(mrs, 10f0000, f3ef8000, 2, (APSR_RR, RVC_PSR), mrs, t_mrs),
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TCE(msr, 120f000, f3808000, 2, (RVC_PSR, RR_EXi), msr, t_msr),
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#undef ARM_VARIANT
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#define ARM_VARIANT &arm_ext_v3m /* ARM 7M long multiplies. */
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &arm_ext_v6t2
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TCE(smull, 0c00090, fb800000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
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CM(smull,s, 0d00090, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull),
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TCE(umull, 0800090, fba00000, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mull, t_mull),
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@ -15312,6 +15321,15 @@ static const struct asm_opcode insns[] =
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TCE(sdiv, 0, fb90f0f0, 3, (RR, oRR, RR), 0, t_div),
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TCE(udiv, 0, fbb0f0f0, 3, (RR, oRR, RR), 0, t_div),
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/* ARM V6M/V7 instructions. */
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#undef ARM_VARIANT
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#define ARM_VARIANT &arm_ext_barrier
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#undef THUMB_VARIANT
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#define THUMB_VARIANT &arm_ext_barrier
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TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
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TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
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TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
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/* ARM V7 instructions. */
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#undef ARM_VARIANT
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#define ARM_VARIANT &arm_ext_v7
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@ -15319,9 +15337,6 @@ static const struct asm_opcode insns[] =
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#define THUMB_VARIANT &arm_ext_v7
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TUF(pli, 450f000, f910f000, 1, (ADDR), pli, t_pld),
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TCE(dbg, 320f0f0, f3af80f0, 1, (I15), dbg, t_dbg),
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TUF(dmb, 57ff050, f3bf8f50, 1, (oBARRIER), barrier, t_barrier),
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TUF(dsb, 57ff040, f3bf8f40, 1, (oBARRIER), barrier, t_barrier),
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TUF(isb, 57ff060, f3bf8f60, 1, (oBARRIER), barrier, t_barrier),
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#undef ARM_VARIANT
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#define ARM_VARIANT &fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
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@ -20099,6 +20114,7 @@ static const struct arm_cpu_option_table arm_cpus[] =
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NULL},
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{"cortex-r4", ARM_ARCH_V7R, FPU_NONE, NULL},
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{"cortex-m3", ARM_ARCH_V7M, FPU_NONE, NULL},
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{"cortex-m1", ARM_ARCH_V6M, FPU_NONE, NULL},
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/* ??? XSCALE is really an architecture. */
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{"xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL},
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/* ??? iwmmxt is not a processor. */
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@ -20147,6 +20163,7 @@ static const struct arm_arch_option_table arm_archs[] =
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{"armv6kt2", ARM_ARCH_V6KT2, FPU_ARCH_VFP},
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{"armv6zt2", ARM_ARCH_V6ZT2, FPU_ARCH_VFP},
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{"armv6zkt2", ARM_ARCH_V6ZKT2, FPU_ARCH_VFP},
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{"armv6-m", ARM_ARCH_V6M, FPU_ARCH_VFP},
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{"armv7", ARM_ARCH_V7, FPU_ARCH_VFP},
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/* The official spelling of the ARMv7 profile variants is the dashed form.
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Accept the non-dashed form for compatibility with old toolchains. */
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@ -20584,8 +20601,9 @@ static const cpu_arch_ver_table cpu_arch_ver[] =
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{5, ARM_ARCH_V5TEJ},
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{6, ARM_ARCH_V6},
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{7, ARM_ARCH_V6Z},
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{8, ARM_ARCH_V6K},
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{9, ARM_ARCH_V6T2},
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{9, ARM_ARCH_V6K},
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{9, ARM_ARCH_V6M},
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{8, ARM_ARCH_V6T2},
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{10, ARM_ARCH_V7A},
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{10, ARM_ARCH_V7R},
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{10, ARM_ARCH_V7M},
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@ -20647,7 +20665,7 @@ aeabi_set_public_attributes (void)
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bfd_elf_add_proc_attr_int (stdoutput, 7, 'A');
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else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
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bfd_elf_add_proc_attr_int (stdoutput, 7, 'R');
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else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m))
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else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
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bfd_elf_add_proc_attr_int (stdoutput, 7, 'M');
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/* Tag_ARM_ISA_use. */
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if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_full))
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@ -1,3 +1,10 @@
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2008-03-04 Paul Brook <paul@codesourcery.com>
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* gas/arm/archv6m.d: New test.
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* gas/arm/archv6m.s: New test.
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* gas/arm/t16-bad.s: Test low register non flag setting add.
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* gas/arm/t16-bad.l: Update expected output.
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2008-03-03 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/5543
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15
gas/testsuite/gas/arm/archv6m.d
Normal file
15
gas/testsuite/gas/arm/archv6m.d
Normal file
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@ -0,0 +1,15 @@
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# name: ARMv6-M
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# objdump: -dr --prefix-addresses --show-raw-insn
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.*: +file format .*arm.*
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Disassembly of section .text:
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0[0-9a-f]+ <[^>]+> f386 8800 msr (APSR|CPSR_f), r6
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0[0-9a-f]+ <[^>]+> f389 8806 msr EPSR, r9
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0[0-9a-f]+ <[^>]+> f3ef 8201 mrs r2, IAPSR
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0[0-9a-f]+ <[^>]+> bf10 yield
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0[0-9a-f]+ <[^>]+> bf20 wfe
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0[0-9a-f]+ <[^>]+> bf30 wfi
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0[0-9a-f]+ <[^>]+> bf40 sev
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0[0-9a-f]+ <[^>]+> 4408 add r0, r1
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0[0-9a-f]+ <[^>]+> bf00 nop
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16
gas/testsuite/gas/arm/archv6m.s
Normal file
16
gas/testsuite/gas/arm/archv6m.s
Normal file
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@ -0,0 +1,16 @@
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.arch armv6-m
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.syntax unified
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.thumb
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.text
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.align 2
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.global foo
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foo:
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msr apsr,r6
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msr epsr,r9
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mrs r2, iapsr
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yield
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wfe
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wfi
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sev
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add r0, r0, r1
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nop
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@ -184,3 +184,4 @@
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[^:]*:134: Error: Thumb does not support the 2-argument form of this instruction -- `cpsie ai,#5'
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[^:]*:135: Error: Thumb does not support the 2-argument form of this instruction -- `cpsid ai,#5'
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[^:]*:138: Error: Thumb does not support conditional execution
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[^:]*:141: Error: cannot honor width suffix -- `add r0,r1'
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@ -136,3 +136,7 @@ l:
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@ Conditional suffixes
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addeq r0,r1,r2
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@ low register non flag setting add.
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.syntax unified
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add r0, r1
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@ -1,3 +1,9 @@
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2008-03-04 Paul Brook <paul@codesourcery.com>
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* arm.h (ARM_EXT_V6M, ARM_EXT_BARRIER, ARM_EXT_THUMB_MSR): Define.
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(ARM_AEXT_V6T2, ARM_AEXT_V7_ARM, ARM_AEXT_V7M): Use new flags.
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(ARM_AEXT_V6M, ARM_ARCH_V6M): Define.
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2008-02-27 Denis Vlasenko <vda.linux@googlemail.com>
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Nick Clifton <nickc@redhat.com>
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@ -44,6 +44,9 @@
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#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
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#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
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#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
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#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
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#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
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#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
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/* Co-processor space extensions. */
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#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
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@ -87,17 +90,22 @@
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#define ARM_AEXT_V6K (ARM_AEXT_V6 | ARM_EXT_V6K)
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#define ARM_AEXT_V6Z (ARM_AEXT_V6 | ARM_EXT_V6Z)
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#define ARM_AEXT_V6ZK (ARM_AEXT_V6 | ARM_EXT_V6K | ARM_EXT_V6Z)
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#define ARM_AEXT_V6T2 (ARM_AEXT_V6 | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM)
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#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
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| ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR)
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#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K)
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#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 | ARM_EXT_V6Z)
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#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_V6Z)
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#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7)
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#define ARM_AEXT_V7_ARM (ARM_AEXT_V6ZKT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
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#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM | ARM_EXT_V7A)
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#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
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#define ARM_AEXT_NOTM \
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(ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM)
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#define ARM_AEXT_V6M \
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((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \
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& ~(ARM_AEXT_NOTM))
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#define ARM_AEXT_V7M \
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((ARM_AEXT_V7_ARM | ARM_EXT_V7M | ARM_EXT_DIV) & ~(ARM_AEXT_NOTM))
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((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
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& ~(ARM_AEXT_NOTM))
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#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
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/* Processors with specific extensions in the co-processor space. */
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@ -158,6 +166,7 @@
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#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
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#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
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#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
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#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
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#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
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#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
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#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
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||||
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|||
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Reference in a new issue