2002-06-03 Chris Demetriou <cgd@broadcom.com>
Ed Satterthwaite <ehs@broadcom.com> * configure.in (mipsisa64sb1*-*-*): New target for supporting Broadcom SiByte SB-1 processor configurations. * configure: Regenerate. * sb1.igen: New file. * mips.igen: Include sb1.igen. (sb1): New model. * Makefile.in (IGEN_INCLUDE): Add sb1.igen. * mdmx.igen: Add "sb1" model to all appropriate functions and instructions. * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. (ob_func, ob_acc): Reference the above. (qh_acc): Adjust to keep the same size as ob_acc. * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
This commit is contained in:
Chris Demetriou
parent
cf6fb9ce2f
commit
7cbea0890e
9 changed files with 316 additions and 19 deletions
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@ -1,3 +1,21 @@
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2002-06-03 Chris Demetriou <cgd@broadcom.com>
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Ed Satterthwaite <ehs@broadcom.com>
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* configure.in (mipsisa64sb1*-*-*): New target for supporting
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Broadcom SiByte SB-1 processor configurations.
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* configure: Regenerate.
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* sb1.igen: New file.
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* mips.igen: Include sb1.igen.
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(sb1): New model.
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* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
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* mdmx.igen: Add "sb1" model to all appropriate functions and
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instructions.
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* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
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(ob_func, ob_acc): Reference the above.
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(qh_acc): Adjust to keep the same size as ob_acc.
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* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
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(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
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2002-06-03 Chris Demetriou <cgd@broadcom.com>
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* Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
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@ -84,6 +84,7 @@ M16_DC=$(srcdir)/m16.dc
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IGEN_INCLUDE=\
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$(srcdir)/m16.igen \
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$(srcdir)/mdmx.igen \
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$(srcdir)/sb1.igen \
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$(srcdir)/tx.igen \
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$(srcdir)/vr.igen \
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32
sim/mips/configure
vendored
32
sim/mips/configure
vendored
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@ -4023,6 +4023,10 @@ case "${target}" in
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sim_igen_machine="-M mips32"
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sim_igen_filter="32,f"
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;;
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mipsisa64sb1*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64,sb1"
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sim_igen_filter="32,64,f"
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;;
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mipsisa64*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64"
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sim_igen_filter="32,64,f"
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@ -4132,7 +4136,7 @@ esac
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# Uses ac_ vars as temps to allow command line to override cache and checks.
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# --without-x overrides everything else, but does not touch the cache.
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echo $ac_n "checking for X""... $ac_c" 1>&6
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echo "configure:4136: checking for X" >&5
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echo "configure:4140: checking for X" >&5
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# Check whether --with-x or --without-x was given.
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if test "${with_x+set}" = set; then
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@ -4194,12 +4198,12 @@ if test "$ac_x_includes" = NO; then
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# First, try using that file with no special directory specified.
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cat > conftest.$ac_ext <<EOF
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#line 4198 "configure"
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#line 4202 "configure"
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#include "confdefs.h"
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#include <$x_direct_test_include>
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:4203: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:4207: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
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if test -z "$ac_err"; then
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rm -rf conftest*
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@ -4268,14 +4272,14 @@ if test "$ac_x_libraries" = NO; then
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ac_save_LIBS="$LIBS"
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LIBS="-l$x_direct_test_library $LIBS"
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cat > conftest.$ac_ext <<EOF
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#line 4272 "configure"
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#line 4276 "configure"
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#include "confdefs.h"
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int main() {
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${x_direct_test_function}()
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; return 0; }
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EOF
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if { (eval echo configure:4279: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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if { (eval echo configure:4283: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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rm -rf conftest*
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LIBS="$ac_save_LIBS"
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# We can link X programs with no special library path.
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@ -4368,17 +4372,17 @@ for ac_hdr in string.h strings.h stdlib.h stdlib.h
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do
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ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'`
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echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6
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echo "configure:4372: checking for $ac_hdr" >&5
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echo "configure:4376: checking for $ac_hdr" >&5
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if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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cat > conftest.$ac_ext <<EOF
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#line 4377 "configure"
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#line 4381 "configure"
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#include "confdefs.h"
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#include <$ac_hdr>
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EOF
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ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out"
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{ (eval echo configure:4382: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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{ (eval echo configure:4386: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }
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ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"`
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if test -z "$ac_err"; then
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rm -rf conftest*
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@ -4405,7 +4409,7 @@ fi
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done
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echo $ac_n "checking for fabs in -lm""... $ac_c" 1>&6
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echo "configure:4409: checking for fabs in -lm" >&5
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echo "configure:4413: checking for fabs in -lm" >&5
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ac_lib_var=`echo m'_'fabs | sed 'y%./+-%__p_%'`
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if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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@ -4413,7 +4417,7 @@ else
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ac_save_LIBS="$LIBS"
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LIBS="-lm $LIBS"
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cat > conftest.$ac_ext <<EOF
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#line 4417 "configure"
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#line 4421 "configure"
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#include "confdefs.h"
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/* Override any gcc2 internal prototype to avoid an error. */
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/* We use char because int might match the return type of a gcc2
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@ -4424,7 +4428,7 @@ int main() {
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fabs()
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; return 0; }
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EOF
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if { (eval echo configure:4428: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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if { (eval echo configure:4432: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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rm -rf conftest*
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eval "ac_cv_lib_$ac_lib_var=yes"
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else
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@ -4454,12 +4458,12 @@ fi
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for ac_func in aint anint sqrt
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do
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echo $ac_n "checking for $ac_func""... $ac_c" 1>&6
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echo "configure:4458: checking for $ac_func" >&5
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echo "configure:4462: checking for $ac_func" >&5
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if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then
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echo $ac_n "(cached) $ac_c" 1>&6
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else
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cat > conftest.$ac_ext <<EOF
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#line 4463 "configure"
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#line 4467 "configure"
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#include "confdefs.h"
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/* System header to define __stub macros and hopefully few prototypes,
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which can conflict with char $ac_func(); below. */
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@ -4482,7 +4486,7 @@ $ac_func();
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; return 0; }
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EOF
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if { (eval echo configure:4486: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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if { (eval echo configure:4490: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then
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rm -rf conftest*
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eval "ac_cv_func_$ac_func=yes"
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else
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@ -128,6 +128,10 @@ case "${target}" in
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sim_igen_machine="-M mips32"
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sim_igen_filter="32,f"
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;;
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mipsisa64sb1*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64,sb1"
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sim_igen_filter="32,64,f"
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;;
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mipsisa64*-*-*) sim_gen=IGEN
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sim_igen_machine="-M mips64"
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sim_igen_filter="32,64,f"
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@ -250,7 +250,6 @@ MsgnQH(signed16 ts, signed16 tt)
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return t;
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}
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static signed16
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SRAQH(signed16 ts, signed16 tt)
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{
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@ -259,6 +258,21 @@ SRAQH(signed16 ts, signed16 tt)
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}
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/* "pabsdiff" and "pavg" are defined only for OB format. */
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static unsigned8
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AbsDiffOB(unsigned8 ts, unsigned8 tt)
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{
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return (ts >= tt ? ts - tt : tt - ts);
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}
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static unsigned8
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AvgOB(unsigned8 ts, unsigned8 tt)
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{
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return ((unsigned32)ts + (unsigned32)tt + 1) >> 1;
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}
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/* Dispatch tables for operations that update a CPR. */
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static const QH_FUNC qh_func[] = {
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@ -270,7 +284,7 @@ static const QH_FUNC qh_func[] = {
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static const OB_FUNC ob_func[] = {
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AndOB, NorOB, OrOB, XorOB, SLLOB, SRLOB,
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AddOB, SubOB, MinOB, MaxOB,
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MulOB, NULL, NULL, NULL, NULL
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MulOB, NULL, NULL, AbsDiffOB, AvgOB
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};
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/* Auxiliary functions for CPR updates. */
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@ -743,17 +757,26 @@ AccSubLOB(signed24 *a, unsigned8 ts, unsigned8 tt)
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*a = (signed24)ts - (signed24)tt;
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}
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static void
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AccAbsDiffOB(signed24 *a, unsigned8 ts, unsigned8 tt)
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{
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unsigned8 t = (ts >= tt ? ts - tt : tt - ts);
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*a += (signed24)t;
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}
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/* Dispatch tables for operations that update a CPR. */
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static const QH_ACC qh_acc[] = {
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AccAddAQH, AccAddAQH, AccMulAQH, AccMulLQH,
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SubMulAQH, SubMulLQH, AccSubAQH, AccSubLQH
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SubMulAQH, SubMulLQH, AccSubAQH, AccSubLQH,
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NULL
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};
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static const OB_ACC ob_acc[] = {
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AccAddAOB, AccAddLOB, AccMulAOB, AccMulLOB,
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SubMulAOB, SubMulLOB, AccSubAOB, AccSubLOB
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SubMulAOB, SubMulLOB, AccSubAOB, AccSubLOB,
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AccAbsDiffOB
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};
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@ -32,6 +32,10 @@
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// Similarly, for the single-bit fields which differentiate between
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// formats (FMTOP), 0 is OB format and 1 is QH format.
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// If you change this file to add instructions, please make sure that model
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// "sb1" configurations still build, and that you've added no new
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// instructions to the "sb1" model.
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// Helper:
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//
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@ -93,6 +97,7 @@
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:%s::::FMTSEL:int fmtsel
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*mdmx:
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*sb1:
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{
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if ((fmtsel & 0x1) == 0)
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return "ob";
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@ -105,6 +110,7 @@
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:%s::::FMTOP:int fmtop
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*mdmx:
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*sb1:
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{
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switch (fmtop)
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{
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@ -117,6 +123,7 @@
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:%s::::SHOP:int shop
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*mdmx:
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*sb1:
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{
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if ((shop & 0x11) == 0x00)
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switch ((shop >> 1) & 0x07)
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@ -146,6 +153,7 @@
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001011:MDMX:64::ADD.fmt
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"add.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -156,6 +164,7 @@
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110111:MDMX:64::ADDA.fmt
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"adda.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -166,6 +175,7 @@
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011110,5.FMTSEL,5.VT,5.VS,1,0000,110111:MDMX:64::ADDL.fmt
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"addl.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -176,6 +186,7 @@
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011110,00,3.IMM,5.VT,5.VS,5.VD,0110,1.FMTOP,0:MDMX:64::ALNI.fmt
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"alni.%s<FMTOP> v<VD>, v<VS>, v<VT>, <IMM>"
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*mdmx:
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*sb1:
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{
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unsigned64 result;
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int s;
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@ -192,6 +203,7 @@
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011110,5.RS,5.VT,5.VS,5.VD,0110,1.FMTOP,1:MDMX:64::ALNV.fmt
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"alnv.%s<FMTOP> v<VD>, v<VS>, v<VT>, r<RS>"
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*mdmx:
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*sb1:
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{
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unsigned64 result;
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int s;
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@ -208,6 +220,7 @@
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011110,5.FMTSEL,5.VT,5.VS,5.VD,001100:MDMX:64::AND.fmt
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"and.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -218,6 +231,7 @@
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011110,5.FMTSEL,5.VT,5.VS,00000,000001:MDMX:64::C.EQ.fmt
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"c.eq.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -228,6 +242,7 @@
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011110,5.FMTSEL,5.VT,5.VS,00000,000101:MDMX:64::C.LE.fmt
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"c.le.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -238,6 +253,7 @@
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011110,5.FMTSEL,5.VT,5.VS,00000,000100:MDMX:64::C.LT.fmt
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"c.lt.%s<FMTSEL> v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -248,6 +264,7 @@
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000111:MDMX:64::MAX.fmt
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"max.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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||||
*mdmx:
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||||
*sb1:
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||||
{
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||||
check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -258,6 +275,7 @@
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011110,5.FMTSEL,5.VT,5.VS,5.VD,000110:MDMX:64::MIN.fmt
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"min.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
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@ -277,6 +295,7 @@
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011110,5.FMTSEL,5.VT,5.VS,5.VD,110000:MDMX:64::MUL.fmt
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"mul.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
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*mdmx:
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*sb1:
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{
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check_mdmx (SD_, instruction_0);
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if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
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|
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@ -287,6 +306,7 @@
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011110,5.FMTSEL,5.VT,5.VS,0,0000,110011:MDMX:64::MULA.fmt
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"mula.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
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||||
*sb1:
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{
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check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -297,6 +317,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,1,0000,110011:MDMX:64::MULL.fmt
|
||||
"mull.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -307,6 +328,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,0,0000,110010:MDMX:64::MULS.fmt
|
||||
"muls.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -317,6 +339,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,1,0000,110010:MDMX:64::MULSL.fmt
|
||||
"mulsl.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -327,6 +350,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001111:MDMX:64::NOR.fmt
|
||||
"nor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -337,6 +361,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001110:MDMX:64::OR.fmt
|
||||
"or.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -347,6 +372,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,000010:MDMX:64::PICKF.fmt
|
||||
"pickf.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -357,6 +383,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,000011:MDMX:64::PICKT.fmt
|
||||
"pickt.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -367,6 +394,7 @@
|
|||
011110,1000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.fmt
|
||||
"rach.%s<FMTOP> v<VD>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
|
|
@ -377,6 +405,7 @@
|
|||
011110,0000,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.fmt
|
||||
"racl.%s<FMTOP> v<VD>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
|
|
@ -387,6 +416,7 @@
|
|||
011110,0100,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.fmt
|
||||
"racm.%s<FMTOP> v<VD>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
|
|
@ -406,6 +436,7 @@
|
|||
011110,5.FMTSEL,5.VT,00000,5.VD,100001:MDMX:64::RNAU.fmt
|
||||
"rnau.%s<FMTSEL> v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -425,6 +456,7 @@
|
|||
011110,5.FMTSEL,5.VT,00000,5.VD,100010:MDMX:64::RNEU.fmt
|
||||
"rneu.%s<FMTSEL> v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -444,6 +476,7 @@
|
|||
011110,5.FMTSEL,5.VT,00000,5.VD,100000:MDMX:64::RZU.fmt
|
||||
"rzu.%s<FMTSEL> v<VD>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -454,6 +487,7 @@
|
|||
011110,5.SHOP,5.VT,5.VS,5.VD,011111:MDMX:64::SHFL.op.fmt
|
||||
"shfl.%s<SHOP> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, SHOP))
|
||||
|
|
@ -464,6 +498,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,010000:MDMX:64::SLL.fmt
|
||||
"sll.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -483,6 +518,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,010010:MDMX:64::SRL.fmt
|
||||
"srl.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -493,6 +529,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001010:MDMX:64::SUB.fmt
|
||||
"sub.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -503,6 +540,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,0,0000,110110:MDMX:64::SUBA.fmt
|
||||
"suba.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -513,6 +551,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,1,0000,110110:MDMX:64::SUBL.fmt
|
||||
"subl.%s<FMTSEL> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
@ -523,6 +562,7 @@
|
|||
011110,1000,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.fmt
|
||||
"wach.%s<FMTOP> v<VS>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
|
|
@ -533,6 +573,7 @@
|
|||
011110,0000,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.fmt
|
||||
"wacl.%s<FMTOP> v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
|
|
@ -543,6 +584,7 @@
|
|||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001101:MDMX:64::XOR.fmt
|
||||
"xor.%s<FMTSEL> v<VD>, v<VS>, v<VT>"
|
||||
*mdmx:
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (check_mdmx_fmtsel (SD_, instruction_0, FMTSEL))
|
||||
|
|
|
|||
|
|
@ -65,6 +65,12 @@
|
|||
:model:::mips16:mips16: // m16.igen (and m16.dc)
|
||||
:model:::mdmx:mdmx: // mdmx.igen
|
||||
|
||||
// Vendor Extensions
|
||||
//
|
||||
// Instructions specific to these extensions are in separate .igen files.
|
||||
// Extensions add instructions on to a base ISA.
|
||||
:model:::sb1:sb1: // sb1.igen
|
||||
|
||||
|
||||
// Pseudo instructions known by IGEN
|
||||
:internal::::illegal:
|
||||
|
|
@ -5057,6 +5063,7 @@
|
|||
|
||||
:include:::m16.igen
|
||||
:include:::mdmx.igen
|
||||
:include:::sb1.igen
|
||||
:include:::tx.igen
|
||||
:include:::vr.igen
|
||||
|
||||
|
|
|
|||
191
sim/mips/sb1.igen
Normal file
191
sim/mips/sb1.igen
Normal file
|
|
@ -0,0 +1,191 @@
|
|||
// -*- C -*-
|
||||
|
||||
// Simulator definition for the Broadcom SiByte SB-1 CPU extensions.
|
||||
// Copyright (C) 2002 Free Software Foundation, Inc.
|
||||
// Contributed by Broadcom Corporation (SiByte).
|
||||
//
|
||||
// This file is part of GDB, the GNU debugger.
|
||||
//
|
||||
// This program is free software; you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation; either version 2, or (at your option)
|
||||
// any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License along
|
||||
// with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
// 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
|
||||
|
||||
|
||||
// MDMX ASE Instructions
|
||||
// ---------------------
|
||||
//
|
||||
// The SB-1 implements the format OB subset of MDMX
|
||||
// and has three additions (pavg, pabsdiff, pabsdifc).
|
||||
// In addition, there are a couple of partial-decoding
|
||||
// issues for the read/write accumulator instructions.
|
||||
//
|
||||
// This code is structured so that mdmx.igen can be used by
|
||||
// selecting the allowed instructions either via model, or by
|
||||
// using check_mdmx_fmtsel and check_mdmx_fmtop to cause an
|
||||
// exception if the instruction is not allowed.
|
||||
|
||||
|
||||
:function:::void:check_mdmx:instruction_word insn
|
||||
*sb1:
|
||||
{
|
||||
if (!COP_Usable(1))
|
||||
SignalExceptionCoProcessorUnusable(1);
|
||||
if ((SR & status_MX) == 0)
|
||||
SignalExceptionMDMX();
|
||||
check_u64 (SD_, insn);
|
||||
}
|
||||
|
||||
:function:::int:check_mdmx_fmtsel:instruction_word insn, int fmtsel
|
||||
*sb1:
|
||||
{
|
||||
switch (fmtsel & 0x03)
|
||||
{
|
||||
case 0x00: /* ob */
|
||||
case 0x02:
|
||||
return 1;
|
||||
case 0x01: /* qh */
|
||||
case 0x03: /* UNPREDICTABLE */
|
||||
SignalException (ReservedInstruction, insn);
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
:function:::int:check_mdmx_fmtop:instruction_word insn, int fmtop
|
||||
*sb1:
|
||||
{
|
||||
switch (fmtop & 0x01)
|
||||
{
|
||||
case 0x00: /* ob */
|
||||
return 1;
|
||||
case 0x01: /* qh */
|
||||
SignalException (ReservedInstruction, insn);
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
011110,10,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACH.sb1.fmt
|
||||
"rach.?<X>.%s<FMTOP> v<VD>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,00,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACL.sb1.fmt
|
||||
"racl.?<X>.%s<FMTOP> v<VD>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,01,2.X!0,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RACM.sb1.fmt
|
||||
"racm.?<X>.%s<FMTOP> v<VD>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,2.X1!0!1!2,2.X2,1.FMTOP,00000,00000,5.VD,111111:MDMX:64::RAC.sb1.fmt
|
||||
"rac?<X1>.?<X2> v<VD>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,10,2.X!0,1.FMTOP,00000,5.VS,00000,111110:MDMX:64::WACH.sb1.fmt
|
||||
"wach.?<X>.%s<FMTOP> v<VS>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,00,2.X!0,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WACL.sb1.fmt
|
||||
"wacl.?<X>.%s<FMTOP> v<VS>,v<VT>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,2.X1!0!2,2.X2,1.FMTOP,5.VT,5.VS,00000,111110:MDMX:64::WAC.sb1.fmt
|
||||
"wacl?<X1>.?<X2>.%s<FMTOP> v<VS>,v<VT>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
check_mdmx_fmtop (SD_, instruction_0, FMTOP);
|
||||
/* No op. */
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001001:MDMX:64::PABSDIFF.fmt
|
||||
"pabsdiff.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (SR & status_SBX)
|
||||
{
|
||||
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
|
||||
StoreFPR(VD,fmt_mdmx,MX_AbsDiff(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
else
|
||||
SignalException(ReservedInstruction, instruction_0);
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,00000,110101:MDMX:64::PABSDIFC.fmt
|
||||
"pabsdifc.%<FMTSEL> v<VS>,v<VT>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (SR & status_SBX)
|
||||
{
|
||||
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
|
||||
MX_AbsDiffC(ValueFPR(VS,fmt_mdmx),VT,FMTSEL);
|
||||
}
|
||||
else
|
||||
SignalException(ReservedInstruction, instruction_0);
|
||||
}
|
||||
|
||||
|
||||
011110,5.FMTSEL,5.VT,5.VS,5.VD,001000:MDMX:64::PAVG.fmt
|
||||
"pavg.%s<FMTSEL> v<VD>,v<VS>,v<VT>"
|
||||
*sb1:
|
||||
{
|
||||
check_mdmx (SD_, instruction_0);
|
||||
if (SR & status_SBX)
|
||||
{
|
||||
check_mdmx_fmtsel (SD_, instruction_0, FMTSEL);
|
||||
StoreFPR(VD,fmt_mdmx,MX_Avg(ValueFPR(VS,fmt_mdmx),VT,FMTSEL));
|
||||
}
|
||||
else
|
||||
SignalException(ReservedInstruction, instruction_0);
|
||||
}
|
||||
|
|
@ -567,6 +567,8 @@ struct sim_state {
|
|||
#define status_CU1 (1 << 29) /* Coprocessor 1 usable */
|
||||
#define status_CU2 (1 << 30) /* Coprocessor 2 usable */
|
||||
#define status_CU3 (1 << 31) /* Coprocessor 3 usable */
|
||||
/* Bits reserved for implementations: */
|
||||
#define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
|
||||
|
||||
#define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
|
||||
#define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
|
||||
|
|
@ -743,7 +745,6 @@ typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
|
|||
#define MX_VECT_XOR (3)
|
||||
#define MX_VECT_SLL (4)
|
||||
#define MX_VECT_SRL (5)
|
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#define MX_VECT_ADD (6)
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#define MX_VECT_SUB (7)
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#define MX_VECT_MIN (8)
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@ -751,6 +752,8 @@ typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
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#define MX_VECT_MUL (10)
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#define MX_VECT_MSGN (11)
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#define MX_VECT_SRA (12)
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#define MX_VECT_ABSD (13) /* SB-1 only. */
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#define MX_VECT_AVG (14) /* SB-1 only. */
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unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
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#define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
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@ -766,6 +769,8 @@ unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmt
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#define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
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#define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
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#define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
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#define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
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#define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
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#define MX_C_EQ 0x1
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#define MX_C_LT 0x4
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@ -784,6 +789,7 @@ unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fm
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#define MX_VECT_MULSL (5)
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#define MX_VECT_SUBA (6)
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#define MX_VECT_SUBL (7)
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#define MX_VECT_ABSDA (8) /* SB-1 only. */
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void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
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#define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
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@ -794,6 +800,7 @@ void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
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#define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
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#define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
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#define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
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#define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
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#define MX_FMT_OB (0)
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#define MX_FMT_QH (1)
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|
|
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Loading…
Add table
Reference in a new issue