gas/
2005-02-15 Jan Beulich <jbeulich@novell.com> * config/tc-ia64.c (md_apply_fix3): Call ia64_gen_real_reloc_type instead of explicitly dealing with the translation; exclude relocations that are already pcrel, however. gas/testsuite/ 2005-02-15 Jan Beulich <jbeulich@novell.com> * gas/ia64/pcrel.[ds]: New. * gas/ia64/ia64.exp: Run new test.
This commit is contained in:
Jan Beulich
parent
a66d2bb7bd
commit
7b347e436d
6 changed files with 179 additions and 21 deletions
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@ -1,3 +1,9 @@
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2005-02-15 Jan Beulich <jbeulich@novell.com>
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* config/tc-ia64.c (md_apply_fix3): Call ia64_gen_real_reloc_type
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instead of explicitly dealing with the translation; exclude
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relocations that are already pcrel, however.
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2005-02-15 Jan Beulich <jbeulich@novell.com>
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2005-02-15 Jan Beulich <jbeulich@novell.com>
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* config/tc-ia64.c: Include limits.h (if available).
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* config/tc-ia64.c: Include limits.h (if available).
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@ -11243,27 +11243,24 @@ md_apply_fix3 (fix, valP, seg)
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if (fix->fx_pcrel)
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if (fix->fx_pcrel)
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{
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{
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switch (fix->fx_r_type)
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switch (fix->fx_r_type)
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{
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{
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case BFD_RELOC_IA64_DIR32MSB:
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case BFD_RELOC_IA64_PCREL21B: break;
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fix->fx_r_type = BFD_RELOC_IA64_PCREL32MSB;
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case BFD_RELOC_IA64_PCREL21BI: break;
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break;
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case BFD_RELOC_IA64_PCREL21F: break;
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case BFD_RELOC_IA64_PCREL21M: break;
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case BFD_RELOC_IA64_DIR32LSB:
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case BFD_RELOC_IA64_PCREL60B: break;
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fix->fx_r_type = BFD_RELOC_IA64_PCREL32LSB;
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case BFD_RELOC_IA64_PCREL22: break;
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break;
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case BFD_RELOC_IA64_PCREL64I: break;
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case BFD_RELOC_IA64_PCREL32MSB: break;
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case BFD_RELOC_IA64_DIR64MSB:
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case BFD_RELOC_IA64_PCREL32LSB: break;
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fix->fx_r_type = BFD_RELOC_IA64_PCREL64MSB;
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case BFD_RELOC_IA64_PCREL64MSB: break;
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break;
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case BFD_RELOC_IA64_PCREL64LSB: break;
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default:
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case BFD_RELOC_IA64_DIR64LSB:
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fix->fx_r_type = ia64_gen_real_reloc_type (pseudo_func[FUNC_PC_RELATIVE].u.sym,
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fix->fx_r_type = BFD_RELOC_IA64_PCREL64LSB;
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fix->fx_r_type);
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break;
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break;
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}
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default:
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break;
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}
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}
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}
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if (fix->fx_addsy)
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if (fix->fx_addsy)
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{
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{
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@ -1,3 +1,8 @@
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2005-02-15 Jan Beulich <jbeulich@novell.com>
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* gas/ia64/pcrel.[ds]: New.
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* gas/ia64/ia64.exp: Run new test.
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2005-02-15 Jan Beulich <jbeulich@novell.com>
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2005-02-15 Jan Beulich <jbeulich@novell.com>
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* gas/ia64/dv-raw-err.l: Expect specific resource for RAW violation on b0.
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* gas/ia64/dv-raw-err.l: Expect specific resource for RAW violation on b0.
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@ -53,6 +53,7 @@ if [istarget "ia64-*"] then {
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run_dump_test "reloc"
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run_dump_test "reloc"
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run_list_test "reloc-bad" ""
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run_list_test "reloc-bad" ""
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run_dump_test "pcrel"
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run_dump_test "real"
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run_dump_test "real"
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run_dump_test "align"
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run_dump_test "align"
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62
gas/testsuite/gas/ia64/pcrel.d
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62
gas/testsuite/gas/ia64/pcrel.d
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@ -0,0 +1,62 @@
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#objdump: -rs
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#name: ia64 pcrel
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.*: +file format .*
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RELOCATION RECORDS FOR \[\.mov\]:
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OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
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0+10[[:space:]]+PCREL22[[:space:]]+esym
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0+20[[:space:]]+PCREL22[[:space:]]+esym\+0x0+20
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0+30[[:space:]]+PCREL22[[:space:]]+esym
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0+40[[:space:]]+PCREL22[[:space:]]+esym\+0xf+e0
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RELOCATION RECORDS FOR \[\.movl\]:
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OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
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0+12[[:space:]]+PCREL64I[[:space:]]+esym
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0+22[[:space:]]+PCREL64I[[:space:]]+esym\+0x0+20
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0+32[[:space:]]+PCREL64I[[:space:]]+esym
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0+42[[:space:]]+PCREL64I[[:space:]]+esym\+0xf+e0
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RELOCATION RECORDS FOR \[\.data8\]:
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OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
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0+10[[:space:]]+PCREL64[LM]SB[[:space:]]+esym
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0+20[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0x0+20
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0+30[[:space:]]+PCREL64[LM]SB[[:space:]]+esym
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0+40[[:space:]]+PCREL64[LM]SB[[:space:]]+esym\+0xf+e0
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RELOCATION RECORDS FOR \[\.data4\]:
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OFFSET[[:space:]]+TYPE[[:space:]]+VALUE[[:space:]]*
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0+10[[:space:]]+PCREL32[LM]SB[[:space:]]+esym
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0+20[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0x0+20
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0+30[[:space:]]+PCREL32[LM]SB[[:space:]]+esym
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0+40[[:space:]]+PCREL32[LM]SB[[:space:]]+esym\+0xf+e0
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Contents of section \.mov:
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0+00 1d108001 00240000 00020000 00000020 .*
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0+10 1d100000 00240000 00020000 00000020 .*
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0+20 1d100000 00240000 00020000 00000020 .*
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0+30 1d100000 00240000 00020000 00000020 .*
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0+40 1d100000 00240000 00020000 00000020 .*
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0+50 1d100000 00240000 00020000 00000020 .*
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Contents of section \.movl:
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0+00 05000000 01000000 00000040 00060060 .*
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0+10 05000000 01000000 00000040 00000060 .*
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0+20 05000000 01000000 00000040 00000060 .*
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0+30 05000000 01000000 00000040 00000060 .*
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0+40 05000000 01000000 00000040 00000060 .*
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0+50 05000000 01000000 00000040 00000060 .*
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Contents of section \.data8:
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0+00 60000000 00000000 00000000 00000000 .*
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0+10 00000000 00000000 00000000 00000000 .*
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0+20 00000000 00000000 00000000 00000000 .*
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0+30 00000000 00000000 00000000 00000000 .*
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0+40 00000000 00000000 00000000 00000000 .*
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0+50 00000000 00000000 00000000 00000000 .*
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Contents of section \.data4:
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0+00 60000000 00000000 00000000 00000000 .*
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0+10 00000000 00000000 00000000 00000000 .*
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0+20 00000000 00000000 00000000 00000000 .*
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0+30 00000000 00000000 00000000 00000000 .*
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0+40 00000000 00000000 00000000 00000000 .*
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0+50 00000000 00000000 00000000 00000000 .*
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87
gas/testsuite/gas/ia64/pcrel.s
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87
gas/testsuite/gas/ia64/pcrel.s
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@ -0,0 +1,87 @@
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.explicit
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.global esym
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.altmacro
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.macro begin n, attr
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.section .&n, attr, @progbits
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.align 16
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_&n:
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.endm
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.macro end n
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.align 16
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_e&n:
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.endm
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.macro m1 op, opnd1
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.align 16
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op opnd1 _e&op - _&op
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.endm
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.macro m2 op, opnd1
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.align 16
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op opnd1 @pcrel(esym)
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.endm
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.macro m3 op, opnd1
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.align 16
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op opnd1 esym - _&op
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.endm
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.macro m4 op, opnd1
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.align 16
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op opnd1 esym - .
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.endm
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.macro m5 op, opnd1
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.align 16
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op opnd1 esym - _e&op
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.endm
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.macro m6 op, opnd1
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.align 16
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op opnd1 0
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.endm
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begin mov, "ax"
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m1 mov, r2 =
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;;
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m2 mov, r2 =
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;;
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m3 mov, r2 =
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;;
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m4 mov, r2 =
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;;
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m5 mov, r2 =
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;;
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m6 mov, r2 =
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;;
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end mov
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begin movl, "ax"
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m1 movl, r2 =
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;;
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m2 movl, r2 =
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;;
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m3 movl, r2 =
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;;
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m4 movl, r2 =
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;;
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m5 movl, r2 =
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;;
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m6 movl, r2 =
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;;
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end movl
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begin data8, "a"
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m1 data8
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m2 data8
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m3 data8
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m4 data8
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m5 data8
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m6 data8
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end data8
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begin data4, "a"
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m1 data4
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m2 data4
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m3 data4
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m4 data4
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m5 data4
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m6 data4
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end data4
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