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[BINUTILS, AARCH64, 1/8] Add support for Memory Tagging Extension for ARMv8.5-A

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This patch is part of the patch series to add support for ARMv8.5-A
Memory Tagging Extensions. Memory Tagging Extension is an optional extension to
ARMv8.5-A and is enabled using the +memtag command line option.
This patch adds the new command line option and the new feature macros.

*** include/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.

*** opcodes/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-tbl.h (aarch64_feature_memtag): New.
	(MEMTAG, MEMTAG_INSN): New.

*** gas/ChangeLog ***

2018-11-12  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (aarch64_features): Add "memtag"
	as a new option.
	* doc/c-aarch64.texi: Document the same.
This commit is contained in:
Sudakshina Das 2018-11-12 12:45:30 +00:00
parent d1b603a74e
commit 73b605ec3f
7 changed files with 26 additions and 0 deletions
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6
gas/ChangeLog
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@ -1,3 +1,9 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): Add "memtag"
as a new option.
* doc/c-aarch64.texi: Document the same.
2018-11-09 Alan Modra <amodra@gmail.com>
* config/tc-ppc.c (fixup_size): New function.

2
gas/config/tc-aarch64.c
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@ -8829,6 +8829,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
AARCH64_ARCH_NONE},
{"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
AARCH64_ARCH_NONE},
{"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0),
AARCH64_ARCH_NONE},
{NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
};

2
gas/doc/c-aarch64.texi
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@ -189,6 +189,8 @@ automatically cause those extensions to be disabled.
@tab Enable ARMv8.5-A random number instructions.
@item @code{ssbs} @tab ARMv8-A @tab ARMv8.5-A or later
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{memtag} @tab ARMv8.5-A @tab No
@tab Enable ARMv8.5-A Memory Tagging Extensions.
@end multitable
@node AArch64 Syntax

4
include/ChangeLog
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@ -1,3 +1,7 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_MEMTAG): New.
2018-11-07 Roman Bolshakov <r.bolshakov@yadro.com>
Saagar Jha <saagar@saagarjha.com>

2
include/opcode/aarch64.h
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@ -84,6 +84,8 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_ID_PFR2 0x400000000000ULL
/* SSBS mechanism enabled. */
#define AARCH64_FEATURE_SSBS 0x800000000000ULL
/* Memory Tagging Extension. */
#define AARCH64_FEATURE_MEMTAG 0x1000000000000ULL
/* Architectures are the sum of the base and extensions. */

5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2018-11-12 Sudakshina Das <sudi.das@arm.com>
* aarch64-tbl.h (aarch64_feature_memtag): New.
(MEMTAG, MEMTAG_INSN): New.
2018-11-06 Sudakshina Das <sudi.das@arm.com>
* arm-dis.c (select_arm_features): Update bfd_mach_arm_8

5
opcodes/aarch64-tbl.h
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@ -2171,6 +2171,8 @@ static const aarch64_feature_set aarch64_feature_predres =
AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
static const aarch64_feature_set aarch64_feature_bti =
AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
static const aarch64_feature_set aarch64_feature_memtag =
AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
#define CORE &aarch64_feature_v8
@ -2205,6 +2207,7 @@ static const aarch64_feature_set aarch64_feature_bti =
#define SB &aarch64_feature_sb
#define PREDRES &aarch64_feature_predres
#define BTI &aarch64_feature_bti
#define MEMTAG &aarch64_feature_memtag
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -2268,6 +2271,8 @@ static const aarch64_feature_set aarch64_feature_bti =
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
#define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] =
{