opcodes/
* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB macros before their corresponding MIPS III hardware instructions. gas/ * config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs. gas/testsuite/ * gas/mips/lineno.s: Convert to o32. * gas/mips/lineno.d: Adjust patterns accordingly. Force the o32 ABI.
This commit is contained in:
Maciej W. Rozycki
parent
998b3c3643
commit
704897fbef
7 changed files with 47 additions and 27 deletions
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@ -1,3 +1,7 @@
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2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
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* config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs.
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2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
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* config/tc-mips.c (mips_pseudo_table): Add "sbss".
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@ -7367,15 +7367,18 @@ macro (struct mips_cl_insn *ip)
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break;
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case M_LD_OB:
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s = "lw";
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s = HAVE_64BIT_GPRS ? "ld" : "lw";
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goto sd_ob;
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case M_SD_OB:
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s = "sw";
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s = HAVE_64BIT_GPRS ? "sd" : "sw";
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sd_ob:
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gas_assert (HAVE_32BIT_ADDRESSES);
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macro_build (&offset_expr, s, "t,o(b)", treg, BFD_RELOC_LO16, breg);
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offset_expr.X_add_number += 4;
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macro_build (&offset_expr, s, "t,o(b)", treg + 1, BFD_RELOC_LO16, breg);
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if (!HAVE_64BIT_GPRS)
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{
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offset_expr.X_add_number += 4;
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macro_build (&offset_expr, s, "t,o(b)", treg + 1,
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BFD_RELOC_LO16, breg);
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}
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break;
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/* New code added to support COPZ instructions.
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@ -1,3 +1,9 @@
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2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
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* gas/mips/lineno.s: Convert to o32.
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* gas/mips/lineno.d: Adjust patterns accordingly. Force the o32
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ABI.
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2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/i386.exp: Run x86-64-nops-1-g64.
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@ -1,6 +1,6 @@
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#objdump: -d -l -mmips:4000
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#name: assembly line numbers
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#as: --gstabs -march=r4000
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#as: --gstabs -32 -march=r4000
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.*: +file format .*mips.*
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@ -17,9 +17,9 @@ main\(\):
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.*lineno.s:16
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.*10:.*addiu.*
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.*lineno.s:17
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.*14:.*sd.*
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.*14:.*sw.*
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.*lineno.s:18
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.*18:.*sd.*
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.*18:.*sw.*
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.*lineno.s:19
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.*1c:.*move.*
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.*lineno.s:20
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@ -59,9 +59,9 @@ main\(\):
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.*lineno.s:34
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.*60:.*move.*
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.*lineno.s:35
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.*64:.*ld.*
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.*64:.*lw.*
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.*lineno.s:36
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.*68:.*ld.*
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.*68:.*lw.*
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.*lineno.s:37
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.*6c:.*addiu.*
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.*lineno.s:38
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@ -73,7 +73,7 @@ g\(\):
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.*lineno.s:47
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.*78:.*addiu.*
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.*lineno.s:48
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.*7c:.*sd.*
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.*7c:.*sw.*
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.*lineno.s:49
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.*80:.*move.*
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.*lineno.s:50
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@ -92,7 +92,7 @@ g\(\):
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.*lineno.s:56
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.*9c:.*move.*
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.*lineno.s:57
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.*a0:.*ld.*
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.*a0:.*lw.*
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.*lineno.s:58
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.*a4:.*addiu.*
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.*lineno.s:59
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@ -7,15 +7,15 @@
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.word 0xdeadbeef
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# some real code, compiled from a toy C program
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.globl main
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.globl main
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.ent main
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main:
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.frame $fp,32,$31 # vars= 16, regs= 2/0, args= 0, extra= 0
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.frame $fp,24,$31 # vars= 16, regs= 2/0, args= 0, extra= 0
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.mask 0xc0000000,-8
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.fmask 0x00000000,0
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subu $sp,$sp,32
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sd $31,24($sp)
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sd $fp,16($sp)
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subu $sp,$sp,24
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sw $31,20($sp)
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sw $fp,16($sp)
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move $fp,$sp
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jal __main
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li $2,2 # 0x2
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@ -32,20 +32,20 @@ main:
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b $L1
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$L1:
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move $sp,$fp
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ld $31,24($sp)
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ld $fp,16($sp)
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addu $sp,$sp,32
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lw $31,20($sp)
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lw $fp,16($sp)
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addu $sp,$sp,24
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j $31
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.end main
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.align 2
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.globl g
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.ent g
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g:
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.frame $fp,32,$31 # vars= 16, regs= 1/0, args= 0, extra= 0
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.frame $fp,24,$31 # vars= 16, regs= 1/0, args= 0, extra= 0
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.mask 0x40000000,-16
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.fmask 0x00000000,0
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subu $sp,$sp,32
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sd $fp,16($sp)
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subu $sp,$sp,24
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sw $fp,16($sp)
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move $fp,$sp
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sw $4,0($fp)
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lw $2,0($fp)
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@ -54,7 +54,7 @@ g:
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b $L2
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$L2:
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move $sp,$fp
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ld $fp,16($sp)
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addu $sp,$sp,32
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lw $fp,16($sp)
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addu $sp,$sp,24
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j $31
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.end g
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@ -1,3 +1,8 @@
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2010-10-18 Maciej W. Rozycki <macro@linux-mips.org>
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* mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB
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macros before their corresponding MIPS III hardware instructions.
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2010-10-16 H.J. Lu <hongjiu.lu@intel.com>
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* i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS.
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@ -743,8 +743,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
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{"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
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{"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
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{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
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/* The macro has to be first to handle o32 correctly. */
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{"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
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{"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
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{"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
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{"ldaddw", "t,b", 0x70000010, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
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{"ldaddwu", "t,b", 0x70000011, 0xfc00ffff, SM|RD_t|WR_t|RD_b, 0, XLR },
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@ -1173,8 +1174,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
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{"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
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{"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
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{"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
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{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
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/* The macro has to be first to handle o32 correctly. */
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{"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
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{"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
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{"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
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{"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
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{"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
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